/dts-v1/;

#include "mt6735.dtsi"
#include "cust.dtsi"
#include "cust_eint.dtsi"
#include "mlt8735_f6h_bat_setting.dtsi"

/ {
	memory@40000000 {
		device_type = "memory";
		reg = <0 0x40000000 0 0x1F000000>;
	};

	led0:led@0 {
		compatible = "mediatek,red";
		led_mode = <0>;
		data = <1>;
		pwm_config = <0 0 0 0 0>;
	};
	led1:led@1 {
		compatible = "mediatek,green";
		led_mode = <0>;
		data = <1>;
		pwm_config = <0 0 0 0 0>;
	};
	led2:led@2 {
		compatible = "mediatek,blue";
		led_mode = <0>;
		data = <1>;
		pwm_config = <0 0 0 0 0>;
	};
	led3:led@3 {
		compatible = "mediatek,jogball-backlight";
		led_mode = <0>;
		data = <1>;
		pwm_config = <0 0 0 0 0>;
	};
	led4:led@4 {
		compatible = "mediatek,keyboard-backlight";
		led_mode = <0>;
		data = <1>;
		pwm_config = <0 0 0 0 0>;
	};
	led5:led@5 {
		compatible = "mediatek,button-backlight";
		led_mode = <0>;
		data = <1>;
		pwm_config = <0 0 0 0 0>;
	};
	led6:led@6 {
		compatible = "mediatek,lcd-backlight";
		led_mode = <5>;
		data = <1>;
		pwm_config = <0 0 0 0 0>;
	};
	vibrator0:vibrator@0 {
		compatible = "mediatek,vibrator";
		vib_timer = <25>;
		vib_limit = <9>;
		vib_vol= <5>;
	};
	cust_accel@0 {
		compatible = "mediatek,bma222e_new";
		i2c_num = <2>;
		i2c_addr = <0x18 0 0 0>;
		direction = <0>;
		power_id = <0xffff>;
		power_vol = <0>;
		firlen = <16>;
		is_batch_supported = <0>;
	};
	cust_alsps@0 {
		compatible = "mediatek,epl2182";
		i2c_num = <2>;
		i2c_addr = <0x72 0x48 0x78 0x00>;
		polling_mode_ps = <0>;
		polling_mode_als = <1>;
		power_id = <0xffff>;
		power_vol = <0>;
		als_level = <0 1 1 7 15 15 100 1000 2000 3000 6000 10000 14000 18000 20000>;
		als_value = <40 40 90 90 160 160 225 320 640 1280 1280 2600 2600 2600 10240 10240>;
		ps_threshold_high = <900>;
		ps_threshold_low = <600>;
		is_batch_supported_ps = <0>;
		is_batch_supported_als = <0>;
	};
};


&mtkfb {
	reg = <0x7e000000 0x1000000>;
};

&accdet {
		accdet-mic-vol = <7>;
		headset-mode-setting = <0x500 0x200 1 0x1F0 0x800 0x800 0x20>;
		accdet-plugout-debounce = <20>;
		/*1:ACC mode, 2:low cost without in bias, 6:low cost with in bias*/
		accdet-mic-mode = <1>;
		/*0--MD_MAX--UP_MAX--DW_MAX*/
		headset-three-key-threshold = <0 80 220 500>;
		/*0--MD_MAX--VOICE_MAX--UP_MAX--DW_MAX*/
		headset-four-key-threshold = <0 58 121 192 450>;
		/* ACCDET GPIO standardization ACC mode use */
		pinctrl-names = "default", "state_eint_as_int";
		pinctrl-0 = <&accdet_pins_default>;
		pinctrl-1 = <&accdet_pins_eint_as_int>;
		status = "okay";
};
&pio {
	accdet_pins_default: eint6default {
	};
	accdet_pins_eint_as_int: eint@6 {
		pins_cmd_dat {
			pins = <PINMUX_GPIO6__FUNC_GPIO6>;
			slew-rate = <0>;
			bias-disable;
		};
	};
};
&touch {
	tpd-resolution = <768 1024>;
	use-tpd-button = <0>;
	tpd-key-num = <3>;
	tpd-key-local= <139 172 158 0>;
	tpd-key-dim-local = <90 883 100 40 230 883 100 40 370 883 100 40 0 0 0 0>;
	tpd-max-touch-num = <5>;
	tpd-filter-enable = <1>;
	tpd-filter-pixel-density = <124>;
	tpd-filter-custom-prameters = <0 0 0 0 0 0 0 0 0 0 0 0>;
	tpd-filter-custom-speed = <0 0 0>;
	pinctrl-names = "default", "state_eint_as_int", "state_eint_output0", "state_eint_output1",
		"state_rst_output0", "state_rst_output1";
	pinctrl-0 = <&CTP_pins_default>;
	pinctrl-1 = <&CTP_pins_eint_as_int>;
	pinctrl-2 = <&CTP_pins_eint_output0>;
	pinctrl-3 = <&CTP_pins_eint_output1>;
	pinctrl-4 = <&CTP_pins_rst_output0>;
	pinctrl-5 = <&CTP_pins_rst_output1>;
	status = "okay";
};
&pio {
	alsps_intpin_cfg: alspspincfg {

	    pins_cmd_dat {
			pins = <PINMUX_GPIO65__FUNC_GPIO65>;
			slew-rate = <0>;
			bias-pull-up = <00>;
		};
	};

	alsps_intpin_default: alspsdefaultcfg {

	};
	CTP_pins_default: eint0default {
	};
	CTP_pins_eint_as_int: eint@0 {
		pins_cmd_dat {
			pins = <PINMUX_GPIO10__FUNC_GPIO10>;
			slew-rate = <0>;
			bias-disable;
		};
	};
	CTP_pins_eint_output0: eintoutput0 {
		pins_cmd_dat {
			pins = <PINMUX_GPIO10__FUNC_GPIO10>;
			slew-rate = <1>;
			output-low;
		};
	};
	CTP_pins_eint_output1: eintoutput1 {
		pins_cmd_dat {
			pins = <PINMUX_GPIO10__FUNC_GPIO10>;
			slew-rate = <1>;
			output-high;
		};
	};
	CTP_pins_rst_output0: rstoutput0 {
		pins_cmd_dat {
			pins = <PINMUX_GPIO62__FUNC_GPIO62>;
			slew-rate = <1>;
			output-low;
		};
	};
	CTP_pins_rst_output1: rstoutput1 {
		pins_cmd_dat {
			pins = <PINMUX_GPIO62__FUNC_GPIO62>;
			slew-rate = <1>;
			output-high;
		};
	};
};

&alsps {
	pinctrl-names = "pin_default", "pin_cfg";
	pinctrl-0 = <&alsps_intpin_default>;
	pinctrl-1 = <&alsps_intpin_cfg>;
	status = "okay";
};
/* TOUCH end */
/* AUDIO GPIO standardization */
&audgpio {
	pinctrl-names = "default", "audpmicclk-mode0", "audpmicclk-mode1", "audi2s1-mode0", "audi2s1-mode1", "extamp-pullhigh", "extamp-pulllow", "extamp2-pullhigh", "extamp2-pulllow", "rcvspk-pullhigh", "rcvspk-pulllow";
	pinctrl-0 = <&aud_pins_default>;
	pinctrl-1 = <&aud_pins_pmicclk_mode0>;
	pinctrl-2 = <&aud_pins_pmicclk_mode1>;
	pinctrl-3 = <&aud_pins_i2s1_mode0>;
	pinctrl-4 = <&aud_pins_i2s1_mode1>;
	pinctrl-5 = <&aud_pins_extamp_high>;
	pinctrl-6 = <&aud_pins_extamp_low>;
	pinctrl-7 = <&aud_pins_extamp2_high>;
	pinctrl-8 = <&aud_pins_extamp2_low>;
	pinctrl-9 = <&aud_pins_rcvspk_high>;
	pinctrl-10 = <&aud_pins_rcvspk_low>;
	status = "okay";
};
&pio {
	aud_pins_default: audiodefault {
	};
	aud_pins_pmicclk_mode0: pmicclkmode0 {
		pins_cmd0_dat {
			pins = <PINMUX_GPIO143__FUNC_GPIO143>;
		};
		pins_cmd1_dat {
			pins = <PINMUX_GPIO144__FUNC_GPIO144>;
		};
		pins_cmd2_dat {
			pins = <PINMUX_GPIO145__FUNC_GPIO145>;
		};
	};
	aud_pins_pmicclk_mode1: pmicclkmode1 {
		pins_cmd0_dat {
			pins = <PINMUX_GPIO143__FUNC_AUD_CLK_MOSI>;
		};
		pins_cmd1_dat {
			pins = <PINMUX_GPIO144__FUNC_AUD_DAT_MISO>;
		};
		pins_cmd2_dat {
			pins = <PINMUX_GPIO145__FUNC_AUD_DAT_MOSI>;
		};
	};
	aud_pins_i2s1_mode0: audi2s1mode0 {
		pins_cmd0_dat {
			pins = <PINMUX_GPIO78__FUNC_GPIO78>;
		};
		pins_cmd1_dat {
			pins = <PINMUX_GPIO79__FUNC_GPIO79>;
		};
		pins_cmd2_dat {
			pins = <PINMUX_GPIO80__FUNC_GPIO80>;
		};
	};
	aud_pins_i2s1_mode1: audi2s1mode1 {
		pins_cmd0_dat {
			pins = <PINMUX_GPIO78__FUNC_I2S0_DI>;
		};
		pins_cmd1_dat {
			pins = <PINMUX_GPIO79__FUNC_I2S0_LRCK>;
		};
		pins_cmd2_dat {
			pins = <PINMUX_GPIO80__FUNC_I2S0_BCK>;
		};
	};
	aud_pins_extamp_high: audexamphigh {
		pins_cmd_dat {
			pins = <PINMUX_GPIO129__FUNC_GPIO129>;
			slew-rate = <1>;
			output-high;
		};
	};
	aud_pins_extamp_low: audexamplow {
		pins_cmd_dat {
			pins = <PINMUX_GPIO129__FUNC_GPIO129>;
			slew-rate = <1>;
			output-low;
		};
	};
	aud_pins_extamp2_high: audexam2phigh {
		pins_cmd_dat {
			pins = <PINMUX_GPIO128__FUNC_GPIO128>;
			slew-rate = <1>;
			output-high;
		};
	};
	aud_pins_extamp2_low: audexamp2low {
		pins_cmd_dat {
			pins = <PINMUX_GPIO128__FUNC_GPIO128>;
			slew-rate = <1>;
			output-low;
		};
	};
	aud_pins_rcvspk_high: audrcvspkhigh {
		pins_cmd_dat {
			pins = <PINMUX_GPIO120__FUNC_GPIO120>;
			slew-rate = <1>;
			output-low; /*set low for receiver out*/
		};
	};
	aud_pins_rcvspk_low: audrcvspklow {
		pins_cmd_dat {
			pins = <PINMUX_GPIO120__FUNC_GPIO120>;
			slew-rate = <1>;
			output-high; /*set high for speaker out*/
		};
	};
};
/* AUDIO end */

/* CAMERA GPIO begin */
&pio {
	camera_pins_cam0_rst0: cam0@0 {
		pins_cmd_dat {
			pins = <PINMUX_GPIO44__FUNC_GPIO44>;/*GPIO_CAMERA_CMRST_PIN*/
			slew-rate = <1>; /*direction 0:in, 1:out*/
			output-low;/*direction out used only. output_low or high*/
		};
	};
	camera_pins_cam0_rst1: cam0@1 {
		pins_cmd_dat {
			pins = <PINMUX_GPIO44__FUNC_GPIO44>;/*GPIO_CAMERA_CMRST_PIN*/
			slew-rate = <1>;
			output-high;
		};
	};
	camera_pins_cam0_pnd0: cam0@2 {
		pins_cmd_dat {
			pins = <PINMUX_GPIO7__FUNC_GPIO7>;/*GPIO_CAMERA_CMPDN_PIN*/
			slew-rate = <1>;
			output-low;
		};
	};
	camera_pins_cam0_pnd1: cam0@3 {
		pins_cmd_dat {
			pins = <PINMUX_GPIO7__FUNC_GPIO7>;/*GPIO_CAMERA_CMPDN_PIN*/
			slew-rate = <1>;
			output-high;
		};
	};
	camera_pins_cam1_rst0: cam1@0 {
		pins_cmd_dat {
			pins = <PINMUX_GPIO11__FUNC_GPIO11>;/*GPIO_CAMERA_CMRST1_PIN*/
			slew-rate = <1>; /*direction 0:in, 1:out*/
			output-low;/*direction out used only. output_low or high*/
		};
	};
	camera_pins_cam1_rst1: cam1@1 {
		pins_cmd_dat {
			pins = <PINMUX_GPIO11__FUNC_GPIO11>;/*GPIO_CAMERA_CMRST1_PIN*/
			slew-rate = <1>;
			output-high;
		};
	};
	camera_pins_cam1_pnd0: cam1@2 {
		pins_cmd_dat {
			pins = <PINMUX_GPIO12__FUNC_GPIO12>;/*GPIO_CAMERA_CMPDN1_PIN*/
			slew-rate = <1>;
			output-low;
		};
	};
	camera_pins_cam1_pnd1: cam1@3 {
		pins_cmd_dat {
			pins = <PINMUX_GPIO12__FUNC_GPIO12>;/*GPIO_CAMERA_CMPDN1_PIN*/
			slew-rate = <1>;
			output-high;
		};
	};
	camera_pins_default: camdefault {

	};
};

&kd_camera_hw1 {
	pinctrl-names = "cam_default", "cam0_rst0", "cam0_rst1", "cam0_pnd0", "cam0_pnd1",
	"cam1_rst0", "cam1_rst1", "cam1_pnd0", "cam1_pnd1";
	pinctrl-0 = <&camera_pins_default>;
	pinctrl-1 = <&camera_pins_cam0_rst0>;
	pinctrl-2 = <&camera_pins_cam0_rst1>;
	pinctrl-3 = <&camera_pins_cam0_pnd0>;
	pinctrl-4 = <&camera_pins_cam0_pnd1>;
	pinctrl-5 = <&camera_pins_cam1_rst0>;
	pinctrl-6 = <&camera_pins_cam1_rst1>;
	pinctrl-7 = <&camera_pins_cam1_pnd0>;
	pinctrl-8 = <&camera_pins_cam1_pnd1>;
	status = "okay";

};
/* CAMERA GPIO end */

/* LCM GPIO set */
&dispsys {
	lcm_power_gpio = <&pio 1 0>;
	lcm_bl_gpio = <&pio 3 0>;
};
/* LCM end */

/* CONSYS GPIO standardization */
&pio {
	consys_pins_default: default {

	};

	gpslna_pins_init: gpslna@0 {

	    pins_cmd_dat {
			pins = <PINMUX_GPIO79__FUNC_GPIO79>;
			slew-rate = <0>;
			bias-disable;
			output-low;
		};
	};

	gpslna_pins_oh: gpslna@1 {

	    pins_cmd_dat {
			pins = <PINMUX_GPIO79__FUNC_GPIO79>;
			slew-rate = <1>;
			output-high;
		};
	};

	gpslna_pins_ol: gpslna@2 {

	    pins_cmd_dat {
			pins = <PINMUX_GPIO79__FUNC_GPIO79>;
			slew-rate = <1>;
			output-low;
		};
	};

};

&consys {
	pinctrl-names = "default", "gps_lna_state_init", "gps_lna_state_oh", "gps_lna_state_ol";
	pinctrl-0 = <&consys_pins_default>;
	pinctrl-1 = <&gpslna_pins_init>;
	pinctrl-2 = <&gpslna_pins_oh>;
	pinctrl-3 = <&gpslna_pins_ol>;
	status = "okay";

};
/* CONSYS end */

/* mmc start */
&mmc0 {
		clk_src = /bits/ 8 <MSDC50_CLKSRC_400MHZ>;
		bus-width = <8>;
		max-frequency = <200000000>;
		cap-mmc-highspeed;
		msdc-sys-suspend;
		mmc-ddr-1_8v;
		mmc-hs200-1_8v;
		mmc-hs400-1_8v;
		non-removable;
		pinctl = <&mmc0_pins_default>;
		register_setting = <&mmc0_register_setting_default>;
		host_function = /bits/ 8 <MSDC_EMMC>;
		bootable;
		status = "okay";
};

&mmc1 {
		clk_src = /bits/ 8 <MSDC30_CLKSRC_200MHZ>;
		bus-width = <4>;
		max-frequency = <200000000>;
		msdc-sys-suspend;
		cap-sd-highspeed;
		sd-uhs-sdr12;
		sd-uhs-sdr25;
		sd-uhs-sdr50;
		sd-uhs-sdr104;
		sd-uhs-ddr50;
		pinctl = <&mmc1_pins_default>;
		pinctl_sdr104 = <&mmc1_pins_sdr104>;
		pinctl_sdr50 = <&mmc1_pins_sdr50>;
		pinctl_ddr50 = <&mmc1_pins_ddr50>;
		register_setting = <&mmc1_register_setting_default>;
		host_function = /bits/ 8 <MSDC_SD>;
		cd_level = /bits/ 8 <MSDC_CD_LOW>;
		cd-gpios = <&pio 5 0>;
		status = "okay";
};

&pio {
	mmc0_pins_default: mmc0@default {
			pins_cmd {
				drive-strength = /bits/ 8 <2>;
			};
			pins_dat {
				drive-strength = /bits/ 8 <2>;
			};
			pins_clk {
				drive-strength = /bits/ 8 <2>;
			};
			pins_rst {
				drive-strength = /bits/ 8 <2>;
			};
			pins_ds {
				drive-strength = /bits/ 8 <2>;
			};
	};

	mmc0_register_setting_default: mmc0@register_default {
		dat0rddly      = /bits/ 8 <0>;
		dat1rddly      = /bits/ 8 <0>;
		dat2rddly      = /bits/ 8 <0>;
		dat3rddly      = /bits/ 8 <0>;
		dat4rddly      = /bits/ 8 <0>;
		dat5rddly      = /bits/ 8 <0>;
		dat6rddly      = /bits/ 8 <0>;
		dat7rddly      = /bits/ 8 <0>;
		datwrddly      = /bits/ 8 <0>;
		cmdrrddly      = /bits/ 8 <0>;
		cmdrddly       = /bits/ 8 <0>;
		cmd_edge = /bits/ 8 <MSDC_SMPL_FALLING>;
		rdata_edge = /bits/ 8 <MSDC_SMPL_FALLING>;
		wdata_edge = /bits/ 8 <MSDC_SMPL_FALLING>;

		ett-hs200-cells = <12>;
		ett-hs200-default = <OFFSET_MSDC_PATCH_BIT0	MSDC_PB0_INT_DAT_LATCH_CK_SEL 0x0
			OFFSET_MSDC_PATCH_BIT0	MSDC_PB0_CKGEN_MSDC_DLY_SEL   0x0
			OFFSET_MSDC_PATCH_BIT1	MSDC_PB1_CMD_RSP_TA_CNTR      0x1
			OFFSET_MSDC_IOCON		MSDC_IOCON_RSPL               0x0
			OFFSET_MSDC_PAD_TUNE0	MSDC_PAD_TUNE0_CMDRDLY        0x7
			OFFSET_MSDC_PAD_TUNE0	MSDC_PAD_TUNE0_CMDRRDLY       0xb
			OFFSET_MSDC_PATCH_BIT1		MSDC_PB1_WRDAT_CRCS_TA_CNTR   0x1
			OFFSET_MSDC_PAD_TUNE0	MSDC_PAD_TUNE0_DATWRDLY       0xb
			OFFSET_MSDC_IOCON			MSDC_IOCON_W_D0SPL            0x0
			OFFSET_MSDC_DAT_RDDLY0		MSDC_DAT_RDDLY0_D0            0x7
			OFFSET_MSDC_PAD_TUNE0	MSDC_PAD_TUNE0_DATRRDLY       0x9
			OFFSET_MSDC_IOCON		MSDC_IOCON_R_D_SMPL           0x0>;

		ett-hs400-cells = <8>;
		ett-hs400-default = <OFFSET_MSDC_PATCH_BIT0	MSDC_PB0_INT_DAT_LATCH_CK_SEL	0x0
			OFFSET_MSDC_PATCH_BIT0		MSDC_PB0_CKGEN_MSDC_DLY_SEL		0x0
			OFFSET_EMMC50_PAD_DS_TUNE	MSDC_EMMC50_PAD_DS_TUNE_DLY1	0x2
			OFFSET_EMMC50_PAD_DS_TUNE	MSDC_EMMC50_PAD_DS_TUNE_DLY3	0x10
			OFFSET_MSDC_PATCH_BIT1			MSDC_PB1_CMD_RSP_TA_CNTR	0x1
			OFFSET_MSDC_IOCON		MSDC_IOCON_RSPL				0x0
			OFFSET_MSDC_PAD_TUNE0			MSDC_PAD_TUNE0_CMDRDLY		0x6
			OFFSET_MSDC_PAD_TUNE0		MSDC_PAD_TUNE0_CMDRRDLY		0x6>;
	};

	mmc1_pins_default: mmc1@default {
			pins_cmd {
				drive-strength = /bits/ 8 <3>;
			};
			pins_dat {
				drive-strength = /bits/ 8 <3>;
			};
			pins_clk {
				drive-strength = /bits/ 8 <3>;
			};
	};

	mmc1_pins_sdr104: mmc1@sdr104 {
			pins_cmd {
				drive-strength = /bits/ 8 <2>;
			};
			pins_dat {
				drive-strength = /bits/ 8 <2>;
			};
			pins_clk {
				drive-strength = /bits/ 8 <3>;
			};
	};

	mmc1_pins_sdr50: mmc1@sdr50 {
			pins_cmd {
				drive-strength = /bits/ 8 <2>;
			};
			pins_dat {
				drive-strength = /bits/ 8 <2>;
			};
			pins_clk {
				drive-strength = /bits/ 8 <3>;
			};
	};

	mmc1_pins_ddr50: mmc1@ddr50 {
			pins_cmd {
				drive-strength = /bits/ 8 <2>;
			};
			pins_dat {
				drive-strength = /bits/ 8 <2>;
			};
			pins_clk {
				drive-strength = /bits/ 8 <3>;
			};
	};

	mmc1_register_setting_default: mmc1@register_default {
				dat0rddly      = /bits/ 8 <0>;
				dat1rddly      = /bits/ 8 <0>;
				dat2rddly      = /bits/ 8 <0>;
				dat3rddly      = /bits/ 8 <0>;
				datwrddly      = /bits/ 8 <0>;
				cmdrrddly      = /bits/ 8 <0>;
				cmdrddly       = /bits/ 8 <0>;
				cmd_edge = /bits/ 8 <MSDC_SMPL_FALLING>;
				rdata_edge = /bits/ 8 <MSDC_SMPL_FALLING>;
				wdata_edge = /bits/ 8 <MSDC_SMPL_FALLING>;
	};
};
/* mmc end */
/* USB GPIO Kernal Standardization start */
&pio {
	usb_default: usb_default {
	};

	gpio0_mode1_iddig: iddig_irq_init {
		pins_cmd_dat {
			pins = <PINMUX_GPIO0__FUNC_IDDIG>;
			slew-rate = <0>;
			bias-pull-up = <00>;
		};
	};

	gpio83_mode2_drvvbus: drvvbus_init {
		pins_cmd_dat {
			pins = <PINMUX_GPIO83__FUNC_USB_DRVVBUS>;
			slew-rate = <1>;
			bias-pull-up = <00>;
		};
	};

	gpio83_mode2_drvvbus_low: drvvbus_low {
		pins_cmd_dat {
			pins = <PINMUX_GPIO83__FUNC_USB_DRVVBUS>;
			slew-rate = <1>;
			output-low;
		};
	};

	gpio83_mode2_drvvbus_high: drvvbus_high {
		pins_cmd_dat {
			pins = <PINMUX_GPIO83__FUNC_USB_DRVVBUS>;
			slew-rate = <1>;
			output-high;
		};
	};
};

&usb0 {
	pinctrl-names = "usb_default", "iddig_irq_init", "drvvbus_init", "drvvbus_low", "drvvbus_high";
	pinctrl-0 = <&usb_default>;
	pinctrl-1 = <&gpio0_mode1_iddig>;
	pinctrl-2 = <&gpio83_mode2_drvvbus>;
	pinctrl-3 = <&gpio83_mode2_drvvbus_low>;
	pinctrl-4 = <&gpio83_mode2_drvvbus_high>;
	status = "okay";
};
/* USB GPIO Kernal Standardization end */

/* i2c start */
&i2c3 {
	bq24296@6b {
		status = "okay";
		compatible = "bq24296";
		reg = <0x6b>;
	};

	ts3a225e@3b {
		compatible = "mediatek,ts3a225e";
		reg = <0x3b>;
		status = "okay";
	};
};
/* i2c end */