#ifndef _DDP_REG_H_ #define _DDP_REG_H_ #include /* #include */ #include #include "display_recorder.h" #include "cmdq_record.h" #include "cmdq_core.h" #include "ddp_hal.h" #include "ddp_log.h" #include "ddp_path.h" /* MIPITX and DSI */ #define ENABLE_CLK_MGR #define DDP_ENING_NUM (13) #define DDP_MOUT_NUM 4 #define DDP_SEL_OUT_NUM 2 #define DDP_SEL_IN_NUM 5 #define DDP_MUTEX_MAX 5 #ifdef DISP_LIST_SCENARIO static unsigned int module_list_scenario[DDP_SCENARIO_MAX][DDP_ENING_NUM] = { /*PRIMARY_DISP*/ {DISP_MODULE_OVL0, DISP_MODULE_COLOR0, DISP_MODULE_CCORR, DISP_MODULE_AAL, DISP_MODULE_GAMMA, DISP_MODULE_OD, DISP_MODULE_DITHER, DISP_MODULE_RDMA0, DISP_MODULE_PWM0, DISP_MODULE_DSI0, -1, -1, -1}, /*PRIMARY_RDMA0_COLOR0_DISP*/ {DISP_MODULE_RDMA0, DISP_MODULE_COLOR0, DISP_MODULE_CCORR, DISP_MODULE_AAL, DISP_MODULE_GAMMA, DISP_MODULE_OD, DISP_MODULE_DITHER, DISP_MODULE_UFOE, DISP_MODULE_PWM0, DISP_MODULE_DSI0, -1, -1, -1}, /*PRIMARY_RDMA0_DISP*/ {DISP_MODULE_RDMA0, DISP_MODULE_PWM0, DISP_MODULE_DSI0, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /*PRIMARY_BYPASS_RDMA*/ {DISP_MODULE_OVL0, DISP_MODULE_COLOR0, DISP_MODULE_CCORR, DISP_MODULE_AAL, DISP_MODULE_GAMMA, DISP_MODULE_OD, DISP_MODULE_DITHER, DISP_MODULE_UFOE, DISP_MODULE_PWM0, DISP_MODULE_DSI0, -1, -1, -1}, /*PRIMARY_OVL_MEMOUT*/ {DISP_MODULE_OVL0, DISP_MODULE_WDMA0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /*PRIMARY_DITHER_MEMOUT*/ {DISP_MODULE_OVL0, DISP_MODULE_COLOR0, DISP_MODULE_CCORR, DISP_MODULE_AAL, DISP_MODULE_GAMMA, DISP_MODULE_OD, DISP_MODULE_DITHER, DISP_MODULE_WDMA0, -1, -1, -1, -1, -1}, /*PRIMARY_UFOE_MEMOUT*/ {DISP_MODULE_OVL0, DISP_MODULE_COLOR0, DISP_MODULE_CCORR, DISP_MODULE_AAL, DISP_MODULE_GAMMA, DISP_MODULE_OD, DISP_MODULE_DITHER, DISP_MODULE_RDMA0, DISP_MODULE_UFOE, DISP_MODULE_WDMA0, -1, -1, -1}, /*SUB_DISP*/ {DISP_MODULE_OVL1, DISP_MODULE_RDMA1, DISP_MODULE_DPI, -1, -1, -1, -1, -1, -1, -1, -1, -1}, #ifndef CONFIG_FPGA_EARLY_PORTING /*SUB_RDMA1_DISP*/ {DISP_MODULE_RDMA1, DISP_MODULE_DPI, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, #else /*SUB_RDMA1_DISP*/ {DISP_MODULE_RDMA1, DISP_MODULE_DSI0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, #endif /*SUB_OVL_MEMOUT*/ {DISP_MODULE_OVL1, DISP_MODULE_WDMA1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /*PRIMARY_ALL*/ {DISP_MODULE_OVL0, DISP_MODULE_WDMA0, DISP_MODULE_COLOR0, DISP_MODULE_CCORR, DISP_MODULE_AAL, DISP_MODULE_GAMMA, DISP_MODULE_OD, DISP_MODULE_DITHER, DISP_MODULE_RDMA0, DISP_MODULE_PWM0, DISP_MODULE_DSI0, -1, -1}, /*SUB_ALL*/ {DISP_MODULE_OVL1, DISP_MODULE_WDMA1, DISP_MODULE_RDMA1, DISP_MODULE_DPI, -1, -1, -1, -1, -1, -1, -1, -1}, /*MULTIPLE_OVL*/ {DISP_MODULE_OVL1, DISP_MODULE_OVL0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, }; #endif /* 1st para is mout's input, 2nd para is mout's output */ extern mout_t mout_map[DDP_MOUT_NUM]; extern sel_t sel_out_map[DDP_SEL_OUT_NUM]; /* 1st para is sout's output, 2nd para is sout's input */ extern sel_t sel_in_map[DDP_SEL_IN_NUM]; /* from DTS, for debug */ static const unsigned int ddp_reg_pa_base[DISP_REG_NUM] = { 0x14007000, 0x14008000, 0x14009000, 0x1400A000, 0x1400B000, 0x1400C000, 0x1400D000, 0x1400E000, 0x1400F000, 0x14010000, 0, 0x1100E000, 0, 0x14015000, 0x14013000, 0x14014000, 0x14000000, 0x14016000, 0x14017000, 0x14018000, 0x10206000, 0x10210000, 0x10211A70, 0x10211974, 0x10211B70, 0x10206044, 0x10206514, 0x10206558, 0x102100A0, 0x10209270, 0x10209274, 0x14012000, 0x10209000 }; static const unsigned int ddp_irq_num[DISP_REG_NUM] = { 193, 211, 194, 195, 196, 197, 198, 199, 200, 201, 0, 117, 0, 186, 203, 204, 205, 176, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 210, 0 }; /* module bit in mutex */ static const module_map_t module_mutex_map[DISP_MODULE_NUM] = { {DISP_MODULE_OVL0, 6}, {DISP_MODULE_OVL1, 7}, {DISP_MODULE_RDMA0, 8}, {DISP_MODULE_RDMA1, 9}, {DISP_MODULE_WDMA0, 10}, {DISP_MODULE_COLOR0, 12}, {DISP_MODULE_CCORR, 11}, {DISP_MODULE_AAL, 13}, {DISP_MODULE_GAMMA, 14}, {DISP_MODULE_DITHER, 15}, {DISP_MODULE_UFOE, -1}, {DISP_MODULE_PWM0, 17}, {DISP_MODULE_WDMA1, -1}, {DISP_MODULE_DSI0, -1}, {DISP_MODULE_DPI, -1}, {DISP_MODULE_SMI, -1}, {DISP_MODULE_CONFIG, -1}, {DISP_MODULE_CMDQ, -1}, {DISP_MODULE_MUTEX, -1}, {DISP_MODULE_COLOR1, -1}, {DISP_MODULE_RDMA2, -1}, {DISP_MODULE_PWM1, -1}, {DISP_MODULE_OD, 18}, }; /* module can be connect if 1 */ static const module_map_t module_can_connect[DISP_MODULE_NUM] = { {DISP_MODULE_OVL0, 1}, {DISP_MODULE_OVL1, 1}, {DISP_MODULE_RDMA0, 1}, {DISP_MODULE_RDMA1, 1}, {DISP_MODULE_WDMA0, 1}, {DISP_MODULE_COLOR0, 1}, {DISP_MODULE_CCORR, 1}, {DISP_MODULE_AAL, 1}, {DISP_MODULE_GAMMA, 1}, {DISP_MODULE_DITHER, 1}, {DISP_MODULE_UFOE, 1}, {DISP_MODULE_PWM0, 0}, {DISP_MODULE_WDMA1, 0}, {DISP_MODULE_DSI0, 1}, {DISP_MODULE_DPI, 1}, {DISP_MODULE_SMI, 0}, {DISP_MODULE_CONFIG, 0}, {DISP_MODULE_CMDQ, 0}, {DISP_MODULE_MUTEX, 0}, {DISP_MODULE_COLOR1, 0}, {DISP_MODULE_RDMA2, 0}, {DISP_MODULE_PWM1, 0}, {DISP_MODULE_OD, 1}, {DISP_MODULE_MERGE, 0}, {DISP_MODULE_SPLIT0, 0}, {DISP_MODULE_SPLIT1, 0}, {DISP_MODULE_DSI1, 0}, {DISP_MODULE_DSIDUAL, 0}, {DISP_MODULE_SMI_LARB0, 0}, {DISP_MODULE_SMI_COMMON, 0}, {DISP_MODULE_UNKNOWN, 0}, }; struct MIPITX_DSI_CON_REG { unsigned RG_DSI_LDOCORE_EN:1; unsigned RG_DSI_CKG_LDOOUT_EN:1; unsigned RG_DSI_BCLK_SEL:2; unsigned RG_DSI_LD_IDX_SEL:3; unsigned rsv_7:1; unsigned RG_DSI_PHYCLK_SEL:2; unsigned RG_DSI_DSICLK_FREQ_SEL:1; unsigned RG_DSI_LPTX_CLMP_EN:1; unsigned rsv_12:20; }; struct MIPITX_DSI_CLOCK_LANE_REG { unsigned RG_DSI_LNTC_LDOOUT_EN:1; unsigned RG_DSI_LNTC_LOOPBACK_EN:1; unsigned RG_DSI_LNTC_LPTX_IPLUS1:1; unsigned RG_DSI_LNTC_LPTX_IPLUS2:1; unsigned RG_DSI_LNTC_LPTX_IMINUS:1; unsigned RG_DSI_LNTC_PHY_SEL:1; unsigned rsv_6:2; unsigned RG_DSI_LNTC_RT_CODE:4; unsigned rsv_12:20; }; struct MIPITX_DSI_DATA_LANE0_REG { unsigned RG_DSI_LNT0_LDOOUT_EN:1; unsigned RG_DSI_LNT0_LOOPBACK_EN:1; unsigned RG_DSI_LNT0_LPTX_IPLUS1:1; unsigned RG_DSI_LNT0_LPTX_IPLUS2:1; unsigned RG_DSI_LNT0_LPTX_IMINUS:1; unsigned RG_DSI_LNT0_LPCD_IPLUS:1; unsigned RG_DSI_LNT0_LPCD_IMINUS:1; unsigned RG_DSI_LNT0_RT_CODE:4; unsigned rsv_11:21; }; struct MIPITX_DSI_DATA_LANE1_REG { unsigned RG_DSI_LNT1_LDOOUT_EN:1; unsigned RG_DSI_LNT1_LOOPBACK_EN:1; unsigned RG_DSI_LNT1_LPTX_IPLUS1:1; unsigned RG_DSI_LNT1_LPTX_IPLUS2:1; unsigned RG_DSI_LNT1_LPTX_IMINUS:1; unsigned RG_DSI_LNT1_RT_CODE:4; unsigned rsv_9:23; }; struct MIPITX_DSI_DATA_LANE2_REG { unsigned RG_DSI_LNT2_LDOOUT_EN:1; unsigned RG_DSI_LNT2_LOOPBACK_EN:1; unsigned RG_DSI_LNT2_LPTX_IPLUS1:1; unsigned RG_DSI_LNT2_LPTX_IPLUS2:1; unsigned RG_DSI_LNT2_LPTX_IMINUS:1; unsigned RG_DSI_LNT2_RT_CODE:4; unsigned rsv_9:23; }; struct MIPITX_DSI_DATA_LANE3_REG { unsigned RG_DSI_LNT3_LDOOUT_EN:1; unsigned RG_DSI_LNT3_LOOPBACK_EN:1; unsigned RG_DSI_LNT3_LPTX_IPLUS1:1; unsigned RG_DSI_LNT3_LPTX_IPLUS2:1; unsigned RG_DSI_LNT3_LPTX_IMINUS:1; unsigned RG_DSI_LNT3_RT_CODE:4; unsigned rsv_9:23; }; struct MIPITX_DSI_TOP_CON_REG { unsigned RG_DSI_LNT_INTR_EN:1; unsigned RG_DSI_LNT_HS_BIAS_EN:1; unsigned RG_DSI_LNT_IMP_CAL_EN:1; unsigned RG_DSI_LNT_TESTMODE_EN:1; unsigned RG_DSI_LNT_IMP_CAL_CODE:4; unsigned RG_DSI_LNT_AIO_SEL:3; unsigned RG_DSI_PAD_TIE_LOW_EN:1; unsigned RG_DSI_DEBUG_INPUT_EN:1; unsigned RG_DSI_PRESERVE:3; unsigned rsv_16:16; }; struct MIPITX_DSI_BG_CON_REG { unsigned RG_DSI_BG_CORE_EN:1; unsigned RG_DSI_BG_CKEN:1; unsigned RG_DSI_BG_DIV:2; unsigned RG_DSI_BG_FAST_CHARGE:1; unsigned RG_DSI_V12_SEL:3; unsigned RG_DSI_V10_SEL:3; unsigned RG_DSI_V072_SEL:3; unsigned RG_DSI_V04_SEL:3; unsigned RG_DSI_V032_SEL:3; unsigned RG_DSI_V02_SEL:3; unsigned rsv_23:1; unsigned RG_DSI_BG_R1_TRIM:4; unsigned RG_DSI_BG_R2_TRIM:4; }; struct MIPITX_DSI_PLL_CON0_REG { unsigned RG_DSI0_MPPLL_PLL_EN:1; unsigned RG_DSI0_MPPLL_PREDIV:2; unsigned RG_DSI0_MPPLL_TXDIV0:2; unsigned RG_DSI0_MPPLL_TXDIV1:2; unsigned RG_DSI0_MPPLL_POSDIV:3; unsigned RG_DSI0_MPPLL_MONVC_EN:1; unsigned RG_DSI0_MPPLL_MONREF_EN:1; unsigned RG_DSI0_MPPLL_VDO_EN:1; unsigned rsv_13:19; }; struct MIPITX_DSI_PLL_CON1_REG { unsigned RG_DSI0_MPPLL_SDM_FRA_EN:1; unsigned RG_DSI0_MPPLL_SDM_SSC_PH_INIT:1; unsigned RG_DSI0_MPPLL_SDM_SSC_EN:1; unsigned rsv_3:13; unsigned RG_DSI0_MPPLL_SDM_SSC_PRD:16; }; struct MIPITX_DSI_PLL_CON2_REG { unsigned RG_DSI0_MPPLL_SDM_PCW_0_7:8; unsigned RG_DSI0_MPPLL_SDM_PCW_8_15:8; unsigned RG_DSI0_MPPLL_SDM_PCW_16_23:8; unsigned RG_DSI0_MPPLL_SDM_PCW_H:7; unsigned rsv_31:1; }; struct MIPITX_DSI_PLL_CON3_REG { unsigned RG_DSI0_MPPLL_SDM_SSC_DELTA1:16; unsigned RG_DSI0_MPPLL_SDM_SSC_DELTA:16; }; struct MIPITX_DSI_PLL_CHG_REG { unsigned RG_DSI0_MPPLL_SDM_PCW_CHG:1; unsigned rsv_1:31; }; struct MIPITX_DSI_PLL_TOP_REG { unsigned RG_MPPLL_TST_EN:1; unsigned RG_MPPLL_TSTCK_EN:1; unsigned RG_MPPLL_TSTSEL:2; unsigned RG_MPPLL_S2QDIV:2; unsigned RG_MPPLL_PLLOUT_EN:1; unsigned RG_MPPLL_PRESERVE:5; unsigned rsv_12:20; }; struct MIPITX_DSI_PLL_PWR_REG { unsigned DA_DSI_MPPLL_SDM_PWR_ON:1; unsigned DA_DSI_MPPLL_SDM_ISO_EN:1; unsigned rsv_2:6; unsigned AD_DSI0_MPPLL_SDM_PWR_ACK:1; unsigned rsv_9:23; }; struct MIPITX_DSI_RGS_REG { unsigned RGS_DSI_LNT_IMP_CAL_OUTPUT:1; unsigned rsv_1:31; }; struct MIPITX_DSI_GPI_EN_REG { unsigned RG_DSI0_GPI0_EN:1; unsigned RG_DSI0_GPI1_EN:1; unsigned RG_DSI0_GPI2_EN:1; unsigned RG_DSI0_GPI3_EN:1; unsigned RG_DSI0_GPI4_EN:1; unsigned RG_DSI0_GPI5_EN:1; unsigned RG_DSI0_GPI6_EN:1; unsigned RG_DSI0_GPI7_EN:1; unsigned RG_DSI0_GPI8_EN:1; unsigned RG_DSI0_GPI9_EN:1; unsigned RG_DSI0_GPI_SMT_EN:1; unsigned RG_DSI0_GPI_DRIVE_EN:1; unsigned rsv_12:20; }; struct MIPITX_DSI_GPI_PULL_REG { unsigned RG_DSI0_GPI0_PD:1; unsigned RG_DSI0_GPI1_PD:1; unsigned RG_DSI0_GPI2_PD:1; unsigned RG_DSI0_GPI3_PD:1; unsigned RG_DSI0_GPI4_PD:1; unsigned RG_DSI0_GPI5_PD:1; unsigned RG_DSI0_GPI6_PD:1; unsigned RG_DSI0_GPI7_PD:1; unsigned RG_DSI0_GPI8_PD:1; unsigned RG_DSI0_GPI9_PD:1; unsigned rsv_10:6; unsigned RG_DSI0_GPI0_PU:1; unsigned RG_DSI0_GPI1_PU:1; unsigned RG_DSI0_GPI2_PU:1; unsigned RG_DSI0_GPI3_PU:1; unsigned RG_DSI0_GPI4_PU:1; unsigned RG_DSI0_GPI5_PU:1; unsigned RG_DSI0_GPI6_PU:1; unsigned RG_DSI0_GPI7_PU:1; unsigned RG_DSI0_GPI8_PU:1; unsigned RG_DSI0_GPI9_PU:1; unsigned rsv_26:6; }; struct MIPITX_DSI_PHY_SEL_REG { unsigned MIPI_TX_PHY0_SEL:3; unsigned rsv_3:1; unsigned MIPI_TX_PHY1_SEL:3; unsigned rsv_7:1; unsigned MIPI_TX_PHY2_SEL:3; unsigned rsv_11:1; unsigned MIPI_TX_PHY3_SEL:3; unsigned rsv_15:1; unsigned MIPI_TX_PHYC_SEL:3; unsigned rsv_19:1; unsigned MIPI_TX_LPRX_SEL:3; unsigned rsv_23:9; }; struct MIPITX_DSI_SW_CTRL_REG { unsigned SW_CTRL_EN:1; unsigned rsv_1:31; }; struct MIPITX_DSI_SW_CTRL_CON0_REG { unsigned SW_LNTC_LPTX_PRE_OE:1; unsigned SW_LNTC_LPTX_OE:1; unsigned SW_LNTC_LPTX_DP:1; unsigned SW_LNTC_LPTX_DN:1; unsigned SW_LNTC_HSTX_PRE_OE:1; unsigned SW_LNTC_HSTX_OE:1; unsigned SW_LNTC_HSTX_RDY:1; unsigned SW_LNTC_LPRX_EN:1; unsigned SW_LNTC_HSTX_DATA:8; unsigned rsv_16:16; }; struct MIPITX_DSI_SW_CTRL_CON1_REG { unsigned SW_LNT0_LPTX_PRE_OE:1; unsigned SW_LNT0_LPTX_OE:1; unsigned SW_LNT0_LPTX_DP:1; unsigned SW_LNT0_LPTX_DN:1; unsigned SW_LNT0_HSTX_PRE_OE:1; unsigned SW_LNT0_HSTX_OE:1; unsigned SW_LNT0_HSTX_RDY:1; unsigned SW_LNT0_LPRX_EN:1; unsigned SW_LNT1_LPTX_PRE_OE:1; unsigned SW_LNT1_LPTX_OE:1; unsigned SW_LNT1_LPTX_DP:1; unsigned SW_LNT1_LPTX_DN:1; unsigned SW_LNT1_HSTX_PRE_OE:1; unsigned SW_LNT1_HSTX_OE:1; unsigned SW_LNT1_HSTX_RDY:1; unsigned SW_LNT1_LPRX_EN:1; unsigned SW_LNT2_LPTX_PRE_OE:1; unsigned SW_LNT2_LPTX_OE:1; unsigned SW_LNT2_LPTX_DP:1; unsigned SW_LNT2_LPTX_DN:1; unsigned SW_LNT2_HSTX_PRE_OE:1; unsigned SW_LNT2_HSTX_OE:1; unsigned SW_LNT2_HSTX_RDY:1; unsigned SW_LNT2_LPRX_EN:1; unsigned SW_LNT3_LPTX_PRE_OE:1; unsigned SW_LNT3_LPTX_OE:1; unsigned SW_LNT3_LPTX_DP:1; unsigned SW_LNT3_LPTX_DN:1; unsigned SW_LNT3_HSTX_PRE_OE:1; unsigned SW_LNT3_HSTX_OE:1; unsigned SW_LNT3_HSTX_RDY:1; unsigned SW_LNT3_LPRX_EN:1; }; struct MIPITX_DSI_SW_CTRL_CON2_REG { unsigned SW_LNT_HSTX_DATA:8; unsigned rsv_8:24; }; struct MIPITX_DSI_DBG_CON_REG { unsigned MIPI_TX_DBG_SEL:4; unsigned MIPI_TX_DBG_OUT_EN:1; unsigned MIPI_TX_GPIO_MODE_EN:1; unsigned MIPI_TX_APB_ASYNC_CNT_EN:1; unsigned rsv_7:25; }; struct MIPITX_DSI_APB_ASYNC_STA_REG { unsigned MIPI_TX_APB_ASYNC_ERR:1; unsigned MIPI_TX_APB_ASYNC_ERR_ADDR:10; unsigned rsv_11:21; }; struct DSI_START_REG { unsigned DSI_START:1; unsigned rsv_1:1; unsigned SLEEPOUT_START:1; unsigned SKEWCAL_START:1; unsigned rsv_4:12; unsigned VM_CMD_START:1; unsigned rsv_17:15; }; struct DSI_STATUS_REG { unsigned rsv_0:1; unsigned BUF_UNDERRUN:1; unsigned rsv_2:2; unsigned ESC_ENTRY_ERR:1; unsigned ESC_SYNC_ERR:1; unsigned CTRL_ERR:1; unsigned CONTENT_ERR:1; unsigned rsv_8:24; }; struct DSI_INT_ENABLE_REG { unsigned RD_RDY:1; unsigned CMD_DONE:1; unsigned TE_RDY:1; unsigned VM_DONE:1; unsigned FRAME_DONE_INT_EN:1; unsigned VM_CMD_DONE:1; unsigned SLEEPOUT_DONE:1; unsigned TE_TIMEOUT_INT_EN:1; unsigned VM_VBP_STR_INT_EN:1; unsigned VM_VACT_STR_INT_EN:1; unsigned VM_VFP_STR_INT_EN:1; unsigned SKEWCAL_DONE_INT_EN:1; unsigned rsv_12:20; }; struct DSI_INT_STATUS_REG { unsigned RD_RDY:1; unsigned CMD_DONE:1; unsigned TE_RDY:1; unsigned VM_DONE:1; unsigned FRAME_DONE_INT_EN:1; unsigned VM_CMD_DONE:1; unsigned SLEEPOUT_DONE:1; unsigned TE_TIMEOUT_INT_EN:1; unsigned VM_VBP_STR_INT_EN:1; unsigned VM_VACT_STR_INT_EN:1; unsigned VM_VFP_STR_INT_EN:1; unsigned SKEWCAL_DONE_INT_EN:1; unsigned rsv_12:19; unsigned BUSY:1; }; struct DSI_COM_CTRL_REG { unsigned DSI_RESET:1; unsigned rsv_1:1; unsigned DPHY_RESET:1; unsigned rsv_3:1; unsigned DSI_DUAL_EN:1; unsigned rsv_5:27; }; enum DSI_MODE_CTRL { DSI_CMD_MODE = 0, DSI_SYNC_PULSE_VDO_MODE = 1, DSI_SYNC_EVENT_VDO_MODE = 2, DSI_BURST_VDO_MODE = 3 }; struct DSI_MODE_CTRL_REG { unsigned MODE:2; unsigned rsv_2:14; unsigned FRM_MODE:1; unsigned MIX_MODE:1; unsigned V2C_SWITCH_ON:1; unsigned C2V_SWITCH_ON:1; unsigned SLEEP_MODE:1; unsigned rsv_21:11; }; enum DSI_LANE_NUM { ONE_LANE = 1, TWO_LANE = 2, THREE_LANE = 3, FOUR_LANE = 4 }; struct DSI_TXRX_CTRL_REG { unsigned VC_NUM:2; unsigned LANE_NUM:4; unsigned DIS_EOT:1; unsigned BLLP_EN:1; unsigned TE_FREERUN:1; unsigned EXT_TE_EN:1; unsigned EXT_TE_EDGE:1; unsigned TE_AUTO_SYNC:1; unsigned MAX_RTN_SIZE:4; unsigned HSTX_CKLP_EN:1; unsigned TYPE1_BTA_SEL:1; unsigned TE_WITH_CMD_EN:1; unsigned TE_TIMEOUT_CHK_EN:1; unsigned rsv_20:12; }; enum DSI_PS_TYPE { PACKED_PS_16BIT_RGB565 = 0, LOOSELY_PS_18BIT_RGB666 = 1, PACKED_PS_24BIT_RGB888 = 2, PACKED_PS_18BIT_RGB666 = 3 }; struct DSI_PSCTRL_REG { unsigned DSI_PS_WC:14; unsigned rsv_14:2; unsigned DSI_PS_SEL:2; unsigned rsv_18:6; unsigned RGB_SWAP:1; unsigned BYTE_SWAP:1; unsigned rsv_26:6; }; struct DSI_VSA_NL_REG { unsigned VSA_NL:10; unsigned rsv_11:22; }; struct DSI_VBP_NL_REG { unsigned VBP_NL:10; unsigned rsv_11:22; }; struct DSI_VFP_NL_REG { unsigned VFP_NL:10; unsigned rsv_11:22; }; struct DSI_VACT_NL_REG { unsigned VACT_NL:12; unsigned rsv_12:20; }; struct DSI_LFR_CON_REG { unsigned LFR_MODE:2; unsigned LFR_TYPE:2; unsigned LFR_EN:1; unsigned LFR_UPDATE:1; unsigned LFR_VSE_DIS:1; unsigned rsv_7:1; unsigned LFR_SKIP_NUM:6; unsigned rsv_14:18; }; struct DSI_LFR_STA_REG { unsigned LFR_SKIP_STA:6; unsigned rsv_6:2; unsigned LFR_SKIP_CNT:24; }; struct DSI_HSA_WC_REG { unsigned HSA_WC:12; unsigned rsv_12:20; }; struct DSI_HBP_WC_REG { unsigned HBP_WC:12; unsigned rsv_12:20; }; struct DSI_HFP_WC_REG { unsigned HFP_WC:12; unsigned rsv_12:20; }; struct DSI_BLLP_WC_REG { unsigned BLLP_WC:12; unsigned rsv_12:20; }; struct DSI_CMDQ_CTRL_REG { unsigned CMDQ_SIZE:8; unsigned rsv_8:24; }; struct DSI_RX_DATA_REG { unsigned char byte0; unsigned char byte1; unsigned char byte2; unsigned char byte3; }; struct DSI_RACK_REG { unsigned DSI_RACK:1; unsigned DSI_RACK_BYPASS:1; unsigned rsv2:30; }; struct DSI_TRIG_STA_REG { unsigned TRIG0:1; /* remote rst */ unsigned TRIG1:1; /* TE */ unsigned TRIG2:1; /* ack */ unsigned TRIG3:1; /* rsv */ unsigned RX_ULPS:1; unsigned DIRECTION:1; unsigned RX_LPDT:1; unsigned rsv7:1; unsigned RX_POINTER:4; unsigned rsv12:20; }; struct DSI_MEM_CONTI_REG { unsigned RWMEM_CONTI:16; unsigned rsv16:16; }; struct DSI_FRM_BC_REG { unsigned FRM_BC:21; unsigned rsv21:11; }; struct DSI_PHY_CON_REG { unsigned PHY_RST:1; unsigned rsv1:4; unsigned HTXTO_RST:1; unsigned LRXTO_RST:1; unsigned BTATO_RST:1; unsigned rsv8:24; }; struct DSI_PHY_LCCON_REG { unsigned LC_HS_TX_EN:1; unsigned LC_ULPM_EN:1; unsigned LC_WAKEUP_EN:1; unsigned rsv3:29; }; struct DSI_PHY_LD0CON_REG { unsigned L0_RM_TRIG_EN:1; unsigned L0_ULPM_EN:1; unsigned L0_WAKEUP_EN:1; unsigned Lx_ULPM_AS_L0:1; unsigned L0_RX_FILTER_EN:1; unsigned rsv3:27; }; struct DSI_PHY_TIMCON0_REG { unsigned char LPX; unsigned char HS_PRPR; unsigned char HS_ZERO; unsigned char HS_TRAIL; }; struct DSI_PHY_TIMCON1_REG { unsigned char TA_GO; unsigned char TA_SURE; unsigned char TA_GET; unsigned char DA_HS_EXIT; }; struct DSI_PHY_TIMCON2_REG { unsigned char CONT_DET; unsigned char DA_HS_SYNC; unsigned char CLK_ZERO; unsigned char CLK_TRAIL; }; struct DSI_PHY_TIMCON3_REG { unsigned char CLK_HS_PRPR; unsigned char CLK_HS_POST; unsigned char CLK_HS_EXIT; unsigned rsv24:8; }; struct DSI_PHY_TIMCON4_REG { unsigned ULPS_WAKEUP:20; unsigned rsv20:12; }; struct DSI_PHY_TIMCON_REG { struct DSI_PHY_TIMCON0_REG CTRL0; struct DSI_PHY_TIMCON1_REG CTRL1; struct DSI_PHY_TIMCON2_REG CTRL2; struct DSI_PHY_TIMCON3_REG CTRL3; }; struct DSI_CKSM_OUT_REG { unsigned PKT_CHECK_SUM:16; unsigned ACC_CHECK_SUM:16; }; struct DSI_STATE_DBG0_REG { unsigned DPHY_CTL_STATE_C:9; unsigned rsv9:7; unsigned DPHY_HS_TX_STATE_C:5; unsigned rsv21:11; }; struct DSI_STATE_DBG1_REG { unsigned CTL_STATE_C:15; unsigned rsv15:1; unsigned HS_TX_STATE_0:5; unsigned rsv21:3; unsigned ESC_STATE_0:8; }; struct DSI_STATE_DBG2_REG { unsigned RX_ESC_STATE:10; unsigned rsv10:6; unsigned TA_T2R_STATE:5; unsigned rsv21:3; unsigned TA_R2T_STATE:5; unsigned rsv29:3; }; struct DSI_STATE_DBG3_REG { unsigned CTL_STATE_1:5; unsigned rsv5:3; unsigned HS_TX_STATE_1:5; unsigned rsv13:3; unsigned CTL_STATE_2:5; unsigned rsv21:3; unsigned HS_TX_STATE_2:5; unsigned rsv29:3; }; struct DSI_STATE_DBG4_REG { unsigned CTL_STATE_3:5; unsigned rsv5:3; unsigned HS_TX_STATE_3:5; unsigned rsv13:19; }; struct DSI_STATE_DBG5_REG { unsigned TIMER_COUNTER:16; unsigned TIMER_BUSY:1; unsigned rsv17:11; unsigned WAKEUP_STATE:4; }; struct DSI_STATE_DBG6_REG { unsigned CMTRL_STATE:14; unsigned rsv14:2; unsigned CMDQ_STATE:8; unsigned rsv24:8; }; struct DSI_STATE_DBG7_REG { unsigned VMCTL_STATE:11; unsigned rsv11:1; unsigned VFP_PERIOD:1; unsigned VACT_PERIOD:1; unsigned VBP_PERIOD:1; unsigned VSA_PERIOD:1; unsigned rsv16:16; }; struct DSI_STATE_DBG8_REG { unsigned WORD_COUNTER:14; unsigned rsv14:18; }; struct DSI_STATE_DBG9_REG { unsigned LINE_COUNTER:22; unsigned rsv22:10; }; struct DSI_DEBUG_SEL_REG { unsigned DEBUG_OUT_SEL:5; unsigned rsv5:3; unsigned CHKSUM_REC_EN:1; unsigned rsv9:23; }; struct DSI_BIST_CON_REG { unsigned BIST_MODE:1; unsigned BIST_ENABLE:1; unsigned BIST_FIX_PATTERN:1; unsigned BIST_SPC_PATTERN:1; unsigned BIST_HS_FREE:1; unsigned rsv_05:1; unsigned SELF_PAT_MODE:1; unsigned rsv_07:1; unsigned BIST_LANE_NUM:4; unsigned rsv12:4; unsigned BIST_TIMING:8; unsigned rsv24:8; }; struct DSI_VM_CMD_CON_REG { unsigned VM_CMD_EN:1; unsigned LONG_PKT:1; unsigned TIME_SEL:1; unsigned TS_VSA_EN:1; unsigned TS_VBP_EN:1; unsigned TS_VFP_EN:1; unsigned rsv6:2; unsigned CM_DATA_ID:8; unsigned CM_DATA_0:8; unsigned CM_DATA_1:8; }; struct DSI_3D_CON_REG { unsigned _3D_MODE:2; unsigned _3D_FMT:2; unsigned _3D_VSYNC:1; unsigned _3D_LR:1; unsigned _3D_EN:1; unsigned rsv08:25; }; struct DSI_TIME_CON0_REG { unsigned UPLS_WAKEUP_PRD:16; unsigned SKEWCALL_PRD:16; }; struct DSI_TIME_CON1_REG { unsigned UPLS_WAKEUP_PRD:16; unsigned rsv16:16; }; struct DSI_REGS { struct DSI_START_REG DSI_START; /* 0000 */ struct DSI_STATUS_REG DSI_STA; /* 0004 */ struct DSI_INT_ENABLE_REG DSI_INTEN; /* 0008 */ struct DSI_INT_STATUS_REG DSI_INTSTA; /* 000C */ struct DSI_COM_CTRL_REG DSI_COM_CTRL; /* 0010 */ struct DSI_MODE_CTRL_REG DSI_MODE_CTRL; /* 0014 */ struct DSI_TXRX_CTRL_REG DSI_TXRX_CTRL; /* 0018 */ struct DSI_PSCTRL_REG DSI_PSCTRL; /* 001C */ struct DSI_VSA_NL_REG DSI_VSA_NL; /* 0020 */ struct DSI_VBP_NL_REG DSI_VBP_NL; /* 0024 */ struct DSI_VFP_NL_REG DSI_VFP_NL; /* 0028 */ struct DSI_VACT_NL_REG DSI_VACT_NL; /* 002C */ struct DSI_LFR_CON_REG DSI_LFR_CON; /* 0030 */ struct DSI_LFR_STA_REG DSI_LFR_STA; /* 0034 */ uint32_t rsv_38[6]; /* 0038..004C */ struct DSI_HSA_WC_REG DSI_HSA_WC; /* 0050 */ struct DSI_HBP_WC_REG DSI_HBP_WC; /* 0054 */ struct DSI_HFP_WC_REG DSI_HFP_WC; /* 0058 */ struct DSI_BLLP_WC_REG DSI_BLLP_WC; /* 005C */ struct DSI_CMDQ_CTRL_REG DSI_CMDQ_SIZE; /* 0060 */ uint32_t DSI_HSTX_CKL_WC; /* 0064 */ uint32_t DSI_HSTX_CKL_WC_AUTO_RESULT; /* 0068 */ uint32_t rsv_006C[2]; /* 006c..0070 */ struct DSI_RX_DATA_REG DSI_RX_DATA0; /* 0074 */ struct DSI_RX_DATA_REG DSI_RX_DATA1; /* 0078 */ struct DSI_RX_DATA_REG DSI_RX_DATA2; /* 007c */ struct DSI_RX_DATA_REG DSI_RX_DATA3; /* 0080 */ struct DSI_RACK_REG DSI_RACK; /* 0084 */ struct DSI_TRIG_STA_REG DSI_TRIG_STA; /* 0088 */ uint32_t rsv_008C; /* 008C */ struct DSI_MEM_CONTI_REG DSI_MEM_CONTI; /* 0090 */ struct DSI_FRM_BC_REG DSI_FRM_BC; /* 0094 */ struct DSI_3D_CON_REG DSI_3D_CON; /* 0098 */ uint32_t rsv_009C; /* 009c */ struct DSI_TIME_CON0_REG DSI_TIME_CON0; /* 00A0 */ struct DSI_TIME_CON1_REG DSI_TIME_CON1; /* 00A4 */ uint32_t rsv_00A8[22]; /* 0A8..0FC */ uint32_t DSI_PHY_PCPAT; /* 00100 */ struct DSI_PHY_LCCON_REG DSI_PHY_LCCON; /* 0104 */ struct DSI_PHY_LD0CON_REG DSI_PHY_LD0CON; /* 0108 */ uint32_t rsv_010C; /* 010C */ struct DSI_PHY_TIMCON0_REG DSI_PHY_TIMECON0; /* 0110 */ struct DSI_PHY_TIMCON1_REG DSI_PHY_TIMECON1; /* 0114 */ struct DSI_PHY_TIMCON2_REG DSI_PHY_TIMECON2; /* 0118 */ struct DSI_PHY_TIMCON3_REG DSI_PHY_TIMECON3; /* 011C */ struct DSI_PHY_TIMCON4_REG DSI_PHY_TIMECON4; /* 0120 */ uint32_t rsv_0124[3]; /* 0124..012c */ struct DSI_VM_CMD_CON_REG DSI_VM_CMD_CON; /* 0130 */ uint32_t DSI_VM_CMD_DATA0; /* 0134 */ uint32_t DSI_VM_CMD_DATA4; /* 0138 */ uint32_t DSI_VM_CMD_DATA8; /* 013C */ uint32_t DSI_VM_CMD_DATAC; /* 0140 */ struct DSI_CKSM_OUT_REG DSI_CKSM_OUT; /* 0144 */ struct DSI_STATE_DBG0_REG DSI_STATE_DBG0; /* 0148 */ struct DSI_STATE_DBG1_REG DSI_STATE_DBG1; /* 014C */ struct DSI_STATE_DBG2_REG DSI_STATE_DBG2; /* 0150 */ struct DSI_STATE_DBG3_REG DSI_STATE_DBG3; /* 0154 */ struct DSI_STATE_DBG4_REG DSI_STATE_DBG4; /* 0158 */ struct DSI_STATE_DBG5_REG DSI_STATE_DBG5; /* 015C */ struct DSI_STATE_DBG6_REG DSI_STATE_DBG6; /* 0160 */ struct DSI_STATE_DBG7_REG DSI_STATE_DBG7; /* 0164 */ struct DSI_STATE_DBG8_REG DSI_STATE_DBG8; /* 0168 */ struct DSI_STATE_DBG9_REG DSI_STATE_DBG9; /* 016C */ struct DSI_DEBUG_SEL_REG DSI_DEBUG_SEL; /* 0170 */ uint32_t rsv174; /* 0174 */ uint32_t DSI_BIST_PATTERN; /* 0178 */ struct DSI_BIST_CON_REG DSI_BIST_CON; /* 017C */ }; struct DSI_CMDQ { unsigned char byte0; unsigned char byte1; unsigned char byte2; unsigned char byte3; }; struct DSI_CMDQ_REGS { struct DSI_CMDQ data[128]; }; struct DSI_VM_CMDQ { unsigned char byte0; unsigned char byte1; unsigned char byte2; unsigned char byte3; }; struct DSI_VM_CMDQ_REGS { struct DSI_VM_CMDQ data[4]; }; struct DSI_PHY_REGS { struct MIPITX_DSI_CON_REG MIPITX_DSI_CON; /* 0000 */ struct MIPITX_DSI_CLOCK_LANE_REG MIPITX_DSI_CLOCK_LANE; /* 0004 */ struct MIPITX_DSI_DATA_LANE0_REG MIPITX_DSI_DATA_LANE0; /* 0008 */ struct MIPITX_DSI_DATA_LANE1_REG MIPITX_DSI_DATA_LANE1; /* 000C */ struct MIPITX_DSI_DATA_LANE2_REG MIPITX_DSI_DATA_LANE2; /* 0010 */ struct MIPITX_DSI_DATA_LANE3_REG MIPITX_DSI_DATA_LANE3; /* 0014 */ uint32_t rsv_18[10]; /* 0018..003C */ struct MIPITX_DSI_TOP_CON_REG MIPITX_DSI_TOP_CON; /* 0040 */ struct MIPITX_DSI_BG_CON_REG MIPITX_DSI_BG_CON; /* 0044 */ uint32_t rsv_48[2]; /* 0048..004C */ struct MIPITX_DSI_PLL_CON0_REG MIPITX_DSI_PLL_CON0; /* 0050 */ struct MIPITX_DSI_PLL_CON1_REG MIPITX_DSI_PLL_CON1; /* 0054 */ struct MIPITX_DSI_PLL_CON2_REG MIPITX_DSI_PLL_CON2; /* 0058 */ struct MIPITX_DSI_PLL_CON3_REG MIPITX_DSI_PLL_CON3; /* 005C */ struct MIPITX_DSI_PLL_CHG_REG MIPITX_DSI_PLL_CHG; /* 0060 */ struct MIPITX_DSI_PLL_TOP_REG MIPITX_DSI_PLL_TOP; /* 0064 */ struct MIPITX_DSI_PLL_PWR_REG MIPITX_DSI_PLL_PWR; /* 0068 */ uint32_t rsv_6C; /* 006C */ struct MIPITX_DSI_RGS_REG MIPITX_DSI_RGS; /* 0070 */ struct MIPITX_DSI_GPI_EN_REG MIPITX_DSI_GPI_EN; /* 0074 */ struct MIPITX_DSI_GPI_PULL_REG MIPITX_DSI_GPI_PULL; /* 0078 */ struct MIPITX_DSI_PHY_SEL_REG MIPITX_DSI_PHY_SEL; /* 007C */ struct MIPITX_DSI_SW_CTRL_REG MIPITX_DSI_SW_CTRL_EN; /* 0080 */ struct MIPITX_DSI_SW_CTRL_CON0_REG MIPITX_DSI_SW_CTRL_CON0; /* 0084 */ struct MIPITX_DSI_SW_CTRL_CON1_REG MIPITX_DSI_SW_CTRL_CON1; /* 0088 */ struct MIPITX_DSI_SW_CTRL_CON2_REG MIPITX_DSI_SW_CTRL_CON2; /* 008C */ struct MIPITX_DSI_DBG_CON_REG MIPITX_DSI_DBG_CON; /* 0090 */ uint32_t MIPITX_DSI_DBG_OUT; /* 0084 */ struct MIPITX_DSI_APB_ASYNC_STA_REG MIPITX_DSI_APB_ASYNC_STA; /* 0098 */ }; #ifndef BUILD_LK /* STATIC_ASSERT(0x0050 == offsetof(struct DSI_PHY_REGS, MIPITX_DSI_PLL_CON0)); STATIC_ASSERT(0x0070 == offsetof(struct DSI_PHY_REGS, MIPITX_DSI_RGS)); STATIC_ASSERT(0x0080 == offsetof(struct DSI_PHY_REGS, MIPITX_DSI_SW_CTRL_EN)); STATIC_ASSERT(0x0090 == offsetof(struct DSI_PHY_REGS, MIPITX_DSI_DBG_CON)); STATIC_ASSERT(0x002C == offsetof(struct DSI_REGS, DSI_VACT_NL)); STATIC_ASSERT(0x0104 == offsetof(struct DSI_REGS, DSI_PHY_LCCON)); STATIC_ASSERT(0x011C == offsetof(struct DSI_REGS, DSI_PHY_TIMECON3)); STATIC_ASSERT(0x017C == offsetof(struct DSI_REGS, DSI_BIST_CON)); STATIC_ASSERT(0x0100 == offsetof(struct DSI_REGS, DSI_PHY_PCPAT)); STATIC_ASSERT(0x0098 == offsetof(struct DSI_REGS, DSI_3D_CON)); */ #endif extern unsigned long dispsys_reg[DISP_REG_NUM]; extern unsigned long mipi_tx_reg; extern unsigned long dsi_reg_va; /* DTS will assign reigister address dynamically, so can not define to 0x1000 */ /* #define DISP_INDEX_OFFSET 0x1000 */ #define DISP_RDMA_INDEX_OFFSET (dispsys_reg[DISP_REG_RDMA1] - dispsys_reg[DISP_REG_RDMA0]) #define DISP_OVL_INDEX_OFFSET (dispsys_reg[DISP_REG_OVL1] - dispsys_reg[DISP_REG_OVL0]) #define DISP_WDMA_INDEX_OFFSET (0) #define DDP_REG_BASE_MMSYS_CONFIG dispsys_reg[DISP_REG_CONFIG] #define DDP_REG_BASE_DISP_OVL0 dispsys_reg[DISP_REG_OVL0] #define DDP_REG_BASE_DISP_OVL1 dispsys_reg[DISP_REG_OVL1] #define DDP_REG_BASE_DISP_RDMA0 dispsys_reg[DISP_REG_RDMA0] #define DDP_REG_BASE_DISP_RDMA1 dispsys_reg[DISP_REG_RDMA1] #define DDP_REG_BASE_DISP_WDMA0 dispsys_reg[DISP_REG_WDMA0] #define DDP_REG_BASE_DISP_WDMA1 0 #define DDP_REG_BASE_DISP_COLOR0 dispsys_reg[DISP_REG_COLOR] #define DDP_REG_BASE_DISP_COLOR1 0 #define DDP_REG_BASE_DISP_AAL dispsys_reg[DISP_REG_AAL] #define DDP_REG_BASE_DISP_GAMMA dispsys_reg[DISP_REG_GAMMA] #define DDP_REG_BASE_DISP_MERGE 0 #define DDP_REG_BASE_DISP_SPLIT0 0 #define DDP_REG_BASE_DISP_SPLIT1 0 #define DDP_REG_BASE_DISP_UFOE 0 #define DDP_REG_BASE_DSI0 dispsys_reg[DISP_REG_DSI0] #define DDP_REG_BASE_DSI1 0 #define DDP_REG_BASE_DPI dispsys_reg[DISP_REG_DPI0] #define DDP_REG_BASE_DISP_PWM0 dispsys_reg[DISP_REG_PWM] #define DDP_REG_BASE_DISP_PWM1 0 #define DDP_REG_BASE_MM_MUTEX dispsys_reg[DISP_REG_MUTEX] #define DDP_REG_BASE_SMI_LARB0 dispsys_reg[DISP_REG_SMI_LARB0] #define DDP_REG_BASE_SMI_COMMON dispsys_reg[DISP_REG_SMI_COMMON] #define DDP_REG_BASE_DISP_OD dispsys_reg[DISP_REG_OD] #define DDP_REG_BASE_DISP_CCORR dispsys_reg[DISP_REG_CCORR] #define DDP_REG_BASE_DISP_DITHER dispsys_reg[DISP_REG_DITHER] #define DDP_REG_BASE_MMSYS_CONFIG2 dispsys_reg[DISP_REG_CONFIG2] #define DDP_REG_BASE_MMSYS_CONFIG3 dispsys_reg[DISP_REG_CONFIG3] #define DDP_REG_IO_DRIVING1 dispsys_reg[DISP_REG_IO_DRIVING1] #define DDP_REG_IO_DRIVING2 dispsys_reg[DISP_REG_IO_DRIVING2] #define DDP_REG_IO_DRIVING3 dispsys_reg[DISP_REG_IO_DRIVING3] #define DDP_REG_EFUSE dispsys_reg[DISP_REG_EFUSE] #define DDP_REG_EFUSE_PERMISSION dispsys_reg[DISP_REG_EFUSE_PERMISSION] #define DDP_REG_EFUSE_KEY dispsys_reg[DISP_RGE_EFUSE_KEY] #define DDP_REG_BASE_VENCPLL dispsys_reg[DISP_RGE_VENCPLL] #define DDP_REG_TVDPLL_CON6 dispsys_reg[DISP_TVDPLL_CFG6] #define DDP_REG_TVDPLL_CON0 dispsys_reg[DISP_TVDPLL_CON0] #define DDP_REG_TVDPLL_CON1 dispsys_reg[DISP_TVDPLL_CON1] #define MIPI_TX_REG_BASE (mipi_tx_reg) #if 0 #define DDP_REG_BASE_MMSYS_CONFIG MMSYS_CONFIG_BASE /* 0xf4000000 */ #define DDP_REG_BASE_DISP_OVL0 OVL0_BASE /* 0xf400C000 */ #define DDP_REG_BASE_DISP_OVL1 OVL1_BASE /* 0xf400D000 */ #define DDP_REG_BASE_DISP_RDMA0 DISP_RDMA0_BASE /* 0xf400E000 */ #define DDP_REG_BASE_DISP_RDMA1 DISP_RDMA1_BASE /* 0xf400F000 */ #define DDP_REG_BASE_DISP_RDMA2 DISP_RDMA2_BASE /* 0xf4010000 */ #define DDP_REG_BASE_DISP_WDMA0 DISP_WDMA0_BASE /* 0xf4011000 */ #define DDP_REG_BASE_DISP_WDMA1 DISP_WDMA1_BASE /* 0xf4012000 */ #define DDP_REG_BASE_DISP_COLOR0 COLOR0_BASE /* 0xf4013000 */ #define DDP_REG_BASE_DISP_COLOR1 COLOR1_BASE /* 0xf4014000 */ #define DDP_REG_BASE_DISP_AAL DISP_AAL_BASE /* 0xf4015000 */ #define DDP_REG_BASE_DISP_GAMMA DISP_GAMMA_BASE /* 0xf4016000 */ #define DDP_REG_BASE_DISP_MERGE DISP_MERGE_BASE /* 0xf4017000 */ #define DDP_REG_BASE_DISP_SPLIT0 DISP_SPLIT0_BASE /* 0xf4018000 */ #define DDP_REG_BASE_DISP_SPLIT1 DISP_SPLIT1_BASE /* 0xf4019000 */ #define DDP_REG_BASE_DISP_UFOE DISP_UFOE_BASE /* 0xf401A000 */ #define DDP_REG_BASE_DSI0 DSI0_BASE /* 0xf401B000 */ #define DDP_REG_BASE_DSI1 DSI1_BASE /* 0xf401C000 */ #define DDP_REG_BASE_DPI DPI_BASE /* 0xf401D000 */ #define DDP_REG_BASE_DISP_PWM0 DISP_PWM0_BASE /* 0xf401E000 */ #define DDP_REG_BASE_DISP_PWM1 DISP_PWM1_BASE /* 0xf401F000 */ #define DDP_REG_BASE_MM_MUTEX MM_MUTEX_BASE /* 0xf4020000 */ #define DDP_REG_BASE_SMI_LARB0 SMI_LARB0_BASE /* 0xf4021000 */ #define DDP_REG_BASE_SMI_COMMON SMI_COMMON_BASE /* 0xf4022000 */ #define DDP_REG_BASE_DISP_OD DISP_OD_BASE /* 0xf4023000 */ #endif #define DISPSYS_REG_ADDR_MIN 0 /* dispsys_reg[0] */ #define DISPSYS_REG_ADDR_MAX 0xffffffffffffffff /* (dispsys_reg[0]+0x200000) */ #define DISPSYS_CONFIG_BASE DDP_REG_BASE_MMSYS_CONFIG #define DISPSYS_OVL0_BASE DDP_REG_BASE_DISP_OVL0 #define DISPSYS_OVL1_BASE DDP_REG_BASE_DISP_OVL1 #define DISPSYS_RDMA0_BASE DDP_REG_BASE_DISP_RDMA0 #define DISPSYS_RDMA1_BASE DDP_REG_BASE_DISP_RDMA1 #define DISPSYS_WDMA0_BASE DDP_REG_BASE_DISP_WDMA0 #define DISPSYS_WDMA1_BASE DDP_REG_BASE_DISP_WDMA1 #define DISPSYS_COLOR0_BASE DDP_REG_BASE_DISP_COLOR0 #define DISPSYS_COLOR1_BASE DDP_REG_BASE_DISP_COLOR1 #define DISPSYS_AAL_BASE DDP_REG_BASE_DISP_AAL #define DISPSYS_GAMMA_BASE DDP_REG_BASE_DISP_GAMMA #define DISPSYS_MERGE_BASE DDP_REG_BASE_DISP_MERGE #define DISPSYS_SPLIT0_BASE DDP_REG_BASE_DISP_SPLIT0 #define DISPSYS_SPLIT1_BASE DDP_REG_BASE_DISP_SPLIT1 #define DISPSYS_UFOE_BASE DDP_REG_BASE_DISP_UFOE #define DISPSYS_DSI0_BASE DDP_REG_BASE_DSI0 #define DISPSYS_DSI1_BASE DDP_REG_BASE_DSI1 #define DISPSYS_DPI_BASE DDP_REG_BASE_DPI #define DISPSYS_PWM0_BASE DDP_REG_BASE_DISP_PWM0 #define DISPSYS_PWM1_BASE DDP_REG_BASE_DISP_PWM1 #define DISPSYS_MUTEX_BASE DDP_REG_BASE_MM_MUTEX #define DISPSYS_SMI_LARB0_BASE DDP_REG_BASE_SMI_LARB0 #define DISPSYS_SMI_COMMON_BASE DDP_REG_BASE_SMI_COMMON #define DISPSYS_OD_BASE DDP_REG_BASE_DISP_OD #define DISPSYS_CCORR_BASE DDP_REG_BASE_DISP_CCORR #define DISPSYS_DITHER_BASE DDP_REG_BASE_DISP_DITHER #define DISPSYS_CONFIG2_BASE DDP_REG_BASE_MMSYS_CONFIG2 #define DISPSYS_CONFIG3_BASE DDP_REG_BASE_MMSYS_CONFIG3 #define DISPSYS_IO_DRIVING1 DDP_REG_IO_DRIVING1 #define DISPSYS_IO_DRIVING2 DDP_REG_IO_DRIVING2 #define DISPSYS_IO_DRIVING3 DDP_REG_IO_DRIVING3 #define DISPSYS_EFUSE DDP_REG_EFUSE #define DISPSYS_EFUSE_PERMISSION DDP_REG_EFUSE_PERMISSION #define DISPSYS_EFUSE_KEY DDP_REG_EFUSE_KEY #define DISPSYS_VENCPLL_BASE DDP_REG_BASE_VENCPLL #define MIPITX_BASE MIPI_TX_REG_BASE /* --------------------------------------------------------------------------- */ /* Type Casting */ /* --------------------------------------------------------------------------- */ #if 0 #define AS_INT32(x) (*(INT32 *)(x)) #define AS_INT16(x) (*(INT16 *)(x)) #define AS_INT8(x) (*(INT8 *)(x)) #define AS_UINT32(x) __raw_readl(x) #define AS_UINT16(x) (*(uint16_t *)(x)) #define AS_UINT8(x) (*(uint8_t *)(x)) /* --------------------------------------------------------------------------- */ /* Register Manipulations */ /* --------------------------------------------------------------------------- */ #define READ_REGISTER_UINT32(reg) \ (*(volatile unsigned long * const)(reg)) #define WRITE_REGISTER_UINT32(reg, val) \ ((*(volatile unsigned long * const)(reg)) = (val)) #define READ_REGISTER_UINT16(reg) \ (*(volatile uint16_t * const)(reg)) #define WRITE_REGISTER_UINT16(reg, val) \ ((*(volatile uint16_t * const)(reg)) = (val)) #define READ_REGISTER_UINT8(reg) \ (*(volatile uint8_t * const)(reg)) #define WRITE_REGISTER_UINT8(reg, val) \ ((*(volatile uint8_t * const)(reg)) = (val)) #endif #if 0 #define INREG8(x) READ_REGISTER_UINT8((uint8_t *)(x)) #define OUTREG8(x, y) WRITE_REGISTER_UINT8((uint8_t *)(x), (uint8_t)(y)) #define SETREG8(x, y) OUTREG8(x, INREG8(x)|(y)) #define CLRREG8(x, y) OUTREG8(x, INREG8(x)&~(y)) #define MASKREG8(x, y, z) OUTREG8(x, (INREG8(x)&~(y))|(z)) #define INREG16(x) READ_REGISTER_UINT16((uint16_t *)(x)) #define OUTREG16(x, y) WRITE_REGISTER_UINT16((uint16_t *)(x), (uint16_t)(y)) #define SETREG16(x, y) OUTREG16(x, INREG16(x)|(y)) #define CLRREG16(x, y) OUTREG16(x, INREG16(x)&~(y)) #define MASKREG16(x, y, z) OUTREG16(x, (INREG16(x)&~(y))|(z)) #define INREG32(x) (__raw_readl((unsigned long *)(x))) #define OUTREG32(x, y) WRITE_REGISTER_UINT32((unsigned long *)(x), (uint32_t)(y)) #define SETREG32(x, y) OUTREG32(x, INREG32(x)|(y)) #define CLRREG32(x, y) OUTREG32(x, INREG32(x)&~(y)) #define MASKREG32(x, y, z) OUTREG32(x, (INREG32(x)&~(y))|(z)) #endif #ifdef INREG32 #undef INREG32 #define INREG32(x) (__raw_readl((unsigned long *)(x))) #endif /* --------------------------------------------------------------------------- */ /* Register Field Access */ /* --------------------------------------------------------------------------- */ #define READ_REGISTER_UINT32(reg) (*(volatile uint32_t *const)(reg)) #define INREG32(x) READ_REGISTER_UINT32((uint32_t *)((void *)(x))) #define WRITE_REGISTER_UINT32(reg, val) ((*(volatile uint32_t *const)(reg)) = (val)) #define OUTREG32(x, y) WRITE_REGISTER_UINT32((uint32_t *)((void *)(x)), (uint32_t)(y)) #define AS_UINT32(x) (*(uint32_t *)((void *)x)) #define REG_FLD(width, shift) \ ((unsigned int)((((width) & 0xFF) << 16) | ((shift) & 0xFF))) #define REG_FLD_WIDTH(field) \ ((unsigned int)(((field) >> 16) & 0xFF)) #define REG_FLD_SHIFT(field) \ ((unsigned int)((field) & 0xFF)) #define REG_FLD_MASK(field) \ (((unsigned int)(1 << REG_FLD_WIDTH(field)) - 1) << REG_FLD_SHIFT(field)) #define REG_FLD_VAL(field, val) \ (((val) << REG_FLD_SHIFT(field)) & REG_FLD_MASK(field)) #define DISP_REG_GET(reg32) __raw_readl((unsigned long *)(reg32)) #define DISP_REG_GET_FIELD(field, reg32) ((__raw_readl((void *)(reg32)) & REG_FLD_MASK(field)) >> REG_FLD_SHIFT(field)) /* polling register until masked bit is 1 */ #define DDP_REG_POLLING(reg32, mask) \ do { \ while (!((DISP_REG_GET(reg32))&mask)) \ ; \ } while (0) /* Polling register until masked bit is 0 */ #define DDP_REG_POLLING_NEG(reg32, mask) \ do { \ while ((DISP_REG_GET(reg32))&mask) \ ; \ } while (0) #define DISP_CPU_REG_SET(reg32, val) \ do {\ if (0) \ dprec_reg_op(NULL, reg32, val, 0x00000000);\ mt_reg_sync_writel(val, (volatile unsigned long *)(reg32));\ } while (0) #define DISP_CPU_REG_SET_FIELD(field, reg32, val) \ do { \ if (0) \ dprec_reg_op(NULL, (unsigned long)(reg32),\ val<