fsl_devices.h 4.0 KB

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  1. /*
  2. * include/linux/fsl_devices.h
  3. *
  4. * Definitions for any platform device related flags or structures for
  5. * Freescale processor devices
  6. *
  7. * Maintainer: Kumar Gala <galak@kernel.crashing.org>
  8. *
  9. * Copyright 2004,2012 Freescale Semiconductor, Inc
  10. *
  11. * This program is free software; you can redistribute it and/or modify it
  12. * under the terms of the GNU General Public License as published by the
  13. * Free Software Foundation; either version 2 of the License, or (at your
  14. * option) any later version.
  15. */
  16. #ifndef _FSL_DEVICE_H_
  17. #define _FSL_DEVICE_H_
  18. #define FSL_UTMI_PHY_DLY 10 /*As per P1010RM, delay for UTMI
  19. PHY CLK to become stable - 10ms*/
  20. #define FSL_USB_PHY_CLK_TIMEOUT 10000 /* uSec */
  21. #define FSL_USB_VER_OLD 0
  22. #define FSL_USB_VER_1_6 1
  23. #define FSL_USB_VER_2_2 2
  24. #define FSL_USB_VER_2_4 3
  25. #include <linux/types.h>
  26. /*
  27. * Some conventions on how we handle peripherals on Freescale chips
  28. *
  29. * unique device: a platform_device entry in fsl_plat_devs[] plus
  30. * associated device information in its platform_data structure.
  31. *
  32. * A chip is described by a set of unique devices.
  33. *
  34. * Each sub-arch has its own master list of unique devices and
  35. * enumerates them by enum fsl_devices in a sub-arch specific header
  36. *
  37. * The platform data structure is broken into two parts. The
  38. * first is device specific information that help identify any
  39. * unique features of a peripheral. The second is any
  40. * information that may be defined by the board or how the device
  41. * is connected externally of the chip.
  42. *
  43. * naming conventions:
  44. * - platform data structures: <driver>_platform_data
  45. * - platform data device flags: FSL_<driver>_DEV_<FLAG>
  46. * - platform data board flags: FSL_<driver>_BRD_<FLAG>
  47. *
  48. */
  49. enum fsl_usb2_operating_modes {
  50. FSL_USB2_MPH_HOST,
  51. FSL_USB2_DR_HOST,
  52. FSL_USB2_DR_DEVICE,
  53. FSL_USB2_DR_OTG,
  54. };
  55. enum fsl_usb2_phy_modes {
  56. FSL_USB2_PHY_NONE,
  57. FSL_USB2_PHY_ULPI,
  58. FSL_USB2_PHY_UTMI,
  59. FSL_USB2_PHY_UTMI_WIDE,
  60. FSL_USB2_PHY_SERIAL,
  61. };
  62. struct clk;
  63. struct platform_device;
  64. struct fsl_usb2_platform_data {
  65. /* board specific information */
  66. int controller_ver;
  67. enum fsl_usb2_operating_modes operating_mode;
  68. enum fsl_usb2_phy_modes phy_mode;
  69. unsigned int port_enables;
  70. unsigned int workaround;
  71. int (*init)(struct platform_device *);
  72. void (*exit)(struct platform_device *);
  73. void __iomem *regs; /* ioremap'd register base */
  74. struct clk *clk;
  75. unsigned power_budget; /* hcd->power_budget */
  76. unsigned big_endian_mmio:1;
  77. unsigned big_endian_desc:1;
  78. unsigned es:1; /* need USBMODE:ES */
  79. unsigned le_setup_buf:1;
  80. unsigned have_sysif_regs:1;
  81. unsigned invert_drvvbus:1;
  82. unsigned invert_pwr_fault:1;
  83. unsigned suspended:1;
  84. unsigned already_suspended:1;
  85. /* register save area for suspend/resume */
  86. u32 pm_command;
  87. u32 pm_status;
  88. u32 pm_intr_enable;
  89. u32 pm_frame_index;
  90. u32 pm_segment;
  91. u32 pm_frame_list;
  92. u32 pm_async_next;
  93. u32 pm_configured_flag;
  94. u32 pm_portsc;
  95. u32 pm_usbgenctrl;
  96. };
  97. /* Flags in fsl_usb2_mph_platform_data */
  98. #define FSL_USB2_PORT0_ENABLED 0x00000001
  99. #define FSL_USB2_PORT1_ENABLED 0x00000002
  100. #define FLS_USB2_WORKAROUND_ENGCM09152 (1 << 0)
  101. struct spi_device;
  102. struct fsl_spi_platform_data {
  103. u32 initial_spmode; /* initial SPMODE value */
  104. s16 bus_num;
  105. unsigned int flags;
  106. #define SPI_QE_CPU_MODE (1 << 0) /* QE CPU ("PIO") mode */
  107. #define SPI_CPM_MODE (1 << 1) /* CPM/QE ("DMA") mode */
  108. #define SPI_CPM1 (1 << 2) /* SPI unit is in CPM1 block */
  109. #define SPI_CPM2 (1 << 3) /* SPI unit is in CPM2 block */
  110. #define SPI_QE (1 << 4) /* SPI unit is in QE block */
  111. /* board specific information */
  112. u16 max_chipselect;
  113. void (*cs_control)(struct spi_device *spi, bool on);
  114. u32 sysclk;
  115. };
  116. struct mpc8xx_pcmcia_ops {
  117. void(*hw_ctrl)(int slot, int enable);
  118. int(*voltage_set)(int slot, int vcc, int vpp);
  119. };
  120. /* Returns non-zero if the current suspend operation would
  121. * lead to a deep sleep (i.e. power removed from the core,
  122. * instead of just the clock).
  123. */
  124. #if defined(CONFIG_PPC_83xx) && defined(CONFIG_SUSPEND)
  125. int fsl_deep_sleep(void);
  126. #else
  127. static inline int fsl_deep_sleep(void) { return 0; }
  128. #endif
  129. #endif /* _FSL_DEVICE_H_ */