mt6627_fm_reg.h 1.8 KB

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  1. #ifndef __MT6627_FM_REG_H__
  2. #define __MT6627_FM_REG_H__
  3. enum MT6627_REG {
  4. FM_MAIN_CG1_CTRL = 0x60,
  5. FM_MAIN_CG2_CTRL = 0x61,
  6. FM_MAIN_HWVER = 0x62,
  7. FM_MAIN_CTRL = 0x63,
  8. FM_CHANNEL_SET = 0x65,
  9. FM_MAIN_CFG1 = 0x66,
  10. FM_MAIN_CFG2 = 0x67,
  11. FM_MAIN_MCLKDESENSE = 0x38,
  12. FM_MAIN_INTR = 0x69,
  13. FM_MAIN_INTRMASK = 0x6A,
  14. FM_MAIN_EXTINTRMASK = 0x6B,
  15. FM_RSSI_IND = 0x6C,
  16. FM_RSSI_TH = 0x6D,
  17. FM_MAIN_RESET = 0x6E,
  18. FM_MAIN_CHANDETSTAT = 0x6F,
  19. FM_RDS_CFG0 = 0x80,
  20. FM_RDS_INFO = 0x81,
  21. FM_RDS_DATA_REG = 0x82,
  22. FM_RDS_GOODBK_CNT = 0x83,
  23. FM_RDS_BADBK_CNT = 0x84,
  24. FM_RDS_PWDI = 0x85,
  25. FM_RDS_PWDQ = 0x86,
  26. FM_RDS_FIFO_STATUS0 = 0x87,
  27. FM_FT_CON9 = 0x8F,
  28. FM_DSP_PATCH_CTRL = 0x90,
  29. FM_DSP_PATCH_OFFSET = 0x91,
  30. FM_DSP_PATCH_DATA = 0x92,
  31. FM_DSP_MEM_CTRL4 = 0x93,
  32. FM_ADDR_PAMD = 0xB4,
  33. FM_RDS_BDGRP_ABD_CTRL_REG = 0xB6,
  34. FM_RDS_POINTER = 0xF0,
  35. };
  36. /* RDS_BDGRP_ABD_CTRL_REG */
  37. enum {
  38. BDGRP_ABD_EN = 0x0001,
  39. BER_RUN = 0x2000
  40. };
  41. #define FM_DAC_CON1 0x83
  42. #define FM_DAC_CON2 0x84
  43. #define FM_FT_CON0 0x86
  44. enum {
  45. FT_EN = 0x0001
  46. };
  47. #define FM_I2S_CON0 0x90
  48. enum {
  49. I2S_EN = 0x0001,
  50. FORMAT = 0x0002,
  51. WLEN = 0x0004,
  52. I2S_SRC = 0x0008
  53. };
  54. /* FM_MAIN_CTRL */
  55. enum {
  56. TUNE = 0x0001,
  57. SEEK = 0x0002,
  58. SCAN = 0x0004,
  59. CQI_READ = 0x0008,
  60. RDS_MASK = 0x0010,
  61. MUTE = 0x0020,
  62. RDS_BRST = 0x0040,
  63. RAMP_DOWN = 0x0100,
  64. };
  65. /* FM_MAIN_INTR */
  66. enum {
  67. FM_INTR_STC_DONE = 0x0001,
  68. FM_INTR_IQCAL_DONE = 0x0002,
  69. FM_INTR_DESENSE_HIT = 0x0004,
  70. FM_INTR_CHNL_CHG = 0x0008,
  71. FM_INTR_SW_INTR = 0x0010,
  72. FM_INTR_RDS = 0x0020
  73. };
  74. enum {
  75. ANTENNA_TYPE = 0x0010, /* 0x61 D4, 0:long, 1:short */
  76. ANALOG_I2S = 0x0080, /* 0x61 D7, 0:lineout, 1:I2S */
  77. DE_EMPHASIS = 0x1000, /* 0x61 D12,0:50us, 1:75 us */
  78. };
  79. #define OSC_FREQ_BITS 0x0070 /* 0x60 bit4~6 */
  80. #define OSC_FREQ_MASK (~OSC_FREQ_BITS)
  81. #endif /* __MT6627_FM_REG_H__ */