max98926.c 33 KB

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  1. /*
  2. * max98926.c -- ALSA SoC Stereo max98926 driver
  3. * Copyright 2013-15 Maxim Integrated Products
  4. * This program is free software; you can redistribute it and/or modify
  5. * it under the terms of the GNU General Public License version 2 as
  6. * published by the Free Software Foundation.
  7. */
  8. #include <linux/delay.h>
  9. #include <linux/i2c.h>
  10. #include <linux/module.h>
  11. #include <linux/regmap.h>
  12. #include <linux/slab.h>
  13. #include <linux/cdev.h>
  14. #include <sound/pcm.h>
  15. #include <sound/pcm_params.h>
  16. #include <linux/dma-mapping.h>
  17. #include <linux/regulator/consumer.h>
  18. #include <sound/soc.h>
  19. #include <sound/tlv.h>
  20. #include "max98926.h"
  21. #define MAX98926_I2C_Channel (0)
  22. static struct i2c_client *new_client;
  23. static ssize_t max_i2c_write(const char *data, size_t count);
  24. static int max_i2c_master_send(const struct i2c_client *client, const char *buf, int count);
  25. static int max98926_WriteReg(u16 a_u2Addr, u16 a_u2Data);
  26. static int max98926_ReadReg(u16 a_u2Addr, unsigned short *a_pu2Result);
  27. static int max98926_regulator_config(struct i2c_client *i2c, bool pullup, bool on);
  28. static void max98926_set_sense_data(struct max98926_priv *max98926);
  29. static const char *const dai_text[] = {
  30. "Left", "Right", "LeftRight", "LeftRightDiv2",
  31. };
  32. static const char *const dai_input_text[] = {
  33. "Pcm", "Analog",
  34. };
  35. static const char *const pdm_1_text[] = {
  36. "Current", "Voltage",
  37. };
  38. static const char *const pdm_0_text[] = {
  39. "Current", "Voltage",
  40. };
  41. static const char *const max98926_boost_voltage_text[] = {
  42. "8.5V", "8.25V", "8.0V", "7.75V", "7.5V", "7.25V", "7.0V", "6.75V",
  43. "6.5V", "6.5V", "6.5V", "6.5V", "6.5V", "6.5V", "6.5V", "6.5V"
  44. };
  45. static SOC_ENUM_SINGLE_DECL(max98926_boost_voltage,
  46. max98926_CONFIGURATION, M98926_BST_VOUT_SHIFT, max98926_boost_voltage_text);
  47. static const char *const hpf_text[] = {
  48. "Disable", "DC Block", "100Hz", "200Hz", "400Hz", "800Hz",
  49. };
  50. static int max98926_spk_zcd_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
  51. {
  52. return 0;
  53. }
  54. static int max98926_spk_zcd_put(struct snd_kcontrol *kcontrol,
  55. struct snd_ctl_elem_value *ucontrol)
  56. {
  57. struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
  58. struct snd_soc_component *codec = component->codec;
  59. struct max98926_priv *max98926 = snd_soc_codec_get_drvdata(codec);
  60. int ret, reg;
  61. ret = snd_soc_read(codec,
  62. max98926_DAI_CLK_DIV_N_LSBS);
  63. pr_err("%s 0x1f read 0x%x\n", __func__, ret);
  64. return 1;
  65. }
  66. static int reg_set_optimum_mode_check(struct regulator *reg, int load_uA)
  67. {
  68. return (regulator_count_voltages(reg) > 0) ?
  69. regulator_set_optimum_mode(reg, load_uA) : 0;
  70. }
  71. static int max98926_regulator_config(struct i2c_client *i2c, bool pullup, bool on)
  72. {
  73. struct regulator *max98926_vcc_i2c;
  74. int rc;
  75. #define VCC_I2C_MIN_UV 1800000
  76. #define VCC_I2C_MAX_UV 1800000
  77. #define I2C_LOAD_UA 300000
  78. pr_info("%s: enter\n", __func__);
  79. if (pullup) {
  80. pr_info("%s: I2C PULL UP.\n", __func__);
  81. max98926_vcc_i2c = regulator_get(&i2c->dev, "vcc_i2c");
  82. if (IS_ERR(max98926_vcc_i2c)) {
  83. rc = PTR_ERR(max98926_vcc_i2c);
  84. pr_info("%s: regulator get failed rc=%d\n", __func__, rc);
  85. goto error_get_vtg_i2c;
  86. }
  87. if (regulator_count_voltages(max98926_vcc_i2c) > 0) {
  88. rc = regulator_set_voltage(max98926_vcc_i2c,
  89. VCC_I2C_MIN_UV, VCC_I2C_MAX_UV);
  90. if (rc) {
  91. pr_info("%s: regulator set_vtg failed rc=%d\n", __func__, rc);
  92. goto error_set_vtg_i2c;
  93. }
  94. }
  95. rc = reg_set_optimum_mode_check(max98926_vcc_i2c, I2C_LOAD_UA);
  96. if (rc < 0) {
  97. pr_info("%s: regulator vcc_i2c set_opt failed rc=%d\n", __func__, rc);
  98. goto error_reg_opt_i2c;
  99. }
  100. rc = regulator_enable(max98926_vcc_i2c);
  101. if (rc) {
  102. pr_info("%s: regulator vcc_i2c enable failed rc=%d\n", __func__, rc);
  103. goto error_reg_en_vcc_i2c;
  104. }
  105. }
  106. return 0;
  107. error_set_vtg_i2c:
  108. regulator_put(max98926_vcc_i2c);
  109. error_get_vtg_i2c:
  110. if (regulator_count_voltages(max98926_vcc_i2c) > 0)
  111. regulator_set_voltage(max98926_vcc_i2c, 0, VCC_I2C_MAX_UV);
  112. error_reg_en_vcc_i2c:
  113. if (pullup)
  114. reg_set_optimum_mode_check(max98926_vcc_i2c, 0);
  115. error_reg_opt_i2c:
  116. regulator_disable(max98926_vcc_i2c);
  117. return rc;
  118. }
  119. static struct reg_default max98926_reg[] = {
  120. { 0x0B, 0x00 }, /* IRQ Enable0 */
  121. { 0x0C, 0x00 }, /* IRQ Enable1 */
  122. { 0x0D, 0x00 }, /* IRQ Enable2 */
  123. { 0x0E, 0x00 }, /* IRQ Clear0 */
  124. { 0x0F, 0x00 }, /* IRQ Clear1 */
  125. { 0x10, 0x00 }, /* IRQ Clear2 */
  126. { 0x11, 0xC0 }, /* Map0 */
  127. { 0x12, 0x00 }, /* Map1 */
  128. { 0x13, 0x00 }, /* Map2 */
  129. { 0x14, 0xF0 }, /* Map3 */
  130. { 0x15, 0x00 }, /* Map4 */
  131. { 0x16, 0xAB }, /* Map5 */
  132. { 0x17, 0x89 }, /* Map6 */
  133. { 0x18, 0x00 }, /* Map7 */
  134. { 0x19, 0x00 }, /* Map8 */
  135. { 0x1A, 0x06 }, /* DAI Clock Mode 1 */
  136. { 0x1B, 0xC0 }, /* DAI Clock Mode 2 */
  137. { 0x1C, 0x00 }, /* DAI Clock Divider Denominator MSBs */
  138. { 0x1D, 0x00 }, /* DAI Clock Divider Denominator LSBs */
  139. { 0x1E, 0xF0 }, /* DAI Clock Divider Numerator MSBs */
  140. { 0x1F, 0x00 }, /* DAI Clock Divider Numerator LSBs */
  141. { 0x20, 0x50 }, /* Format */
  142. { 0x21, 0x00 }, /* TDM Slot Select */
  143. { 0x22, 0x00 }, /* DOUT Configuration VMON */
  144. { 0x23, 0x00 }, /* DOUT Configuration IMON */
  145. { 0x24, 0x00 }, /* DOUT Configuration VBAT */
  146. { 0x25, 0x00 }, /* DOUT Configuration VBST */
  147. { 0x26, 0x00 }, /* DOUT Configuration FLAG */
  148. { 0x27, 0xFF }, /* DOUT HiZ Configuration 1 */
  149. { 0x28, 0xFF }, /* DOUT HiZ Configuration 2 */
  150. { 0x29, 0xFF }, /* DOUT HiZ Configuration 3 */
  151. { 0x2A, 0xFF }, /* DOUT HiZ Configuration 4 */
  152. { 0x2B, 0x02 }, /* DOUT Drive Strength */
  153. { 0x2C, 0x90 }, /* Filters */
  154. { 0x2D, 0x00 }, /* Gain */
  155. { 0x2E, 0x02 }, /* Gain Ramping */
  156. { 0x2F, 0x00 }, /* Speaker Amplifier */
  157. { 0x30, 0x0A }, /* Threshold */
  158. { 0x31, 0x00 }, /* ALC Attack */
  159. { 0x32, 0x80 }, /* ALC Atten and Release */
  160. { 0x33, 0x00 }, /* ALC Infinite Hold Release */
  161. { 0x34, 0x92 }, /* ALC Configuration */
  162. { 0x35, 0x01 }, /* Boost Converter */
  163. { 0x36, 0x00 }, /* Block Enable */
  164. { 0x37, 0x00 }, /* Configuration */
  165. { 0x38, 0x00 }, /* Global Enable */
  166. { 0x3A, 0x00 }, /* Boost Limiter */
  167. };
  168. static const struct soc_enum max98926_dai_enum =
  169. SOC_ENUM_SINGLE(max98926_GAIN, 5, ARRAY_SIZE(dai_text), dai_text);
  170. static const struct soc_enum max98926_dai_input_enum =
  171. SOC_ENUM_SINGLE(max98926_SPK_AMP, 1, ARRAY_SIZE(dai_input_text), dai_input_text);
  172. static const struct soc_enum max98926_pdm_1_enum =
  173. SOC_ENUM_SINGLE(max98926_DAI_CLK_DIV_N_LSBS, 4, ARRAY_SIZE(pdm_1_text), pdm_1_text);
  174. static const struct soc_enum max98926_pdm_0_enum =
  175. SOC_ENUM_SINGLE(max98926_DAI_CLK_DIV_N_LSBS, 0, ARRAY_SIZE(pdm_0_text), pdm_0_text);
  176. static const struct soc_enum max98926_hpf_enum =
  177. SOC_ENUM_SINGLE(max98926_FILTERS, 0, ARRAY_SIZE(hpf_text), hpf_text);
  178. static const struct snd_kcontrol_new max98926_hpf_sel_mux =
  179. SOC_DAPM_ENUM("Rc Filter MUX Mux", max98926_hpf_enum);
  180. static const struct snd_kcontrol_new max98926_dai_sel_mux =
  181. SOC_DAPM_ENUM("DAI IN MUX Mux", max98926_dai_enum);
  182. static const struct snd_kcontrol_new max98926_input_sel_mux =
  183. SOC_DAPM_ENUM("INPUT SEL MUX Mux", max98926_dai_input_enum);
  184. static const struct snd_kcontrol_new max98926_pdm_1_sel_mux =
  185. SOC_DAPM_ENUM("PDM CHANNEL_1 MUX Mux", max98926_pdm_1_enum);
  186. static const struct snd_kcontrol_new max98926_pdm_0_sel_mux =
  187. SOC_DAPM_ENUM("PDM CHANNEL_0 MUX Mux", max98926_pdm_0_enum);
  188. static int max98926_get_switch_mixer(struct snd_kcontrol *kcontrol,
  189. struct snd_ctl_elem_value *ucontrol)
  190. {
  191. return 0;
  192. }
  193. static int max98926_put_switch_mixer(struct snd_kcontrol *kcontrol,
  194. struct snd_ctl_elem_value *ucontrol)
  195. {
  196. struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
  197. struct snd_soc_component *codec = component->codec;
  198. struct snd_soc_dapm_widget *widget = snd_kcontrol_chip(kcontrol);
  199. if (ucontrol->value.integer.value[0])
  200. snd_soc_dapm_mixer_update_power(widget, kcontrol, 1, NULL);
  201. else
  202. snd_soc_dapm_mixer_update_power(widget, kcontrol, 0 , NULL);
  203. return 1;
  204. }
  205. static const struct snd_kcontrol_new max98926_pdm_path_1_control =
  206. SOC_SINGLE_EXT("Switch", SND_SOC_NOPM, 0, 1, 0, max98926_get_switch_mixer, max98926_put_switch_mixer);
  207. static const struct snd_kcontrol_new max98926_pdm_path_0_control =
  208. SOC_SINGLE_EXT("Switch", SND_SOC_NOPM, 0, 1, 0, max98926_get_switch_mixer, max98926_put_switch_mixer);
  209. static int max98926_dac_event(struct snd_soc_dapm_widget *w,
  210. struct snd_kcontrol *kcontrol, int event)
  211. {
  212. struct snd_soc_codec *codec = w->codec;
  213. struct max98926_priv *max98926 = snd_soc_codec_get_drvdata(codec);
  214. switch (event) {
  215. case SND_SOC_DAPM_PRE_PMU:
  216. snd_soc_update_bits(codec,
  217. max98926_BLOCK_ENABLE,
  218. M98926_BST_EN_MASK |
  219. M98926_ADC_IMON_EN_MASK | M98926_ADC_VMON_EN_MASK,
  220. M98926_BST_EN_MASK |
  221. M98926_ADC_IMON_EN_MASK | M98926_ADC_VMON_EN_MASK);
  222. break;
  223. case SND_SOC_DAPM_POST_PMD:
  224. snd_soc_update_bits(codec,
  225. max98926_BLOCK_ENABLE, M98926_BST_EN_MASK |
  226. M98926_ADC_IMON_EN_MASK | M98926_ADC_VMON_EN_MASK, 0);
  227. break;
  228. default:
  229. return 0;
  230. }
  231. return 0;
  232. }
  233. static int pdm_enable_channel_ev(struct snd_soc_dapm_widget *w,
  234. struct snd_kcontrol *kcontrol, int event)
  235. {
  236. struct snd_soc_codec *codec = w->codec;
  237. struct max98926_priv *max98926 = snd_soc_codec_get_drvdata(codec);
  238. int ret, reg;
  239. ret = snd_soc_read(codec,
  240. max98926_DAI_CLK_DIV_N_LSBS);
  241. pr_err("%s 0x1f read 0x%x\n", __func__, ret);
  242. switch (event) {
  243. case SND_SOC_DAPM_PRE_PMU:
  244. /* enable current measurement */
  245. snd_soc_update_bits(codec,
  246. max98926_DAI_CLK_DIV_N_LSBS,
  247. max98926_PDM_CURRENT_MASK, max98926_PDM_CURRENT_MASK);
  248. /* enable voltage measurement */
  249. snd_soc_update_bits(codec,
  250. max98926_DAI_CLK_DIV_N_LSBS,
  251. max98926_PDM_VOLTAGE_MASK, max98926_PDM_VOLTAGE_MASK);
  252. break;
  253. case SND_SOC_DAPM_POST_PMD:
  254. snd_soc_update_bits(codec,
  255. max98926_DAI_CLK_DIV_N_LSBS,
  256. max98926_PDM_CURRENT_MASK, 0);
  257. snd_soc_update_bits(codec,
  258. max98926_DAI_CLK_DIV_N_LSBS,
  259. max98926_PDM_VOLTAGE_MASK, 0);
  260. break;
  261. }
  262. ret = snd_soc_read(codec,
  263. max98926_DAI_CLK_DIV_N_LSBS);
  264. pr_err("%s 0x1f read 0x%x\n", __func__, ret);
  265. return 0;
  266. }
  267. static const struct snd_soc_dapm_widget max98926_dapm_widgets[] = {
  268. SND_SOC_DAPM_AIF_IN("DAI_OUT", "HiFi Playback", 0, SND_SOC_NOPM, 0, 0),
  269. SND_SOC_DAPM_AIF_OUT("DAI_IN", "HiFi Capture", 0, SND_SOC_NOPM, 0, 0),
  270. SND_SOC_DAPM_MUX("DAI IN MUX", SND_SOC_NOPM, 0, 0,
  271. &max98926_dai_sel_mux),
  272. SND_SOC_DAPM_SWITCH("PDM PATH CH_1", SND_SOC_NOPM, 0, 0,
  273. &max98926_pdm_path_1_control),
  274. SND_SOC_DAPM_SWITCH("PDM PATH CH_0", SND_SOC_NOPM, 0, 0,
  275. &max98926_pdm_path_0_control),
  276. SND_SOC_DAPM_MUX("INPUT SEL MUX", SND_SOC_NOPM, 0, 0,
  277. &max98926_input_sel_mux),
  278. SND_SOC_DAPM_MUX_E("PDM CHANNEL_1 MUX", max98926_DAI_CLK_DIV_N_LSBS, 6, 0,
  279. &max98926_pdm_1_sel_mux, pdm_enable_channel_ev, SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  280. SND_SOC_DAPM_MUX_E("PDM CHANNEL_0 MUX", max98926_DAI_CLK_DIV_N_LSBS, 2, 0,
  281. &max98926_pdm_0_sel_mux, pdm_enable_channel_ev, SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  282. SND_SOC_DAPM_MUX("Rc Filter MUX", SND_SOC_NOPM, 0, 0,
  283. &max98926_hpf_sel_mux),
  284. SND_SOC_DAPM_DAC_E("Amp Enable", NULL, max98926_BLOCK_ENABLE,
  285. M98926_SPK_EN_SHIFT, 0, max98926_dac_event,
  286. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  287. SND_SOC_DAPM_SUPPLY("Global Enable", max98926_GLOBAL_ENABLE,
  288. M98926_EN_SHIFT, 0, NULL, 0),
  289. SND_SOC_DAPM_OUTPUT("BE_OUT"),
  290. SND_SOC_DAPM_INPUT("Speaker_Pdm"),
  291. };
  292. static const struct snd_soc_dapm_route max98926_audio_map[] = {
  293. {"DAI IN MUX", "Left", "DAI_OUT"},
  294. {"DAI IN MUX", "Right", "DAI_OUT"},
  295. {"DAI IN MUX", "LeftRight", "DAI_OUT"},
  296. {"DAI IN MUX", "LeftRightDiv2", "DAI_OUT"},
  297. {"Rc Filter MUX", "Disable", "DAI IN MUX"},
  298. {"Rc Filter MUX", "DC Block", "DAI IN MUX"},
  299. {"Rc Filter MUX", "100Hz", "DAI IN MUX"},
  300. {"Rc Filter MUX", "200Hz", "DAI IN MUX"},
  301. {"Rc Filter MUX", "400Hz", "DAI IN MUX"},
  302. {"Rc Filter MUX", "800Hz", "DAI IN MUX"},
  303. {"Amp Enable", NULL, "Rc Filter MUX"},
  304. {"Amp Enable", NULL, "Global Enable"},
  305. {"BE_OUT", NULL, "Amp Enable"},
  306. {"INPUT SEL MUX", "Pcm", "DAI_OUT"},
  307. {"INPUT SEL MUX", "Analog", "DAI_OUT"},
  308. {"Amp Enable", NULL, "INPUT SEL MUX"},
  309. #if 0
  310. {"PDM CHANNEL_1 MUX", "Voltage", "DAI_IN"},
  311. {"PDM CHANNEL_1 MUX", "Current", "DAI_IN"},
  312. {"PDM CHANNEL_0 MUX", "Voltage", "DAI_IN"},
  313. {"PDM CHANNEL_0 MUX", "Current", "DAI_IN"},
  314. {"PDM PATH CH_1", "Switch", "PDM CHANNEL_1 MUX"},
  315. {"PDM PATH CH_0", "Switch", "PDM CHANNEL_0 MUX"},
  316. {"Speaker_Pdm", NULL, "PDM PATH CH_1"},
  317. {"Speaker_Pdm", NULL, "PDM PATH CH_0"},
  318. #endif
  319. #if 1
  320. {"PDM CHANNEL_1 MUX", "Voltage", "DAI_OUT"},
  321. {"PDM CHANNEL_1 MUX", "Current", "DAI_OUT"},
  322. {"PDM CHANNEL_0 MUX", "Voltage", "DAI_OUT"},
  323. {"PDM CHANNEL_0 MUX", "Current", "DAI_OUT"},
  324. {"PDM PATH CH_1", "Switch", "PDM CHANNEL_1 MUX"},
  325. {"PDM PATH CH_0", "Switch", "PDM CHANNEL_0 MUX"},
  326. {"Amp Enable", NULL, "PDM PATH CH_1"},
  327. {"Amp Enable", NULL, "PDM PATH CH_0"},
  328. #endif
  329. };
  330. static bool max98926_volatile_register(struct device *dev, unsigned int reg)
  331. {
  332. switch (reg) {
  333. case max98926_VBAT_DATA:
  334. case max98926_VBST_DATA:
  335. case max98926_LIVE_STATUS0:
  336. case max98926_LIVE_STATUS1:
  337. case max98926_LIVE_STATUS2:
  338. case max98926_STATE0:
  339. case max98926_STATE1:
  340. case max98926_STATE2:
  341. case max98926_FLAG0:
  342. case max98926_FLAG1:
  343. case max98926_FLAG2:
  344. case max98926_REV_VERSION:
  345. case max98926_DAI_CLK_DIV_N_LSBS:
  346. return true;
  347. default:
  348. return false;
  349. }
  350. }
  351. static bool max98926_readable_register(struct device *dev, unsigned int reg)
  352. {
  353. switch (reg) {
  354. case max98926_IRQ_CLEAR0:
  355. case max98926_IRQ_CLEAR1:
  356. case max98926_IRQ_CLEAR2:
  357. case max98926_ALC_HOLD_RLS:
  358. return false;
  359. default:
  360. return true;
  361. }
  362. }
  363. DECLARE_TLV_DB_SCALE(max98926_spk_tlv, -600, 100, 0);
  364. static int max98926_reg_put(struct snd_kcontrol *kcontrol,
  365. struct snd_ctl_elem_value *ucontrol, unsigned int reg,
  366. unsigned int mask, unsigned int shift)
  367. {
  368. struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
  369. struct snd_soc_component *codec = component->codec;
  370. struct max98926_priv *max98926 = snd_soc_codec_get_drvdata(codec);
  371. unsigned int sel = ucontrol->value.integer.value[0];
  372. pr_err("%s codec = %p\n", __func__, codec);
  373. snd_soc_update_bits(codec, reg, mask, sel << shift);
  374. pr_err("%s: register 0x%02X, value 0x%02X\n",
  375. __func__, reg, sel);
  376. return 0;
  377. }
  378. static int speaker_enable;
  379. static int max98926_spk_enable_get(struct snd_kcontrol *kcontrol,
  380. struct snd_ctl_elem_value *ucontrol)
  381. {
  382. pr_err("%s , speaker_enable = %d\n", __func__, speaker_enable);
  383. ucontrol->value.integer.value[0] = speaker_enable;
  384. return 0;
  385. }
  386. static int max98926_spk_enable_put(struct snd_kcontrol *kcontrol,
  387. struct snd_ctl_elem_value *ucontrol)
  388. {
  389. struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
  390. struct snd_soc_component *codec = component->codec;
  391. struct max98926_priv *max98926 = snd_soc_codec_get_drvdata(codec);
  392. pr_err("%s , codec = %p\n", __func__, codec);
  393. if (ucontrol->value.integer.value[0] == 1) {
  394. snd_soc_update_bits(codec, max98926_BLOCK_ENABLE,
  395. (M98926_SPK_EN_MASK | M98926_BST_EN_MASK |
  396. M98926_ADC_IMON_EN_MASK | M98926_ADC_VMON_EN_MASK,
  397. M98926_SPK_EN_MASK | M98926_BST_EN_MASK |
  398. M98926_ADC_IMON_EN_MASK | M98926_ADC_VMON_EN_MASK),
  399. (M98926_SPK_EN_MASK | M98926_BST_EN_MASK |
  400. M98926_ADC_IMON_EN_MASK | M98926_ADC_VMON_EN_MASK,
  401. M98926_SPK_EN_MASK | M98926_BST_EN_MASK |
  402. M98926_ADC_IMON_EN_MASK | M98926_ADC_VMON_EN_MASK)
  403. );
  404. snd_soc_update_bits(codec, max98926_BLOCK_ENABLE,
  405. (M98926_SPK_EN_MASK | M98926_BST_EN_MASK |
  406. M98926_ADC_IMON_EN_MASK | M98926_ADC_VMON_EN_MASK,
  407. M98926_SPK_EN_MASK | M98926_BST_EN_MASK |
  408. M98926_ADC_IMON_EN_MASK | M98926_ADC_VMON_EN_MASK),
  409. (M98926_SPK_EN_MASK | M98926_BST_EN_MASK |
  410. M98926_ADC_IMON_EN_MASK | M98926_ADC_VMON_EN_MASK,
  411. M98926_SPK_EN_MASK | M98926_BST_EN_MASK |
  412. M98926_ADC_IMON_EN_MASK | M98926_ADC_VMON_EN_MASK)
  413. );
  414. snd_soc_update_bits(codec, max98926_GLOBAL_ENABLE,
  415. M98926_EN_MASK, M98926_EN_MASK);
  416. max98926_set_sense_data(max98926);
  417. } else if (ucontrol->value.integer.value[0] == 0) {
  418. snd_soc_update_bits(codec, max98926_BLOCK_ENABLE
  419. , M98926_SPK_EN_MASK | M98926_BST_EN_MASK |
  420. M98926_ADC_IMON_EN_MASK | M98926_ADC_VMON_EN_MASK,
  421. 0);
  422. snd_soc_update_bits(codec, max98926_GLOBAL_ENABLE,
  423. M98926_EN_MASK, 0);
  424. }
  425. speaker_enable = ucontrol->value.integer.value[0];
  426. return 1;
  427. }
  428. static const char *const spk_enable_text[] = {"Off", "On"};
  429. static const struct soc_enum max98926_global_enum[] = {
  430. SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(spk_enable_text), spk_enable_text),
  431. };
  432. static const struct snd_kcontrol_new max98926_snd_controls[] = {
  433. SOC_SINGLE_TLV("Speaker Volume", max98926_GAIN,
  434. M98926_SPK_GAIN_SHIFT, (1 << M98926_SPK_GAIN_WIDTH) - 1, 0,
  435. max98926_spk_tlv),
  436. SOC_SINGLE("Ramp Switch", max98926_GAIN_RAMPING,
  437. M98926_SPK_RMP_EN_SHIFT, 1, 0),
  438. SOC_SINGLE("ZCD Switch", max98926_GAIN_RAMPING,
  439. M98926_SPK_ZCD_EN_SHIFT, 1, 0),
  440. SOC_SINGLE("ALC Switch", max98926_THRESHOLD,
  441. M98926_ALC_EN_SHIFT, 1, 0),
  442. SOC_SINGLE("ALC Threshold", max98926_THRESHOLD, M98926_ALC_TH_SHIFT,
  443. (1 << M98926_ALC_TH_WIDTH) - 1, 0),
  444. SOC_ENUM("Boost Output Voltage", max98926_boost_voltage),
  445. SOC_SINGLE_EXT("Speaker ZCD", 0, 0, 1, 0,
  446. max98926_spk_zcd_get, max98926_spk_zcd_put),
  447. SOC_ENUM_EXT("Spk_Enable", max98926_global_enum[0], max98926_spk_enable_get, max98926_spk_enable_put),
  448. };
  449. /* codec sample rate and n/m dividers parameter table */
  450. static const struct {
  451. int rate;
  452. int sr;
  453. int divisors[3][2];
  454. } rate_table[] = {
  455. {
  456. .rate = 8000,
  457. .sr = 0,
  458. .divisors = { {1, 375}, {5, 1764}, {1, 384} }
  459. },
  460. {
  461. .rate = 11025,
  462. .sr = 1,
  463. .divisors = { {147, 40000}, {1, 256}, {147, 40960} }
  464. },
  465. {
  466. .rate = 12000,
  467. .sr = 2,
  468. .divisors = { {1, 250}, {5, 1176}, {1, 256} }
  469. },
  470. {
  471. .rate = 16000,
  472. .sr = 3,
  473. .divisors = { {2, 375}, {5, 882}, {1, 192} }
  474. },
  475. {
  476. .rate = 22050,
  477. .sr = 4,
  478. .divisors = { {147, 20000}, {1, 128}, {147, 20480} }
  479. },
  480. {
  481. .rate = 24000,
  482. .sr = 5,
  483. .divisors = { {1, 125}, {5, 588}, {1, 128} }
  484. },
  485. {
  486. .rate = 32000,
  487. .sr = 6,
  488. .divisors = { {4, 375}, {5, 441}, {1, 96} }
  489. },
  490. {
  491. .rate = 44100,
  492. .sr = 7,
  493. .divisors = { {147, 10000}, {1, 64}, {147, 10240} }
  494. },
  495. {
  496. .rate = 48000,
  497. .sr = 8,
  498. .divisors = { {2, 125}, {5, 294}, {1, 64} }
  499. },
  500. };
  501. static inline int max98926_rate_value(struct snd_soc_codec *codec,
  502. int rate, int clock, int *value, int *n, int *m)
  503. {
  504. int ret = -EINVAL;
  505. int i;
  506. for (i = 0; i < ARRAY_SIZE(rate_table); i++) {
  507. if (rate_table[i].rate >= rate) {
  508. *value = rate_table[i].sr;
  509. *n = rate_table[i].divisors[clock][0];
  510. *m = rate_table[i].divisors[clock][1];
  511. ret = 0;
  512. break;
  513. }
  514. }
  515. dev_dbg(codec->dev, "%s: sample rate is %d, returning %d\n",
  516. __func__, rate_table[i].rate, *value);
  517. return ret;
  518. }
  519. static void max98926_set_sense_data(struct max98926_priv *max98926)
  520. {
  521. struct snd_soc_codec *codec = max98926->codec;
  522. pr_err("%s %d %d\n", __func__, max98926->i_slot, max98926->v_slot);
  523. /* set VMON slots */
  524. snd_soc_update_bits(codec,
  525. max98926_DOUT_CFG_VMON,
  526. M98926_DAI_VMON_EN_MASK, M98926_DAI_VMON_EN_MASK);
  527. snd_soc_update_bits(codec,
  528. max98926_DOUT_CFG_VMON,
  529. M98926_DAI_VMON_SLOT_MASK, max98926->v_slot);
  530. /* set IMON slots */
  531. snd_soc_update_bits(codec,
  532. max98926_DOUT_CFG_IMON,
  533. M98926_DAI_IMON_EN_MASK, M98926_DAI_IMON_EN_MASK);
  534. snd_soc_update_bits(codec,
  535. max98926_DOUT_CFG_IMON,
  536. M98926_DAI_IMON_SLOT_MASK, max98926->i_slot);
  537. pr_err("%s codec = %p", __func__, codec);
  538. }
  539. static int max98926_dai_set_fmt(struct snd_soc_dai *codec_dai,
  540. unsigned int fmt)
  541. {
  542. struct snd_soc_codec *codec = codec_dai->codec;
  543. struct max98926_priv *max98926 = snd_soc_codec_get_drvdata(codec);
  544. unsigned int invert = 0;
  545. dev_dbg(codec->dev, "%s: fmt 0x%08X\n", __func__, fmt);
  546. switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
  547. case SND_SOC_DAIFMT_CBS_CFS:
  548. max98926_set_sense_data(max98926);
  549. break;
  550. case SND_SOC_DAIFMT_CBM_CFM:
  551. case SND_SOC_DAIFMT_CBS_CFM:
  552. case SND_SOC_DAIFMT_CBM_CFS:
  553. default:
  554. dev_err(codec->dev, "DAI clock mode unsupported");
  555. return -EINVAL;
  556. }
  557. switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
  558. case SND_SOC_DAIFMT_NB_NF:
  559. break;
  560. case SND_SOC_DAIFMT_NB_IF:
  561. invert = M98926_DAI_WCI_MASK;
  562. break;
  563. case SND_SOC_DAIFMT_IB_NF:
  564. invert = M98926_DAI_BCI_MASK;
  565. break;
  566. case SND_SOC_DAIFMT_IB_IF:
  567. invert = M98926_DAI_BCI_MASK | M98926_DAI_WCI_MASK;
  568. break;
  569. default:
  570. dev_err(codec->dev, "DAI invert mode unsupported");
  571. return -EINVAL;
  572. }
  573. snd_soc_update_bits(codec, max98926_FORMAT,
  574. M98926_DAI_BCI_MASK, invert);
  575. return 0;
  576. }
  577. static int max98926_set_clock(struct max98926_priv *max98926,
  578. struct snd_pcm_hw_params *params)
  579. {
  580. unsigned int dai_sr = 0, clock, n, m;
  581. struct snd_soc_codec *codec = max98926->codec;
  582. int rate = params_rate(params);
  583. /* BCLK/LRCLK ratio calculation */
  584. int blr_clk_ratio = params_channels(params) * max98926->ch_size;
  585. pr_err("%s %d %d\n", __func__, params_channels(params), max98926->ch_size);
  586. switch (blr_clk_ratio) {
  587. case 32:
  588. snd_soc_update_bits(codec,
  589. max98926_DAI_CLK_MODE2,
  590. M98926_DAI_BSEL_MASK, M98926_DAI_BSEL_32);
  591. break;
  592. case 48:
  593. snd_soc_update_bits(codec,
  594. max98926_DAI_CLK_MODE2,
  595. M98926_DAI_BSEL_MASK, M98926_DAI_BSEL_48);
  596. break;
  597. case 64:
  598. snd_soc_update_bits(codec,
  599. max98926_DAI_CLK_MODE2,
  600. M98926_DAI_BSEL_MASK, M98926_DAI_BSEL_64);
  601. break;
  602. default:
  603. return -EINVAL;
  604. }
  605. switch (max98926->sysclk) {
  606. case 6000000:
  607. clock = 0;
  608. break;
  609. case 11289600:
  610. clock = 1;
  611. break;
  612. case 12000000:
  613. clock = 0;
  614. break;
  615. case 12288000:
  616. clock = 2;
  617. break;
  618. default:
  619. pr_err("unsupported sysclk %d\n",
  620. max98926->sysclk);
  621. break;
  622. }
  623. if (max98926_rate_value(codec, rate, clock, &dai_sr, &n, &m)) {
  624. pr_err("%s return -EINVAL\n", __func__);
  625. return -EINVAL;
  626. }
  627. /* set DAI_SR to correct LRCLK frequency */
  628. snd_soc_update_bits(codec,
  629. max98926_DAI_CLK_MODE2,
  630. M98926_DAI_SR_MASK, dai_sr << M98926_DAI_SR_SHIFT);
  631. pr_err("%s return 0\n", __func__);
  632. return 0;
  633. }
  634. static int max98926_dai_hw_params(struct snd_pcm_substream *substream,
  635. struct snd_pcm_hw_params *params,
  636. struct snd_soc_dai *dai)
  637. {
  638. struct snd_soc_codec *codec = dai->codec;
  639. struct max98926_priv *max98926 = snd_soc_codec_get_drvdata(codec);
  640. int ret, reg;
  641. ret = snd_soc_read(codec,
  642. max98926_DAI_CLK_DIV_N_LSBS);
  643. pr_err("%s 0x1f read 0x%x\n", __func__, ret);
  644. pr_err("%s %d\n", __func__, snd_pcm_format_width(params_format(params)));
  645. switch (snd_pcm_format_width(params_format(params))) {
  646. case 16:
  647. snd_soc_update_bits(codec,
  648. max98926_FORMAT,
  649. M98926_DAI_CHANSZ_MASK, M98926_DAI_CHANSZ_16);
  650. max98926->ch_size = 16;
  651. break;
  652. case 24:
  653. snd_soc_update_bits(codec,
  654. max98926_FORMAT,
  655. M98926_DAI_CHANSZ_MASK, M98926_DAI_CHANSZ_32);
  656. max98926->ch_size = 32;
  657. break;
  658. case 32:
  659. snd_soc_update_bits(codec,
  660. max98926_FORMAT,
  661. M98926_DAI_CHANSZ_MASK, M98926_DAI_CHANSZ_32);
  662. max98926->ch_size = 32;
  663. break;
  664. default:
  665. pr_err("%s: format unsupported %d",
  666. __func__, params_format(params));
  667. return -EINVAL;
  668. }
  669. dev_dbg(codec->dev, "%s: format supported %d",
  670. __func__, params_format(params));
  671. return max98926_set_clock(max98926, params);
  672. }
  673. static int max98926_dai_set_sysclk(struct snd_soc_dai *dai,
  674. int clk_id, unsigned int freq, int dir)
  675. {
  676. struct snd_soc_codec *codec = dai->codec;
  677. struct max98926_priv *max98926 = snd_soc_codec_get_drvdata(codec);
  678. max98926->sysclk = freq;
  679. return 0;
  680. }
  681. #define max98926_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE)
  682. static struct snd_soc_dai_ops max98926_dai_ops = {
  683. .set_sysclk = max98926_dai_set_sysclk,
  684. .set_fmt = max98926_dai_set_fmt,
  685. .hw_params = max98926_dai_hw_params,
  686. };
  687. static struct snd_soc_dai_driver max98926_dai[] = {
  688. {
  689. .name = "max98926-aif1",
  690. .playback = {
  691. .stream_name = "Speaker_PLayback",
  692. .channels_min = 1,
  693. .channels_max = 2,
  694. .rates = SNDRV_PCM_RATE_8000_48000,
  695. .formats = max98926_FORMATS,
  696. },
  697. .capture = {
  698. .stream_name = "Speaker_PLayback",
  699. .channels_min = 1,
  700. .channels_max = 2,
  701. .rates = SNDRV_PCM_RATE_8000_48000,
  702. .formats = max98926_FORMATS,
  703. },
  704. .ops = &max98926_dai_ops,
  705. }
  706. };
  707. static int max98926_probe(struct snd_soc_codec *codec)
  708. {
  709. int ret = 0;
  710. struct max98926_priv *max98926 = snd_soc_codec_get_drvdata(codec);
  711. max98926->codec = codec;
  712. codec->control_data = codec;
  713. pr_err("%s codec = %p", __func__, codec);
  714. speaker_enable = false;
  715. /*
  716. ret = snd_soc_codec_set_cache_io(codec, 8, 8, SND_SOC_I2C);
  717. if (ret != 0) {
  718. dev_err(codec->dev, "Failed to set cache I/O: %d\n", ret);
  719. return ret;
  720. }
  721. */
  722. ret = snd_soc_read(codec,
  723. max98926_REV_VERSION);
  724. if ((ret < 0) ||
  725. ((ret != max98926_VERSION) &&
  726. (ret != max98926_VERSION1))) {
  727. pr_err("device initialization error (%d )\n",
  728. ret);
  729. }
  730. pr_err("device version 0x%02X\n", ret);
  731. /* can be configured to any other value supported by this chip */
  732. max98926->sysclk = 12288000;
  733. max98926->spk_gain = 0x14;
  734. snd_soc_write(codec, max98926_GLOBAL_ENABLE, 0x00);
  735. /* It's not the default but we need to set DAI_DLY */
  736. snd_soc_write(codec,
  737. max98926_FORMAT, M98926_DAI_DLY_MASK);
  738. snd_soc_write(codec, max98926_TDM_SLOT_SELECT, 0xC8);
  739. snd_soc_write(codec, max98926_DOUT_HIZ_CFG1, 0xFF);
  740. snd_soc_write(codec, max98926_DOUT_HIZ_CFG2, 0xFF);
  741. snd_soc_write(codec, max98926_DOUT_HIZ_CFG3, 0xFF);
  742. snd_soc_write(codec, max98926_DOUT_HIZ_CFG4, 0xCC);
  743. snd_soc_write(codec, max98926_FILTERS, 0xD8);
  744. snd_soc_write(codec, max98926_ALC_CONFIGURATION, 0xF8);
  745. snd_soc_write(codec, max98926_GAIN, 0x1a);
  746. /* Disable ALC muting */
  747. snd_soc_write(codec, max98926_BOOST_LIMITER, 0xF8);
  748. if (codec->dev->of_node)
  749. dev_set_name(&codec->dev, "%s", "MAX98926_MT");
  750. return 0;
  751. }
  752. static unsigned int max98926_read(struct snd_soc_codec *codec, unsigned int addr)
  753. {
  754. unsigned short Ret = 0;
  755. max98926_ReadReg((unsigned short)addr, (unsigned short *)&Ret);
  756. return Ret;
  757. }
  758. static int max98926_write(struct snd_soc_codec *codec, unsigned int adrress, unsigned int value)
  759. {
  760. int ret = 0;
  761. ret = max98926_WriteReg(adrress , value);
  762. return ret;
  763. }
  764. static struct snd_soc_codec_driver soc_codec_dev_max98926 = {
  765. .probe = max98926_probe,
  766. .controls = max98926_snd_controls,
  767. .num_controls = ARRAY_SIZE(max98926_snd_controls),
  768. .dapm_routes = max98926_audio_map,
  769. .num_dapm_routes = ARRAY_SIZE(max98926_audio_map),
  770. .dapm_widgets = max98926_dapm_widgets,
  771. .num_dapm_widgets = ARRAY_SIZE(max98926_dapm_widgets),
  772. .read = max98926_read,
  773. .write = max98926_write,
  774. };
  775. static struct regmap_config max98926_regmap = {
  776. .reg_bits = 8,
  777. .val_bits = 8,
  778. .max_register = max98926_REV_VERSION,
  779. .reg_defaults = max98926_reg,
  780. .num_reg_defaults = ARRAY_SIZE(max98926_reg),
  781. .volatile_reg = max98926_volatile_register,
  782. .readable_reg = max98926_readable_register,
  783. .cache_type = REGCACHE_RBTREE,
  784. };
  785. static ssize_t max_i2c_write(const char *data, size_t count)
  786. {
  787. int ret;
  788. pr_err("%s count = %zu\n", __func__, count);
  789. ret = max_i2c_master_send(new_client, data, count);
  790. return ret;
  791. }
  792. static int max_i2c_master_send(const struct i2c_client *client, const char *buf, int count)
  793. {
  794. int ret;
  795. struct i2c_adapter *adap = client->adapter;
  796. struct i2c_msg msg;
  797. #ifdef CONFIG_MTK_I2C_EXTENSION
  798. if (count <= 8)
  799. msg.addr = client->addr & I2C_MASK_FLAG;
  800. else
  801. msg.addr = client->addr & I2C_MASK_FLAG | I2C_DMA_FLAG;
  802. #endif
  803. msg.flags = client->flags & I2C_M_TEN;
  804. msg.len = count;
  805. msg.buf = (char *)buf;
  806. #ifdef CONFIG_MTK_I2C_EXTENSION
  807. msg.ext_flag = client->ext_flag;
  808. #endif
  809. ret = i2c_transfer(adap, &msg, 1);
  810. /*
  811. * If everything went ok (i.e. 1 msg transmitted), return #bytes
  812. * transmitted, else error code.
  813. */
  814. return (ret == 1) ? count : ret;
  815. }
  816. static int max98926_WriteReg(u16 a_u2Addr, u16 a_u2Data)
  817. {
  818. pr_err("%s\n", __func__);
  819. int i4RetValue = 0;
  820. char puSendCmd[2] = {(char)a_u2Addr , (char)a_u2Data};
  821. #ifdef CONFIG_MTK_I2C_EXTENSION
  822. new_client->ext_flag = 0;
  823. #endif
  824. i4RetValue = i2c_master_send(new_client, puSendCmd, 2);
  825. if (i4RetValue < 0) {
  826. pr_err("max98926_WriteReg I2C send failed!!\n");
  827. return -1;
  828. }
  829. return 0;
  830. }
  831. static int max98926_ReadReg(u16 a_u2Addr, unsigned short *a_pu2Result)
  832. {
  833. int i4RetValue = 0;
  834. char pBuff;
  835. int ret;
  836. struct i2c_adapter *adap = new_client->adapter;
  837. unsigned short buffer[2];
  838. #ifdef CONFIG_MTK_I2C_EXTENSION
  839. new_client->ext_flag = ((new_client->ext_flag) & I2C_MASK_FLAG) | I2C_WR_FLAG | I2C_RS_FLAG;
  840. if (i2c_master_send(new_client, &a_u2Addr, 1 << 8 | 1) != 1)
  841. pr_err("max98926_ReadReg I2C send failed!!\n");
  842. *a_pu2Result = a_u2Addr;
  843. #else
  844. struct i2c_msg wr_msgs[2];
  845. wr_msgs[0].addr = new_client->addr;
  846. wr_msgs[0].flags = 0x00;
  847. wr_msgs[0].len = 1;
  848. wr_msgs[0].buf = &buffer[0];
  849. wr_msgs[1].addr = new_client->addr;
  850. wr_msgs[1].flags |= I2C_M_RD;
  851. wr_msgs[1].len = 1;
  852. wr_msgs[1].buf = &buffer[1];
  853. ret = i2c_transfer(adap, &wr_msgs, 2);
  854. *a_pu2Result = buffer[1];
  855. #endif
  856. return 0;
  857. }
  858. static int max98926_i2c_probe(struct i2c_client *i2c,
  859. const struct i2c_device_id *id)
  860. {
  861. pr_err("%s\n", __func__);
  862. new_client = i2c;
  863. #ifdef CONFIG_MTK_I2C_EXTENSION
  864. new_client->timing = 100;
  865. new_client->ext_flag = ((new_client->ext_flag) & I2C_MASK_FLAG) | I2C_WR_FLAG | I2C_RS_FLAG;
  866. #endif
  867. struct snd_soc_codec *codec = NULL;
  868. int ret, reg;
  869. u32 value;
  870. struct max98926_priv *max98926 = NULL;
  871. /*
  872. max98926_regulator_config(i2c, of_property_read_bool(i2c->dev.of_node,
  873. "max98926,i2c-pull-up"), 1);
  874. */
  875. max98926 = devm_kzalloc(&i2c->dev,
  876. sizeof(*max98926), GFP_KERNEL);
  877. if (!max98926)
  878. return -ENOMEM;
  879. pr_err("max98926 = %p\n", max98926);
  880. i2c_set_clientdata(i2c, max98926);
  881. /*
  882. max98926->regmap = devm_regmap_init_i2c(i2c, &max98926_regmap);
  883. if (IS_ERR(max98926->regmap))
  884. {
  885. ret = PTR_ERR(max98926->regmap);
  886. dev_err(&i2c->dev,"Failed to allocate regmap: %d\n", ret);
  887. goto err_out;
  888. }
  889. */
  890. if (!of_property_read_u32(i2c->dev.of_node, "vmon-slot-no", &value)) {
  891. if (value > M98926_DAI_VMON_SLOT_1E_1F) {
  892. dev_err(&i2c->dev, "vmon slot number is wrong:\n");
  893. return -EINVAL;
  894. }
  895. max98926->v_slot = value;
  896. } else {
  897. max98926->v_slot = 0;
  898. }
  899. if (!of_property_read_u32(i2c->dev.of_node, "imon-slot-no", &value)) {
  900. if (value > M98926_DAI_IMON_SLOT_1E_1F) {
  901. dev_err(&i2c->dev, "imon slot number is wrong:\n");
  902. return -EINVAL;
  903. }
  904. max98926->i_slot = value;
  905. } else {
  906. max98926->i_slot = 4;
  907. }
  908. pr_err("4 %s max98926->v_slot = %d max98926->i_slot = %d\n", __func__, max98926->v_slot, max98926->i_slot);
  909. if (&i2c->dev.of_node)
  910. dev_set_name(&i2c->dev, "%s", "MAX98926_MT");
  911. ret = snd_soc_register_codec(&i2c->dev, &soc_codec_dev_max98926,
  912. max98926_dai, ARRAY_SIZE(max98926_dai));
  913. if (ret < 0)
  914. dev_err(&i2c->dev, "Failed to register codec: %d\n", ret);
  915. pr_err("%s ret = %d\n", __func__, ret);
  916. err_out:
  917. return ret;
  918. }
  919. static int max98926_i2c_remove(struct i2c_client *client)
  920. {
  921. snd_soc_unregister_codec(&client->dev);
  922. return 0;
  923. }
  924. static const struct i2c_device_id max98926_i2c_id[] = {
  925. { "max98926L", 0 },
  926. { }
  927. };
  928. MODULE_DEVICE_TABLE(i2c, max98926_i2c_id);
  929. static const struct of_device_id max98926_of_match[] = {
  930. { .compatible = "mediatek,speaker_amp", },
  931. { }
  932. };
  933. MODULE_DEVICE_TABLE(of, max98926_of_match);
  934. static struct i2c_driver max98926_i2c_driver = {
  935. .driver = {
  936. .name = "speaker_amp",
  937. .owner = THIS_MODULE,
  938. .of_match_table = of_match_ptr(max98926_of_match),
  939. .pm = NULL,
  940. },
  941. .probe = max98926_i2c_probe,
  942. .remove = max98926_i2c_remove,
  943. .id_table = max98926_i2c_id,
  944. };
  945. /*
  946. static struct i2c_board_info __initdata max_i2c_board_info[] = {
  947. {
  948. I2C_BOARD_INFO("max98926L", 0x31), // if 0x31 is your device address_space
  949. },
  950. };
  951. */
  952. static struct platform_device *Max98926_dev;
  953. static int __init max98926_init(void)
  954. {
  955. int ret = 0;
  956. pr_err("+max98926_init\n");
  957. Max98926_dev = platform_device_alloc("max98926L", -1);
  958. if (!Max98926_dev)
  959. return -ENOMEM;
  960. ret = platform_device_add(Max98926_dev);
  961. if (ret != 0) {
  962. platform_device_put(Max98926_dev);
  963. return ret;
  964. }
  965. /*
  966. i2c_register_board_info(MAX98926_I2C_Channel, max_i2c_board_info, ARRAY_SIZE(max_i2c_board_info));
  967. */
  968. if (i2c_add_driver(&max98926_i2c_driver)) {
  969. pr_err("fail to add device into i2c");
  970. return -1;
  971. }
  972. pr_err("-max98926_init\n");
  973. return 0;
  974. }
  975. subsys_initcall(max98926_init);
  976. static void __exit max98926_exit(void)
  977. {
  978. i2c_del_driver(&max98926_i2c_driver);
  979. }
  980. module_exit(max98926_exit);
  981. /* replace with init_call and module exit.
  982. module_i2c_driver(max98926_i2c_driver)
  983. */
  984. MODULE_DESCRIPTION("ALSA SoC max98926 driver");
  985. MODULE_AUTHOR("Ralph Birt <rdbirt@gmail.com>, Anish kumar <anish.kumar@maximintegrated.com>");
  986. MODULE_LICENSE("GPL");