mt6391.c 101 KB

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  1. /* Copyright (c) 2011-2013, The Linux Foundation. All rights reserved.
  2. *
  3. * This program is free software; you can redistribute it and/or modify
  4. * it under the terms of the GNU General Public License version 2 and
  5. * only version 2 as published by the Free Software Foundation.
  6. *
  7. * This program is distributed in the hope that it will be useful,
  8. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  9. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  10. * GNU General Public License for more details.
  11. */
  12. #include <linux/slab.h>
  13. #include <linux/delay.h>
  14. #include <linux/module.h>
  15. #include <linux/of.h>
  16. #include <linux/debugfs.h>
  17. #include <sound/soc.h>
  18. #include "mt6391.h"
  19. #include <linux/mfd/mt6397/registers.h>
  20. #define MT6397_CODEC_NAME "mt6397-codec"
  21. #define PMIC6397_E1_CID_CODE 0x1097
  22. #define ENUM_TO_STR(enum) #enum
  23. #define USE_MT6397_REGMAP
  24. /* #define USE_PMIC_WRAP_DRIVER */
  25. #if defined(USE_MT6397_REGMAP)
  26. #include <linux/mfd/mt6397/core.h>
  27. #elif defined(USE_PMIC_WRAP_DRIVER)
  28. #include <mt_pmic_wrap.h>
  29. #include <mt-plat/upmu_common.h>
  30. #endif
  31. #define MT6397_TRIM_ADDRESS1 (MT6397_EFUSE_DOUT_192_207)
  32. #define MT6397_TRIM_ADDRESS2 (MT6397_EFUSE_DOUT_208_223)
  33. /* enum definition */
  34. enum mt6391_device_volume {
  35. MT6391_VOL_HSOUTL = 0,
  36. MT6391_VOL_HSOUTR,
  37. MT6391_VOL_HPOUTL,
  38. MT6391_VOL_HPOUTR,
  39. MT6391_VOL_SPKL,
  40. MT6391_VOL_SPKR,
  41. MT6391_VOL_SPEAKER_HEADSET_R,
  42. MT6391_VOL_SPEAKER_HEADSET_L,
  43. MT6391_VOL_IV_BUFFER,
  44. MT6391_VOL_LINEOUTL,
  45. MT6391_VOL_LINEOUTR,
  46. MT6391_VOL_LINEINL,
  47. MT6391_VOL_LINEINR,
  48. MT6391_VOL_MICAMPL,
  49. MT6391_VOL_MICAMPR,
  50. MT6391_VOL_LEVELSHIFTL,
  51. MT6391_VOL_LEVELSHIFTR,
  52. MT6391_VOL_TYPE_MAX
  53. };
  54. enum mt6391_device_mux {
  55. MT6391_MUX_VOICE = 0,
  56. MT6391_MUX_AUDIO,
  57. MT6391_MUX_IV_BUFFER,
  58. MT6391_MUX_LINEIN_STEREO,
  59. MT6391_MUX_LINEIN_L,
  60. MT6391_MUX_LINEIN_R,
  61. MT6391_MUX_LINEIN_AUDIO_MONO,
  62. MT6391_MUX_LINEIN_AUDIO_STEREO,
  63. MT6391_MUX_IN_MIC1,
  64. MT6391_MUX_IN_MIC2,
  65. MT6391_MUX_IN_MIC3,
  66. MT6391_MUX_IN_PREAMP_1,
  67. MT6391_MUX_IN_PREAMP_2,
  68. MT6391_MUX_IN_LEVEL_SHIFT_BUFFER,
  69. MT6391_MUX_MUTE,
  70. MT6391_MUX_OPEN,
  71. MT6391_MUX_MAX_TYPE
  72. };
  73. enum mt6391_device_type {
  74. MT6391_DEV_OUT_EARPIECER = 0,
  75. MT6391_DEV_OUT_EARPIECEL,
  76. MT6391_DEV_OUT_HEADSETR,
  77. MT6391_DEV_OUT_HEADSETL,
  78. MT6391_DEV_OUT_SPEAKERR,
  79. MT6391_DEV_OUT_SPEAKERL,
  80. MT6391_DEV_OUT_SPEAKER_HEADSET_R,
  81. MT6391_DEV_OUT_SPEAKER_HEADSET_L,
  82. MT6391_DEV_IN_ADC1,
  83. MT6391_DEV_IN_ADC2,
  84. MT6391_DEV_IN_PREAMP_L,
  85. MT6391_DEV_IN_PREAMP_R,
  86. MT6391_DEV_IN_DIGITAL_MIC,
  87. MT6391_DEV_MAX,
  88. MT6391_DEV_OUT_MAX = MT6391_DEV_OUT_SPEAKER_HEADSET_L + 1,
  89. MT6391_DEV_ADC_MAX = MT6391_DEV_IN_ADC2 + 1,
  90. MT6391_DEV_IN_MAX = MT6391_DEV_IN_DIGITAL_MIC + 1,
  91. };
  92. enum mt6391_adda_type {
  93. MT6391_ADDA_DAC,
  94. MT6391_ADDA_ADC,
  95. MT6391_ADDA_MAX
  96. };
  97. enum mt6391_speaker_mode {
  98. MT6391_CLASS_D = 0,
  99. MT6391_CLASS_AB,
  100. };
  101. enum mt6391_speaker_channel_sel {
  102. MT6391_CHANNEL_SEL_STEREO = 0,
  103. MT6391_CHANNEL_SEL_MONO_LEFT,
  104. MT6391_CHANNEL_SEL_MONO_RIGHT,
  105. };
  106. enum mt6391_loopback {
  107. CODEC_LOOPBACK_NONE = 0,
  108. CODEC_LOOPBACK_AMIC_TO_SPK,
  109. CODEC_LOOPBACK_AMIC_TO_HP,
  110. CODEC_LOOPBACK_DMIC_TO_SPK,
  111. CODEC_LOOPBACK_DMIC_TO_HP,
  112. CODEC_LOOPBACK_HEADSET_MIC_TO_SPK,
  113. CODEC_LOOPBACK_HEADSET_MIC_TO_HP,
  114. CODEC_LOOPBACK_AMIC_TO_EXTDAC,
  115. CODEC_LOOPBACK_HEADSET_MIC_TO_EXTDAC,
  116. };
  117. enum mt6391_dac_frequency {
  118. DAC_FREQ_8000 = 0,
  119. DAC_FREQ_11025,
  120. DAC_FREQ_12000,
  121. DAC_FREQ_16000,
  122. DAC_FREQ_22050,
  123. DAC_FREQ_24000,
  124. DAC_FREQ_32000,
  125. DAC_FREQ_44100,
  126. DAC_FREQ_48000,
  127. };
  128. enum mt6391_adc_frequency {
  129. ADC_FREQ_8000 = 0,
  130. ADC_FREQ_16000,
  131. ADC_FREQ_32000,
  132. ADC_FREQ_48000,
  133. };
  134. enum mt6391_soc_enum_type {
  135. ENUM_AUDIO_AMP = 0,
  136. ENUM_VOICE_AMP,
  137. ENUM_SPK_AMP,
  138. ENUM_HS_SPK_AMP,
  139. ENUM_HEADSETL_GAIN,
  140. ENUM_HEADSETR_GAIN,
  141. ENUM_HANDSET_GAIN,
  142. ENUM_SPKL_GAIN,
  143. ENUM_SPKR_GAIN,
  144. ENUM_SPK_SEL,
  145. ENUM_SPK_OC_FLAG,
  146. ENUM_DAC_SCK,
  147. ENUM_DMIC_SWITCH,
  148. ENUM_ADC1_SWITCH,
  149. ENUM_ADC2_SWITCH,
  150. ENUM_PREAMP1_MUX,
  151. ENUM_PREAMP2_MUX,
  152. ENUM_PREAMP1_GAIN,
  153. ENUM_PREAMP2_GAIN,
  154. ENUM_LOOPBACK_SEL,
  155. ENUM_DAC_SGEN,
  156. ENUM_ADC_SGEN,
  157. ENUM_DAC_FREQ,
  158. ENUM_ADC_FREQ,
  159. };
  160. /* codec private data */
  161. struct mt6391_priv {
  162. int device_volume[MT6391_VOL_TYPE_MAX];
  163. int device_mux[MT6391_MUX_MAX_TYPE];
  164. bool device_power[MT6391_DEV_MAX];
  165. uint32_t sample_rate[MT6391_ADDA_MAX];
  166. uint32_t speaker_channel_sel;
  167. uint32_t speaker_mode;
  168. uint32_t adc_warmup_time_us;
  169. uint32_t dmic_warmup_time_us;
  170. uint8_t hpl_trim;
  171. uint8_t hpl_fine_trim;
  172. uint8_t hpr_trim;
  173. uint8_t hpr_fine_trim;
  174. uint8_t iv_hpl_trim;
  175. uint8_t iv_hpl_fine_trim;
  176. uint8_t iv_hpr_trim;
  177. uint8_t iv_hpr_fine_trim;
  178. uint8_t spkl_polarity;
  179. uint8_t ispkl_trim;
  180. uint8_t spkr_polarity;
  181. uint8_t ispkr_trim;
  182. uint32_t codec_loopback_type;
  183. uint32_t dac_sgen_switch;
  184. uint32_t adc_sgen_switch;
  185. int ana_clk_counter;
  186. struct mutex ctrl_mutex;
  187. struct mutex clk_mutex;
  188. struct snd_soc_codec *codec;
  189. #ifdef CONFIG_DEBUG_FS
  190. struct dentry *debugfs;
  191. #endif
  192. };
  193. /* Function implementation */
  194. static uint32_t mt6391_get_reg(struct mt6391_priv *codec_data, uint32_t offset)
  195. {
  196. uint32_t data = 0;
  197. #if defined(USE_MT6397_REGMAP)
  198. data = snd_soc_read(codec_data->codec, offset);
  199. #elif defined(USE_PMIC_WRAP_DRIVER)
  200. pwrap_read(offset, &data);
  201. #endif
  202. return data;
  203. }
  204. static void mt6391_set_reg(struct mt6391_priv *codec_data, uint32_t offset,
  205. uint32_t value, uint32_t mask)
  206. {
  207. #if defined(USE_MT6397_REGMAP)
  208. snd_soc_update_bits(codec_data->codec, offset, mask, value);
  209. #elif defined(USE_PMIC_WRAP_DRIVER)
  210. int ret = 0;
  211. uint32_t reg_value = mt6391_get_reg(codec_data, offset);
  212. reg_value &= (~mask);
  213. reg_value |= (value & mask);
  214. ret = pwrap_write(offset, reg_value);
  215. reg_value = mt6391_get_reg(codec_data, offset);
  216. if ((reg_value & mask) != (value & mask)) {
  217. pr_debug("%s 0x%x-0x%x(0x%x) ret = %d reg_value = 0x%x\n",
  218. __func__, offset, value, mask, ret, reg_value);
  219. }
  220. #endif
  221. }
  222. static void mt6391_control_top_clk(struct mt6391_priv *codec_data,
  223. uint32_t mask, bool enable)
  224. {
  225. /* set pmic register or analog CONTROL_IFACE_PATH */
  226. uint32_t val;
  227. uint32_t reg = enable ? MT6397_TOP_CKPDN_CLR : MT6397_TOP_CKPDN_SET;
  228. #if defined(USE_MT6397_REGMAP)
  229. snd_soc_update_bits(codec_data->codec, reg, mask, mask);
  230. val = snd_soc_read(codec_data->codec, MT6397_TOP_CKPDN);
  231. #elif defined(USE_PMIC_WRAP_DRIVER)
  232. pwrap_write(reg, mask);
  233. pwrap_read(MT6397_TOP_CKPDN, &val);
  234. #endif
  235. if ((val & mask) != (enable ? 0 : mask))
  236. pr_err("%s: data mismatch: mask=%04X, val=%04X, enable=%d\n",
  237. __func__, mask, val, enable);
  238. }
  239. static void mt6391_ana_clk_on(struct mt6391_priv *codec_data)
  240. {
  241. mutex_lock(&codec_data->clk_mutex);
  242. if (codec_data->ana_clk_counter == 0) {
  243. pr_debug("+%s ana_clk_counter:%d\n", __func__, codec_data->ana_clk_counter);
  244. #if defined(USE_MT6397_REGMAP)
  245. mt6391_set_reg(codec_data, MT6397_TOP_CKCON1, 0x0010, 0x0010);
  246. #elif defined(USE_PMIC_WRAP_DRIVER)
  247. upmu_set_rg_clksq_en(1);
  248. #endif
  249. mt6391_control_top_clk(codec_data, 0x0003, true);
  250. }
  251. codec_data->ana_clk_counter++;
  252. mutex_unlock(&codec_data->clk_mutex);
  253. pr_debug("-%s ana_clk_counter:%d\n", __func__, codec_data->ana_clk_counter);
  254. }
  255. static void mt6391_ana_clk_off(struct mt6391_priv *codec_data)
  256. {
  257. mutex_lock(&codec_data->clk_mutex);
  258. codec_data->ana_clk_counter--;
  259. if (codec_data->ana_clk_counter == 0) {
  260. pr_debug("+%s ana_clk_counter:%d\n", __func__, codec_data->ana_clk_counter);
  261. #if defined(USE_MT6397_REGMAP)
  262. mt6391_set_reg(codec_data, MT6397_TOP_CKCON1, 0x0000, 0x0010);
  263. #elif defined(USE_PMIC_WRAP_DRIVER)
  264. upmu_set_rg_clksq_en(0);
  265. #endif
  266. mt6391_control_top_clk(codec_data, 0x0003, false);
  267. } else if (codec_data->ana_clk_counter < 0) {
  268. pr_err("%s ana_clk_counter:%d<0\n", __func__, codec_data->ana_clk_counter);
  269. codec_data->ana_clk_counter = 0;
  270. }
  271. mutex_unlock(&codec_data->clk_mutex);
  272. pr_debug("-%s ana_clk_counter:%d\n", __func__, codec_data->ana_clk_counter);
  273. }
  274. static void mt6391_suspend_clk_on(struct mt6391_priv *codec_data)
  275. {
  276. if (codec_data->ana_clk_counter > 0) {
  277. pr_debug("%s ana_clk_counter:%d\n", __func__, codec_data->ana_clk_counter);
  278. #if defined(USE_MT6397_REGMAP)
  279. mt6391_set_reg(codec_data, MT6397_TOP_CKCON1, 0x0010, 0x0010);
  280. #elif defined(USE_PMIC_WRAP_DRIVER)
  281. upmu_set_rg_clksq_en(1);
  282. #endif
  283. }
  284. }
  285. static void mt6391_suspend_clk_off(struct mt6391_priv *codec_data)
  286. {
  287. if (codec_data->ana_clk_counter > 0) {
  288. pr_debug("%s ana_clk_counter:%d\n", __func__, codec_data->ana_clk_counter);
  289. #if defined(USE_MT6397_REGMAP)
  290. mt6391_set_reg(codec_data, MT6397_TOP_CKCON1, 0x0000, 0x0010);
  291. #elif defined(USE_PMIC_WRAP_DRIVER)
  292. upmu_set_rg_clksq_en(0);
  293. #endif
  294. }
  295. }
  296. static uint32_t mt6391_get_dl_input_mode(unsigned int frequency)
  297. {
  298. uint32_t reg_value = 0;
  299. pr_debug("%s frequency = %d\n", __func__, frequency);
  300. switch (frequency) {
  301. case 8000:
  302. reg_value = 0;
  303. break;
  304. case 11025:
  305. reg_value = 1;
  306. break;
  307. case 12000:
  308. reg_value = 2;
  309. break;
  310. case 16000:
  311. reg_value = 3;
  312. break;
  313. case 22050:
  314. reg_value = 4;
  315. break;
  316. case 24000:
  317. reg_value = 5;
  318. break;
  319. case 32000:
  320. reg_value = 6;
  321. break;
  322. case 44100:
  323. reg_value = 7;
  324. break;
  325. case 48000:
  326. reg_value = 8;
  327. break;
  328. default:
  329. pr_warn("%s unexpected frequency = %d\n", __func__, frequency);
  330. break;
  331. }
  332. return reg_value;
  333. }
  334. uint32_t mt6391_get_ul_voice_mode(uint32_t frequency)
  335. {
  336. uint32_t reg_value = 0;
  337. pr_debug("%s frequency = %d\n", __func__, frequency);
  338. switch (frequency) {
  339. case 8000:
  340. reg_value = 0x0 << 1;
  341. break;
  342. case 16000:
  343. reg_value = 0x5 << 1;
  344. break;
  345. case 32000:
  346. reg_value = 0xa << 1;
  347. break;
  348. case 48000:
  349. reg_value = 0xf << 1;
  350. break;
  351. default:
  352. pr_warn("%s unsupported frequency = %d\n", __func__, frequency);
  353. }
  354. pr_debug("%s reg_value = %d\n", __func__, reg_value);
  355. return reg_value;
  356. }
  357. static bool mt6391_get_dl_status(struct mt6391_priv *codec_data)
  358. {
  359. int i = 0;
  360. for (i = 0; i < MT6391_DEV_OUT_MAX; i++) {
  361. if (codec_data->device_power[i])
  362. return true;
  363. }
  364. return false;
  365. }
  366. static bool mt6391_get_ul_status(struct mt6391_priv *codec_data)
  367. {
  368. int i = 0;
  369. for (i = MT6391_DEV_IN_ADC1; i < MT6391_DEV_IN_MAX; i++) {
  370. if (codec_data->device_power[i])
  371. return true;
  372. }
  373. return false;
  374. }
  375. static bool mt6391_get_adc_status(struct mt6391_priv *codec_data)
  376. {
  377. int i = 0;
  378. for (i = MT6391_DEV_IN_ADC1; i < MT6391_DEV_ADC_MAX; i++) {
  379. if (codec_data->device_power[i])
  380. return true;
  381. }
  382. return false;
  383. }
  384. static void mt6391_set_mux(struct mt6391_priv *codec_data,
  385. enum mt6391_device_type device_type, enum mt6391_device_mux mux_type)
  386. {
  387. uint32_t reg_value = 0;
  388. switch (device_type) {
  389. case MT6391_DEV_OUT_EARPIECEL:
  390. case MT6391_DEV_OUT_EARPIECER:
  391. if (mux_type == MT6391_MUX_OPEN) {
  392. reg_value = 0;
  393. } else if (mux_type == MT6391_MUX_MUTE) {
  394. reg_value = 1 << 3;
  395. } else if (mux_type == MT6391_MUX_VOICE) {
  396. reg_value = 2 << 3;
  397. } else {
  398. reg_value = 2 << 3;
  399. pr_warn("%s %d %d\n", __func__, device_type, mux_type);
  400. }
  401. mt6391_set_reg(codec_data, MT6397_AUDBUF_CFG0, reg_value, 0x000000018);
  402. break;
  403. case MT6391_DEV_OUT_HEADSETL:
  404. if (mux_type == MT6391_MUX_OPEN) {
  405. reg_value = 0;
  406. } else if (mux_type == MT6391_MUX_LINEIN_L) {
  407. reg_value = 1 << 5;
  408. } else if (mux_type == MT6391_MUX_LINEIN_R) {
  409. reg_value = 2 << 5;
  410. } else if (mux_type == MT6391_MUX_LINEIN_STEREO) {
  411. reg_value = 3 << 5;
  412. } else if (mux_type == MT6391_MUX_AUDIO) {
  413. reg_value = 4 << 5;
  414. } else if (mux_type == MT6391_MUX_LINEIN_AUDIO_MONO) {
  415. reg_value = 5 << 5;
  416. } else if (mux_type == MT6391_MUX_IV_BUFFER) {
  417. reg_value = 8 << 5;
  418. } else {
  419. reg_value = 4 << 5;
  420. pr_warn("%s %d %d\n", __func__, device_type, mux_type);
  421. }
  422. mt6391_set_reg(codec_data, MT6397_AUDBUF_CFG0, reg_value, 0x000001e0);
  423. break;
  424. case MT6391_DEV_OUT_HEADSETR:
  425. if (mux_type == MT6391_MUX_OPEN) {
  426. reg_value = 0;
  427. } else if (mux_type == MT6391_MUX_LINEIN_L) {
  428. reg_value = 1 << 9;
  429. } else if (mux_type == MT6391_MUX_LINEIN_R) {
  430. reg_value = 2 << 9;
  431. } else if (mux_type == MT6391_MUX_LINEIN_STEREO) {
  432. reg_value = 3 << 9;
  433. } else if (mux_type == MT6391_MUX_AUDIO) {
  434. reg_value = 4 << 9;
  435. } else if (mux_type == MT6391_MUX_LINEIN_AUDIO_MONO) {
  436. reg_value = 5 << 9;
  437. } else if (mux_type == MT6391_MUX_IV_BUFFER) {
  438. reg_value = 8 << 9;
  439. } else {
  440. reg_value = 4 << 9;
  441. pr_warn("%s %d %d\n", __func__, device_type, mux_type);
  442. }
  443. mt6391_set_reg(codec_data, MT6397_AUDBUF_CFG0, reg_value, 0x00001e00);
  444. break;
  445. case MT6391_DEV_OUT_SPEAKERR:
  446. case MT6391_DEV_OUT_SPEAKERL:
  447. case MT6391_DEV_OUT_SPEAKER_HEADSET_R:
  448. case MT6391_DEV_OUT_SPEAKER_HEADSET_L:
  449. if (mux_type == MT6391_MUX_OPEN) {
  450. reg_value = 0;
  451. } else if ((mux_type == MT6391_MUX_LINEIN_L)
  452. || (mux_type == MT6391_MUX_LINEIN_R)) {
  453. reg_value = 1 << 2;
  454. } else if (mux_type == MT6391_MUX_LINEIN_STEREO) {
  455. reg_value = 2 << 2;
  456. } else if (mux_type == MT6391_MUX_OPEN) {
  457. reg_value = 3 << 2;
  458. } else if (mux_type == MT6391_MUX_AUDIO) {
  459. reg_value = 4 << 2;
  460. } else if (mux_type == MT6391_MUX_LINEIN_AUDIO_MONO) {
  461. reg_value = 5 << 2;
  462. } else if (mux_type == MT6391_MUX_LINEIN_AUDIO_STEREO) {
  463. reg_value = 6 << 2;
  464. } else {
  465. reg_value = 4 << 2;
  466. pr_warn("%s %d %d\n", __func__, device_type, mux_type);
  467. }
  468. mt6391_set_reg(codec_data, MT6397_AUD_IV_CFG0,
  469. reg_value | (reg_value << 8), 0x00001c1c);
  470. break;
  471. case MT6391_DEV_IN_PREAMP_L:
  472. if (mux_type == MT6391_MUX_IN_MIC1) {
  473. reg_value = 1 << 2;
  474. } else if (mux_type == MT6391_MUX_IN_MIC2) {
  475. reg_value = 2 << 2;
  476. } else if (mux_type == MT6391_MUX_IN_MIC3) {
  477. reg_value = 3 << 2;
  478. } else {
  479. reg_value = 1 << 2;
  480. pr_warn("%s %d %d\n", __func__, device_type, mux_type);
  481. }
  482. mt6391_set_reg(codec_data, MT6397_AUDPREAMP_CON0, reg_value, 0x0000001c);
  483. break;
  484. case MT6391_DEV_IN_PREAMP_R:
  485. if (mux_type == MT6391_MUX_IN_MIC1) {
  486. reg_value = 1 << 5;
  487. } else if (mux_type == MT6391_MUX_IN_MIC2) {
  488. reg_value = 2 << 5;
  489. } else if (mux_type == MT6391_MUX_IN_MIC3) {
  490. reg_value = 3 << 5;
  491. } else {
  492. reg_value = 1 << 5;
  493. pr_warn("%s %d %d\n", __func__, device_type, mux_type);
  494. }
  495. mt6391_set_reg(codec_data, MT6397_AUDPREAMP_CON0, reg_value, 0x000000e0);
  496. break;
  497. case MT6391_DEV_IN_ADC1:
  498. if (mux_type == MT6391_MUX_IN_MIC1) {
  499. reg_value = 1 << 2;
  500. } else if (mux_type == MT6391_MUX_IN_PREAMP_1) {
  501. reg_value = 4 << 2;
  502. } else if (mux_type == MT6391_MUX_IN_LEVEL_SHIFT_BUFFER) {
  503. reg_value = 5 << 2;
  504. } else {
  505. reg_value = 1 << 2;
  506. pr_warn("%s %d %d\n", __func__, device_type, mux_type);
  507. }
  508. mt6391_set_reg(codec_data, MT6397_AUDADC_CON0, reg_value, 0x0000001c);
  509. break;
  510. case MT6391_DEV_IN_ADC2:
  511. if (mux_type == MT6391_MUX_IN_MIC1) {
  512. reg_value = 1 << 5;
  513. } else if (mux_type == MT6391_MUX_IN_PREAMP_2) {
  514. reg_value = 4 << 5;
  515. } else if (mux_type == MT6391_MUX_IN_LEVEL_SHIFT_BUFFER) {
  516. reg_value = 5 << 5;
  517. } else {
  518. reg_value = 1 << 5;
  519. pr_warn("%s %d %d\n", __func__, device_type, mux_type);
  520. }
  521. mt6391_set_reg(codec_data, MT6397_AUDADC_CON0, reg_value, 0x000000e0);
  522. break;
  523. default:
  524. break;
  525. }
  526. }
  527. static void mt6391_turn_on_dac(struct mt6391_priv *codec_data)
  528. {
  529. uint32_t rate = codec_data->sample_rate[MT6391_ADDA_DAC];
  530. pr_debug("%s dac_sample_rate = %d\n", __func__, rate);
  531. mt6391_set_reg(codec_data, MT6397_AFE_PMIC_NEWIF_CFG0,
  532. (mt6391_get_dl_input_mode(rate) << 12),
  533. 0xf000);
  534. mt6391_set_reg(codec_data, MT6397_AFUNC_AUD_CON2, 0x0006, 0xffff);
  535. mt6391_set_reg(codec_data, MT6397_AFUNC_AUD_CON0, 0xc3a1, 0xffff);
  536. mt6391_set_reg(codec_data, MT6397_AFUNC_AUD_CON2, 0x0003, 0xffff);
  537. mt6391_set_reg(codec_data, MT6397_AFUNC_AUD_CON2, 0x000b, 0xffff);
  538. mt6391_set_reg(codec_data, MT6397_AFE_DL_SDM_CON1, 0x001e, 0xffff);
  539. mt6391_set_reg(codec_data, MT6397_AFE_DL_SRC2_CON0_H,
  540. 0x0300 | (mt6391_get_dl_input_mode(rate) << 12),
  541. 0x0ffff);
  542. mt6391_set_reg(codec_data, MT6397_AFE_UL_DL_CON0, 0x007f, 0xffff);
  543. mt6391_set_reg(codec_data, MT6397_AFE_DL_SRC2_CON0_L, 0x1801, 0xffff);
  544. }
  545. static void mt6391_turn_off_dac(struct mt6391_priv *codec_data)
  546. {
  547. pr_debug("%s\n", __func__);
  548. mt6391_set_reg(codec_data, MT6397_AFE_DL_SRC2_CON0_L, 0x1800, 0xffff);
  549. if (!mt6391_get_ul_status(codec_data))
  550. mt6391_set_reg(codec_data, MT6397_AFE_UL_DL_CON0, 0x0000, 0xffff);
  551. }
  552. static void mt6391_spk_auto_trim_offset(struct mt6391_priv *codec_data)
  553. {
  554. uint32_t wait_for_ready = 0;
  555. uint32_t reg = 0;
  556. uint32_t chip_version = 0;
  557. int retry_count = 50;
  558. mt6391_set_reg(codec_data, MT6397_AFUNC_AUD_CON2, 0x0080, 0x0080);
  559. /* enable VA28 , VA 33 VBAT ref , set dc */
  560. mt6391_set_reg(codec_data, MT6397_AUDLDO_CFG0, 0x0D92, 0xffff);
  561. /* set ACC mode enable NVREF */
  562. mt6391_set_reg(codec_data, MT6397_AUDNVREGGLB_CFG0, 0x000C, 0xffff);
  563. /* enable LDO ; fix me , separate for UL DL LDO */
  564. mt6391_set_reg(codec_data, MT6397_AUD_NCP0, 0xE000, 0xE000);
  565. mt6391_set_reg(codec_data, MT6397_NCP_CLKDIV_CON0, 0x102B, 0xffff); /* RG DEV ck on */
  566. mt6391_set_reg(codec_data, MT6397_NCP_CLKDIV_CON1, 0x0000, 0xffff); /* NCP on */
  567. udelay(200);
  568. /* ZCD setting gain step gain and enable */
  569. mt6391_set_reg(codec_data, MT6397_ZCD_CON0, 0x0301, 0xffff);
  570. /* audio bias adjustment */
  571. mt6391_set_reg(codec_data, MT6397_IBIASDIST_CFG0, 0x0552, 0xffff);
  572. /* set DUDIV gain ,iv buffer gain */
  573. mt6391_set_reg(codec_data, MT6397_ZCD_CON4, 0x0505, 0xffff);
  574. mt6391_set_reg(codec_data, MT6397_AUD_IV_CFG0, 0x1111, 0xffff); /* set IV buffer on */
  575. udelay(100);
  576. mt6391_set_reg(codec_data, MT6397_AUDCLKGEN_CFG0, 0x0001, 0x0001); /* reset docoder */
  577. mt6391_set_reg(codec_data, MT6397_AUDDAC_CON0, 0x000f, 0xffff); /* power on DAC */
  578. udelay(100);
  579. mt6391_set_mux(codec_data, MT6391_DEV_OUT_SPEAKERR, MT6391_MUX_AUDIO);
  580. mt6391_set_mux(codec_data, MT6391_DEV_OUT_SPEAKERL, MT6391_MUX_AUDIO);
  581. mt6391_set_reg(codec_data, MT6397_AUDBUF_CFG0, 0x0000, 0x0007); /* set Mux */
  582. mt6391_set_reg(codec_data, MT6397_AFUNC_AUD_CON2, 0x0000, 0x0080);
  583. /* disable the software register mode */
  584. mt6391_set_reg(codec_data, MT6397_SPK_CON1, 0, 0x7f00);
  585. /* disable the software register mode */
  586. mt6391_set_reg(codec_data, MT6397_SPK_CON4, 0, 0x7f00);
  587. /* Choose new mode for trim (E2 Trim) */
  588. mt6391_set_reg(codec_data, MT6397_SPK_CON9, 0x0018, 0xffff);
  589. mt6391_set_reg(codec_data, MT6397_SPK_CON0, 0x0008, 0xffff); /* Enable auto trim */
  590. mt6391_set_reg(codec_data, MT6397_SPK_CON3, 0x0008, 0xffff); /* Enable auto trim R */
  591. mt6391_set_reg(codec_data, MT6397_SPK_CON0, 0x3000, 0xf000); /* set gain */
  592. mt6391_set_reg(codec_data, MT6397_SPK_CON3, 0x3000, 0xf000); /* set gain R */
  593. mt6391_set_reg(codec_data, MT6397_SPK_CON9, 0x0100, 0x0f00); /* set gain L */
  594. mt6391_set_reg(codec_data, MT6397_SPK_CON5, (0x1 << 11), 0x7800); /* set gain R */
  595. /* Enable amplifier & auto trim */
  596. mt6391_set_reg(codec_data, MT6397_SPK_CON0, 0x0001, 0x0001);
  597. /* Enable amplifier & auto trim R */
  598. mt6391_set_reg(codec_data, MT6397_SPK_CON3, 0x0001, 0x0001);
  599. /* empirical data shows it usually takes 13ms to be ready */
  600. usleep_range(15000, 16000);
  601. do {
  602. wait_for_ready = mt6391_get_reg(codec_data, MT6397_SPK_CON1);
  603. wait_for_ready = ((wait_for_ready & 0x8000) >> 15);
  604. if (wait_for_ready) {
  605. wait_for_ready = mt6391_get_reg(codec_data, MT6397_SPK_CON4);
  606. wait_for_ready = ((wait_for_ready & 0x8000) >> 15);
  607. if (wait_for_ready)
  608. break;
  609. }
  610. pr_debug("%s sleep\n", __func__);
  611. udelay(100);
  612. } while (retry_count--);
  613. if (likely(wait_for_ready))
  614. pr_notice("%s done retry_count = %d\n", __func__, retry_count);
  615. else
  616. pr_warn("%s fail\n", __func__);
  617. mt6391_set_reg(codec_data, MT6397_SPK_CON9, 0x0, 0xffff);
  618. mt6391_set_reg(codec_data, MT6397_SPK_CON5, 0, 0x7800); /* set gain R */
  619. mt6391_set_reg(codec_data, MT6397_SPK_CON0, 0x0000, 0x0001);
  620. mt6391_set_reg(codec_data, MT6397_SPK_CON3, 0x0000, 0x0001);
  621. /* get trim offset result */
  622. pr_debug("%s GetSPKAutoTrimOffset\n", __func__);
  623. mt6391_set_reg(codec_data, MT6397_TEST_CON0, 0x0805, 0xffff);
  624. reg = mt6391_get_reg(codec_data, MT6397_TEST_OUT_L);
  625. codec_data->ispkl_trim = ((reg >> 0) & 0xf);
  626. mt6391_set_reg(codec_data, MT6397_TEST_CON0, 0x0806, 0xffff);
  627. reg = mt6391_get_reg(codec_data, MT6397_TEST_OUT_L);
  628. codec_data->ispkl_trim |= (((reg >> 0) & 0x1) << 4);
  629. codec_data->spkl_polarity = ((reg >> 1) & 0x1);
  630. mt6391_set_reg(codec_data, MT6397_TEST_CON0, 0x080E, 0xffff);
  631. reg = mt6391_get_reg(codec_data, MT6397_TEST_OUT_L);
  632. codec_data->ispkr_trim = ((reg >> 0) & 0xf);
  633. mt6391_set_reg(codec_data, MT6397_TEST_CON0, 0x080F, 0xffff);
  634. reg = mt6391_get_reg(codec_data, MT6397_TEST_OUT_L);
  635. codec_data->ispkr_trim |= (((reg >> 0) & 0x1) << 4);
  636. codec_data->spkr_polarity = ((reg >> 1) & 0x1);
  637. #if defined(USE_MT6397_REGMAP)
  638. chip_version = mt6391_get_reg(codec_data, MT6397_CID);
  639. #elif defined(USE_PMIC_WRAP_DRIVER)
  640. chip_version = upmu_get_cid();
  641. #endif
  642. if (chip_version == PMIC6397_E1_CID_CODE) {
  643. pr_debug("%s PMIC is MT6397 E1, set speaker R trim code to 0\n", __func__);
  644. codec_data->ispkr_trim = 0;
  645. codec_data->spkr_polarity = 0;
  646. }
  647. pr_debug("%s spkl_polarity = %d ispkl_trim = 0x%x\n",
  648. __func__, codec_data->spkl_polarity, codec_data->ispkl_trim);
  649. pr_debug("%s spkr_polarity = %d ispkr_trim = 0x%x\n",
  650. __func__, codec_data->spkr_polarity, codec_data->ispkr_trim);
  651. /* turn off speaker after trim */
  652. mt6391_set_reg(codec_data, MT6397_AFUNC_AUD_CON2, 0x0080, 0x0080);
  653. mt6391_set_reg(codec_data, MT6397_SPK_CON0, 0x0000, 0xffff);
  654. mt6391_set_reg(codec_data, MT6397_SPK_CON3, 0x0000, 0xffff);
  655. mt6391_set_reg(codec_data, MT6397_SPK_CON11, 0x0000, 0xffff);
  656. mt6391_set_reg(codec_data, MT6397_ZCD_CON0, 0x0101, 0xffff);
  657. /* enable LDO ; fix me , separate for UL DL LDO */
  658. mt6391_set_reg(codec_data, MT6397_AUDCLKGEN_CFG0, 0x0000, 0x0001);
  659. mt6391_set_reg(codec_data, MT6397_AUDDAC_CON0, 0x0000, 0xffff); /* RG DEV ck on */
  660. mt6391_set_reg(codec_data, MT6397_AUD_IV_CFG0, 0x0000, 0xffff); /* NCP on */
  661. /* Audio headset power on */
  662. mt6391_set_reg(codec_data, MT6397_IBIASDIST_CFG0, 0x1552, 0xffff);
  663. /* mt6391_set_reg(codec_data, MT6397_AUDBUF_CFG1, 0x0000, 0x0100); */
  664. mt6391_set_reg(codec_data, MT6397_AUDNVREGGLB_CFG0, 0x0006, 0xffff);
  665. mt6391_set_reg(codec_data, MT6397_NCP_CLKDIV_CON1, 0x0001, 0xffff); /* fix me */
  666. mt6391_set_reg(codec_data, MT6397_AUD_NCP0, 0x0000, 0x6000);
  667. mt6391_set_reg(codec_data, MT6397_AUDLDO_CFG0, 0x0192, 0xffff);
  668. mt6391_set_reg(codec_data, MT6397_AFUNC_AUD_CON2, 0x0000, 0x0080);
  669. }
  670. static void mt6391_get_hp_trim_offset(struct mt6391_priv *codec_data)
  671. {
  672. uint32_t reg1 = 0, reg2 = 0;
  673. bool trim_enable = 0;
  674. /* get to check if trim happen */
  675. reg1 = mt6391_get_reg(codec_data, MT6397_TRIM_ADDRESS1);
  676. reg2 = mt6391_get_reg(codec_data, MT6397_TRIM_ADDRESS2);
  677. pr_debug("%s reg1 = 0x%x reg2 = 0x%x\n", __func__, reg1, reg2);
  678. trim_enable = (reg1 >> 11) & 1;
  679. if (trim_enable == 0) {
  680. codec_data->hpl_trim = 2;
  681. codec_data->hpl_fine_trim = 0;
  682. codec_data->hpr_trim = 2;
  683. codec_data->hpr_fine_trim = 0;
  684. codec_data->iv_hpl_trim = 3;
  685. codec_data->iv_hpl_fine_trim = 0;
  686. codec_data->iv_hpr_trim = 3;
  687. codec_data->iv_hpr_fine_trim = 0;
  688. } else {
  689. codec_data->hpl_trim = ((reg1 >> 3) & 0xf);
  690. codec_data->hpr_trim = ((reg1 >> 7) & 0xf);
  691. codec_data->hpl_fine_trim = ((reg1 >> 12) & 0x3);
  692. codec_data->hpr_fine_trim = ((reg1 >> 14) & 0x3);
  693. codec_data->iv_hpl_trim = ((reg2 >> 0) & 0xf);
  694. codec_data->iv_hpr_trim = ((reg2 >> 4) & 0xf);
  695. codec_data->iv_hpl_fine_trim = ((reg2 >> 8) & 0x3);
  696. codec_data->iv_hpr_fine_trim = ((reg2 >> 10) & 0x3);
  697. }
  698. pr_debug("%s trim_enable = %d reg1 = 0x%x reg2 = 0x%x\n", __func__, trim_enable, reg1,
  699. reg2);
  700. pr_debug("%s hpl_trim = 0x%x hpl_fine_trim = 0x%x hpr_trim = 0x%x hpr_fine_trim = 0x%x\n",
  701. __func__, codec_data->hpl_trim, codec_data->hpl_fine_trim, codec_data->hpr_trim,
  702. codec_data->hpr_fine_trim);
  703. pr_debug("%s iv_hpl_trim = 0x%x iv_hpl_fine_trim = 0x%x\n", __func__,
  704. codec_data->iv_hpl_trim, codec_data->iv_hpl_fine_trim);
  705. pr_debug("%s iv_hpr_trim = 0x%x iv_hpr_fine_trim = 0x%x\n", __func__,
  706. codec_data->iv_hpr_trim, codec_data->iv_hpr_fine_trim);
  707. }
  708. static void mt6391_set_hp_trim_offset(struct mt6391_priv *codec_data)
  709. {
  710. uint32_t reg_value = 0;
  711. pr_debug("%s", __func__);
  712. reg_value |= 1 << 8; /* enable trim function */
  713. reg_value |= codec_data->hpr_fine_trim << 11;
  714. reg_value |= codec_data->hpl_fine_trim << 9;
  715. reg_value |= codec_data->hpr_trim << 4;
  716. reg_value |= codec_data->hpl_trim;
  717. mt6391_set_reg(codec_data, MT6397_AUDBUF_CFG3, reg_value, 0x1fff);
  718. }
  719. static void mt6391_set_spk_trim_offset(struct mt6391_priv *codec_data)
  720. {
  721. uint32_t reg_value = 0;
  722. reg_value |= 1 << 14; /* enable trim function */
  723. reg_value |= codec_data->spkl_polarity << 13; /* polarity */
  724. reg_value |= codec_data->ispkl_trim << 8; /* polarity */
  725. pr_debug("%s reg_value = 0x%x\n", __func__, reg_value);
  726. mt6391_set_reg(codec_data, MT6397_SPK_CON1, reg_value, 0x7f00);
  727. reg_value = 0;
  728. reg_value |= 1 << 14; /* enable trim function */
  729. reg_value |= codec_data->spkr_polarity << 13; /* polarity */
  730. reg_value |= codec_data->ispkr_trim << 8; /* polarity */
  731. pr_debug("%s reg_value = 0x%x\n", __func__, reg_value);
  732. mt6391_set_reg(codec_data, MT6397_SPK_CON4, reg_value, 0x7f00);
  733. }
  734. static void mt6391_set_iv_hp_trim_offset(struct mt6391_priv *codec_data)
  735. {
  736. uint32_t reg_value = 0;
  737. reg_value |= 1 << 8; /* enable trim function */
  738. if ((codec_data->hpr_fine_trim == 0) || (codec_data->hpl_fine_trim == 0))
  739. codec_data->iv_hpr_fine_trim = 0;
  740. else
  741. codec_data->iv_hpr_fine_trim = 2;
  742. reg_value |= codec_data->iv_hpr_fine_trim << 11;
  743. if ((codec_data->hpr_fine_trim == 0) || (codec_data->hpl_fine_trim == 0))
  744. codec_data->iv_hpl_fine_trim = 0;
  745. else
  746. codec_data->iv_hpl_fine_trim = 2;
  747. reg_value |= codec_data->iv_hpl_fine_trim << 9;
  748. reg_value |= codec_data->iv_hpr_trim << 4;
  749. reg_value |= codec_data->iv_hpl_trim;
  750. mt6391_set_reg(codec_data, MT6397_AUDBUF_CFG3, reg_value, 0x1fff);
  751. }
  752. static void mt6391_turn_on_headphone_amp(struct mt6391_priv *codec_data)
  753. {
  754. pr_debug("%s\n", __func__);
  755. if (codec_data->device_power[MT6391_DEV_OUT_HEADSETL]) {
  756. pr_info("%s turn on already\n", __func__);
  757. return;
  758. }
  759. if (!mt6391_get_dl_status(codec_data))
  760. mt6391_turn_on_dac(codec_data);
  761. mt6391_set_reg(codec_data, MT6397_AFUNC_AUD_CON2, 0x0080, 0x0080);
  762. mt6391_set_hp_trim_offset(codec_data);
  763. /* enable VA28 , VA 33 VBAT ref , set dc */
  764. mt6391_set_reg(codec_data, MT6397_AUDLDO_CFG0, 0x0D92, 0xffff);
  765. /* set ACC mode enable NVREF */
  766. mt6391_set_reg(codec_data, MT6397_AUDNVREGGLB_CFG0, 0x000C, 0xffff);
  767. /* enable LDO ; fix me , separate for UL DL LDO */
  768. mt6391_set_reg(codec_data, MT6397_AUD_NCP0, 0xE000, 0xE000);
  769. /* RG DEV ck on */
  770. mt6391_set_reg(codec_data, MT6397_NCP_CLKDIV_CON0, 0x102b, 0xffff);
  771. /* NCP on */
  772. mt6391_set_reg(codec_data, MT6397_NCP_CLKDIV_CON1, 0x0000, 0xffff);
  773. udelay(200);
  774. mt6391_set_reg(codec_data, MT6397_ZCD_CON0, 0x0101, 0xffff);
  775. mt6391_set_reg(codec_data, MT6397_AUDACCDEPOP_CFG0, 0x0030, 0xffff);
  776. mt6391_set_reg(codec_data, MT6397_AUDBUF_CFG0, 0x0008, 0xffff);
  777. mt6391_set_reg(codec_data, MT6397_IBIASDIST_CFG0, 0x0552, 0xffff);
  778. mt6391_set_reg(codec_data, MT6397_ZCD_CON2, 0x0c0c, 0xffff);
  779. mt6391_set_reg(codec_data, MT6397_ZCD_CON3, 0x000F, 0xffff);
  780. mt6391_set_reg(codec_data, MT6397_AUDBUF_CFG1, 0x0900, 0xffff);
  781. mt6391_set_reg(codec_data, MT6397_AUDBUF_CFG2, 0x0082, 0xffff);
  782. mt6391_set_reg(codec_data, MT6397_AUDBUF_CFG0, 0x0009, 0xffff);
  783. mt6391_set_reg(codec_data, MT6397_AUDBUF_CFG1, 0x0940, 0xffff);
  784. udelay(200);
  785. mt6391_set_reg(codec_data, MT6397_AUDBUF_CFG0, 0x000F, 0xffff);
  786. mt6391_set_reg(codec_data, MT6397_AUDBUF_CFG1, 0x0100, 0xffff);
  787. udelay(100);
  788. mt6391_set_reg(codec_data, MT6397_AUDBUF_CFG2, 0x0022, 0xffff);
  789. mt6391_set_reg(codec_data, MT6397_ZCD_CON2, 0x00c0c, 0xffff);
  790. udelay(100);
  791. mt6391_set_reg(codec_data, MT6397_AUDCLKGEN_CFG0, 0x0001, 0x0001);
  792. mt6391_set_reg(codec_data, MT6397_AUDDAC_CON0, 0x000F, 0xffff);
  793. udelay(100);
  794. mt6391_set_reg(codec_data, MT6397_AUDBUF_CFG0, 0x0006, 0x0007);
  795. mt6391_set_mux(codec_data, MT6391_DEV_OUT_HEADSETR, MT6391_MUX_AUDIO);
  796. mt6391_set_mux(codec_data, MT6391_DEV_OUT_HEADSETL, MT6391_MUX_AUDIO);
  797. mt6391_set_reg(codec_data, MT6397_AFUNC_AUD_CON2, 0x0000, 0x0080);
  798. pr_debug("%s done\n", __func__);
  799. }
  800. static void mt6391_turn_off_headphone_amp(struct mt6391_priv *codec_data)
  801. {
  802. pr_debug("%s\n", __func__);
  803. if (codec_data->device_power[MT6391_DEV_OUT_HEADSETL]) {
  804. pr_info("%s still on\n", __func__);
  805. return;
  806. }
  807. mt6391_set_reg(codec_data, MT6397_AFUNC_AUD_CON2, 0x0080, 0x0080);
  808. mt6391_set_reg(codec_data, MT6397_ZCD_CON2, 0x0c0c, 0xffff);
  809. mt6391_set_reg(codec_data, MT6397_AUDBUF_CFG0, 0x0000, 0x1fe7);
  810. mt6391_set_reg(codec_data, MT6397_IBIASDIST_CFG0, 0x1552, 0xffff); /* RG DEV ck off; */
  811. mt6391_set_reg(codec_data, MT6397_AUDDAC_CON0, 0x0000, 0xffff); /* NCP off */
  812. mt6391_set_reg(codec_data, MT6397_AUDCLKGEN_CFG0, 0x0000, 0x0001);
  813. if (mt6391_get_ul_status(codec_data) == false)
  814. mt6391_set_reg(codec_data, MT6397_AUDNVREGGLB_CFG0, 0x0006, 0xffff);
  815. mt6391_set_reg(codec_data, MT6397_NCP_CLKDIV_CON1, 0x0001, 0xffff);
  816. mt6391_set_reg(codec_data, MT6397_AUD_NCP0, 0x0000, 0x6000);
  817. if (mt6391_get_ul_status(codec_data) == false)
  818. mt6391_set_reg(codec_data, MT6397_AUDLDO_CFG0, 0x0192, 0xffff);
  819. mt6391_set_reg(codec_data, MT6397_AFUNC_AUD_CON2, 0x0000, 0x0080);
  820. if (mt6391_get_dl_status(codec_data) == false)
  821. mt6391_turn_off_dac(codec_data);
  822. pr_debug("%s done\n", __func__);
  823. }
  824. static void mt6391_turn_on_voice_amp(struct mt6391_priv *codec_data)
  825. {
  826. if (codec_data->device_power[MT6391_DEV_OUT_EARPIECEL]) {
  827. pr_info("%s turn on already\n", __func__);
  828. return;
  829. }
  830. if (!mt6391_get_dl_status(codec_data))
  831. mt6391_turn_on_dac(codec_data);
  832. mt6391_set_reg(codec_data, MT6397_AFUNC_AUD_CON2, 0x0080, 0x0080);
  833. /* enable VA28 , VA 33 VBAT ref , set dc */
  834. mt6391_set_reg(codec_data, MT6397_AUDLDO_CFG0, 0x0D92, 0xffff);
  835. /* set ACC mode enable NVREF */
  836. mt6391_set_reg(codec_data, MT6397_AUDNVREGGLB_CFG0, 0x000C, 0xffff);
  837. /* enable LDO ; separate for UL DL LDO */
  838. mt6391_set_reg(codec_data, MT6397_AUD_NCP0, 0xE000, 0xE000);
  839. mt6391_set_reg(codec_data, MT6397_NCP_CLKDIV_CON0, 0x102B, 0xffff); /* RG DEV ck on */
  840. mt6391_set_reg(codec_data, MT6397_NCP_CLKDIV_CON1, 0x0000, 0xffff); /* NCP on */
  841. /* usleep(1 * 1000); */
  842. /* ZCD setting gain step gain and enable */
  843. mt6391_set_reg(codec_data, MT6397_ZCD_CON0, 0x0201, 0xffff);
  844. /* select charge current l; fix me */
  845. mt6391_set_reg(codec_data, MT6397_AUDACCDEPOP_CFG0, 0x0030, 0xffff);
  846. /* set voice playback with headset */
  847. mt6391_set_reg(codec_data, MT6397_AUDBUF_CFG0, 0x0008, 0xffff);
  848. /* audio bias adjustment */
  849. mt6391_set_reg(codec_data, MT6397_IBIASDIST_CFG0, 0x0552, 0xffff);
  850. /* handset gain , minimun gain */
  851. mt6391_set_reg(codec_data, MT6397_ZCD_CON3, 0x000F, 0xffff);
  852. /* short HS to vcm and HS output stability enhance */
  853. mt6391_set_reg(codec_data, MT6397_AUDBUF_CFG2, 0x00A2, 0xffff);
  854. /* handset gain , minimun gain */
  855. mt6391_set_reg(codec_data, MT6397_AUDBUF_CFG0, 0x0001, 0xffff);
  856. /* short HS to vcm and HS output stability enhance */
  857. mt6391_set_reg(codec_data, MT6397_AUDBUF_CFG2, 0x0022, 0xffff);
  858. /* handset gain , normal gain */
  859. mt6391_set_reg(codec_data, MT6397_ZCD_CON3, 0x0002, 0xffff);
  860. mt6391_set_reg(codec_data, MT6397_AUDCLKGEN_CFG0, 0x0001, 0x0001); /* reset decoder */
  861. /* power on audio DAC right channels */
  862. mt6391_set_reg(codec_data, MT6397_AUDDAC_CON0, 0x0009, 0xffff);
  863. /* usleep(1000); */
  864. mt6391_set_reg(codec_data, MT6397_AFUNC_AUD_CON2, 0x0000, 0x0080);
  865. mt6391_set_mux(codec_data, MT6391_DEV_OUT_EARPIECEL, MT6391_MUX_VOICE);
  866. mt6391_set_reg(codec_data, MT6397_AUDBUF_CFG0, 0x0001, 0x0001); /* mux selection */
  867. /* usleep(1000); */
  868. }
  869. static void mt6391_turn_off_voice_amp(struct mt6391_priv *codec_data)
  870. {
  871. if (codec_data->device_power[MT6391_DEV_OUT_EARPIECEL]) {
  872. pr_info("%s still on\n", __func__);
  873. return;
  874. }
  875. mt6391_set_reg(codec_data, MT6397_AFUNC_AUD_CON2, 0x0080, 0x0080);
  876. /* short HS to vcm and HS output stability enhance */
  877. mt6391_set_reg(codec_data, MT6397_AUDBUF_CFG2, 0x0022, 0xffff);
  878. mt6391_set_reg(codec_data, MT6397_AUDBUF_CFG0, 0x0880, 0xffff);
  879. mt6391_set_reg(codec_data, MT6397_IBIASDIST_CFG0, 0x1552, 0xffff); /* RG DEV ck off */
  880. mt6391_set_reg(codec_data, MT6397_AUDDAC_CON0, 0x0000, 0xffff); /* NCP off */
  881. /* Audio headset power off */
  882. mt6391_set_reg(codec_data, MT6397_AUDCLKGEN_CFG0, 0x0000, 0x0001);
  883. /* short HS to vcm and HS output stability EnhanceParasNum */
  884. mt6391_set_reg(codec_data, MT6397_AUDBUF_CFG2, 0x0022, 0xffff);
  885. if (mt6391_get_ul_status(codec_data) == false)
  886. mt6391_set_reg(codec_data, MT6397_AUDNVREGGLB_CFG0, 0x0006, 0xffff);
  887. mt6391_set_reg(codec_data, MT6397_NCP_CLKDIV_CON1, 0x0001, 0xffff);
  888. mt6391_set_reg(codec_data, MT6397_AUD_NCP0, 0x0000, 0x6000);
  889. if (mt6391_get_ul_status(codec_data) == false)
  890. mt6391_set_reg(codec_data, MT6397_AUDLDO_CFG0, 0x0192, 0xffff);
  891. mt6391_set_reg(codec_data, MT6397_AFUNC_AUD_CON2, 0x0000, 0x0080);
  892. if (!mt6391_get_dl_status(codec_data))
  893. mt6391_turn_off_dac(codec_data);
  894. }
  895. static void mt6391_turn_on_speaker_amp(struct mt6391_priv *codec_data)
  896. {
  897. pr_debug("%s\n", __func__);
  898. if (codec_data->device_power[MT6391_DEV_OUT_SPEAKERL]) {
  899. pr_info("%s turn on already\n", __func__);
  900. return;
  901. }
  902. if (mt6391_get_dl_status(codec_data) == false)
  903. mt6391_turn_on_dac(codec_data);
  904. /* here pmic analog control */
  905. mt6391_control_top_clk(codec_data, 0x0604, true); /* enable SPK related CLK */
  906. mt6391_set_reg(codec_data, MT6397_AFUNC_AUD_CON2, 0x0080, 0x0080);
  907. mt6391_set_spk_trim_offset(codec_data);
  908. /* enable VA28 , VA 33 VBAT ref , set dc */
  909. mt6391_set_reg(codec_data, MT6397_AUDLDO_CFG0, 0x0D92, 0xffff);
  910. /* set ACC mode enable NVREF */
  911. mt6391_set_reg(codec_data, MT6397_AUDNVREGGLB_CFG0, 0x000C, 0xffff);
  912. /* enable LDO ; fix me , separate for UL DL LDO */
  913. mt6391_set_reg(codec_data, MT6397_AUD_NCP0, 0xE000, 0xE000);
  914. mt6391_set_reg(codec_data, MT6397_NCP_CLKDIV_CON0, 0x102B, 0xffff); /* RG DEV ck on */
  915. mt6391_set_reg(codec_data, MT6397_NCP_CLKDIV_CON1, 0x0000, 0xffff); /* NCP on */
  916. udelay(200);
  917. /* ZCD setting gain step gain and enable */
  918. mt6391_set_reg(codec_data, MT6397_ZCD_CON0, 0x0301, 0xffff);
  919. /* audio bias adjustment */
  920. mt6391_set_reg(codec_data, MT6397_IBIASDIST_CFG0, 0x0552, 0xffff);
  921. /* set DUDIV gain ,iv buffer gain */
  922. mt6391_set_reg(codec_data, MT6397_ZCD_CON4, 0x0505, 0xffff);
  923. mt6391_set_reg(codec_data, MT6397_AUD_IV_CFG0, 0x1111, 0xffff); /* set IV buffer on */
  924. udelay(100);
  925. mt6391_set_reg(codec_data, MT6397_AUDCLKGEN_CFG0, 0x0001, 0x0001); /* reset docoder */
  926. mt6391_set_reg(codec_data, MT6397_AUDDAC_CON0, 0x000f, 0xffff); /* power on DAC */
  927. udelay(100);
  928. mt6391_set_mux(codec_data, MT6391_DEV_OUT_SPEAKERR, MT6391_MUX_AUDIO);
  929. mt6391_set_mux(codec_data, MT6391_DEV_OUT_SPEAKERL, MT6391_MUX_AUDIO);
  930. mt6391_set_reg(codec_data, MT6397_AUDBUF_CFG0, 0x0000, 0x0007); /* set Mux */
  931. mt6391_set_reg(codec_data, MT6397_AFUNC_AUD_CON2, 0x0000, 0x0080);
  932. mt6391_set_reg(codec_data, MT6397_SPK_CON9, 0x0100, 0x0f00); /* set gain L */
  933. mt6391_set_reg(codec_data, MT6397_SPK_CON5, (0x1 << 11), 0x7800); /* set gain R */
  934. if (codec_data->speaker_channel_sel == MT6391_CHANNEL_SEL_STEREO) {
  935. mt6391_set_reg(codec_data, MT6397_SPK_CON0,
  936. 0x3001 | (codec_data->speaker_mode << 2),
  937. 0xffff);
  938. mt6391_set_reg(codec_data, MT6397_SPK_CON3,
  939. 0x3001 | (codec_data->speaker_mode << 2),
  940. 0xffff);
  941. mt6391_set_reg(codec_data, MT6397_SPK_CON2, 0x0014, 0xffff);
  942. mt6391_set_reg(codec_data, MT6397_SPK_CON5, 0x0014, 0x07ff);
  943. /* SPK gain setting */
  944. mt6391_set_reg(codec_data, MT6397_SPK_CON9, 0x0800, 0xffff);
  945. mt6391_set_reg(codec_data, MT6397_SPK_CON5, (0x8 << 11), 0x7800);
  946. } else if (codec_data->speaker_channel_sel == MT6391_CHANNEL_SEL_MONO_LEFT) {
  947. mt6391_set_reg(codec_data, MT6397_SPK_CON0,
  948. 0x3001 | (codec_data->speaker_mode << 2),
  949. 0xffff);
  950. mt6391_set_reg(codec_data, MT6397_SPK_CON2, 0x0014, 0xffff);
  951. /* SPK gain setting */
  952. mt6391_set_reg(codec_data, MT6397_SPK_CON9, 0x0800, 0xffff);
  953. } else if (codec_data->speaker_channel_sel == MT6391_CHANNEL_SEL_MONO_RIGHT) {
  954. mt6391_set_reg(codec_data, MT6397_SPK_CON3,
  955. 0x3001 | (codec_data->speaker_mode << 2),
  956. 0xffff);
  957. mt6391_set_reg(codec_data, MT6397_SPK_CON5, 0x0014, 0x07ff);
  958. /* SPK gain setting */
  959. mt6391_set_reg(codec_data, MT6397_SPK_CON5, (0x8 << 11), 0x7800);
  960. } else {
  961. pr_err("%s unexpected condition\n", __func__);
  962. }
  963. /* spk output stage enabke and enable */
  964. mt6391_set_reg(codec_data, MT6397_SPK_CON11, 0x0f00, 0xffff);
  965. usleep_range(4000, 5000);
  966. pr_debug("%s done\n", __func__);
  967. }
  968. static void mt6391_turn_off_speaker_amp(struct mt6391_priv *codec_data)
  969. {
  970. pr_debug("%s\n", __func__);
  971. if (codec_data->device_power[MT6391_DEV_OUT_SPEAKERL]) {
  972. pr_info("%s still on\n", __func__);
  973. return;
  974. }
  975. mt6391_set_reg(codec_data, MT6397_AFUNC_AUD_CON2, 0x0080, 0x0080);
  976. mt6391_set_reg(codec_data, MT6397_SPK_CON0, 0x0000, 0xffff);
  977. mt6391_set_reg(codec_data, MT6397_SPK_CON3, 0x0000, 0xffff);
  978. mt6391_set_reg(codec_data, MT6397_SPK_CON11, 0x0000, 0xffff);
  979. /* enable LDO ; fix me , separate for UL DL LDO */
  980. mt6391_set_reg(codec_data, MT6397_AUDCLKGEN_CFG0, 0x0000, 0x0001);
  981. mt6391_set_reg(codec_data, MT6397_AUDDAC_CON0, 0x0000, 0xffff); /* RG DEV ck on */
  982. mt6391_set_reg(codec_data, MT6397_AUD_IV_CFG0, 0x0000, 0xffff); /* NCP on */
  983. /* Audio headset power on */
  984. mt6391_set_reg(codec_data, MT6397_IBIASDIST_CFG0, 0x1552, 0xffff);
  985. /* mt6391_set_reg(codec_data, MT6397_AUDBUF_CFG1, 0x0000, 0x0100); */
  986. if (mt6391_get_ul_status(codec_data) == false)
  987. mt6391_set_reg(codec_data, MT6397_AUDNVREGGLB_CFG0, 0x0006, 0xffff);
  988. mt6391_set_reg(codec_data, MT6397_NCP_CLKDIV_CON1, 0x0001, 0xffff); /* fix me */
  989. mt6391_set_reg(codec_data, MT6397_AUD_NCP0, 0x0000, 0x6000);
  990. if (mt6391_get_ul_status(codec_data) == false)
  991. mt6391_set_reg(codec_data, MT6397_AUDLDO_CFG0, 0x0192, 0xffff);
  992. mt6391_set_reg(codec_data, MT6397_AFUNC_AUD_CON2, 0x0000, 0x0080);
  993. mt6391_control_top_clk(codec_data, 0x0604, false); /* disable SPK related CLK */
  994. if (mt6391_get_dl_status(codec_data) == false)
  995. mt6391_turn_off_dac(codec_data);
  996. /* temp solution, set MT6397_ZCD_CON0 to 0x101 for pop noise */
  997. mt6391_set_reg(codec_data, MT6397_ZCD_CON0, 0x0101, 0xffff);
  998. pr_debug("%s done\n", __func__);
  999. }
  1000. static void mt6391_turn_on_headset_speaker_amp(struct mt6391_priv *codec_data)
  1001. {
  1002. pr_debug("%s\n", __func__);
  1003. if (codec_data->device_power[MT6391_DEV_OUT_SPEAKER_HEADSET_L]) {
  1004. pr_info("%s turn on already\n", __func__);
  1005. return;
  1006. }
  1007. if (!mt6391_get_dl_status(codec_data))
  1008. mt6391_turn_on_dac(codec_data);
  1009. /* here pmic analog control */
  1010. mt6391_control_top_clk(codec_data, 0x0604, true); /* enable SPK related CLK */
  1011. mt6391_set_reg(codec_data, MT6397_AFUNC_AUD_CON2, 0x0080, 0x0080);
  1012. mt6391_set_hp_trim_offset(codec_data);
  1013. mt6391_set_iv_hp_trim_offset(codec_data);
  1014. mt6391_set_spk_trim_offset(codec_data);
  1015. /* enable VA28 , VA 33 VBAT ref , set dc */
  1016. mt6391_set_reg(codec_data, MT6397_AUDLDO_CFG0, 0x0D92, 0xffff);
  1017. /* set ACC mode enable NVREF */
  1018. mt6391_set_reg(codec_data, MT6397_AUDNVREGGLB_CFG0, 0x000C, 0xffff);
  1019. /* enable LDO ; fix me , separate for UL DL LDO */
  1020. mt6391_set_reg(codec_data, MT6397_AUD_NCP0, 0xE000, 0xE000);
  1021. mt6391_set_reg(codec_data, MT6397_NCP_CLKDIV_CON0, 0x102B, 0xffff); /* RG DEV ck on */
  1022. mt6391_set_reg(codec_data, MT6397_NCP_CLKDIV_CON1, 0x0000, 0xffff); /* NCP on */
  1023. udelay(200);
  1024. /* ZCD setting gain step gain and enable */
  1025. mt6391_set_reg(codec_data, MT6397_ZCD_CON0, 0x0301, 0xffff);
  1026. /* select charge current ; fix me */
  1027. mt6391_set_reg(codec_data, MT6397_AUDACCDEPOP_CFG0, 0x0030, 0xffff);
  1028. /* set voice playback with headset */
  1029. mt6391_set_reg(codec_data, MT6397_AUDBUF_CFG0, 0x0008, 0xffff);
  1030. /* audio bias adjustment */
  1031. mt6391_set_reg(codec_data, MT6397_IBIASDIST_CFG0, 0x0552, 0xffff);
  1032. mt6391_set_reg(codec_data, MT6397_ZCD_CON2, 0x0C0C, 0xffff); /* HP PGA gain */
  1033. mt6391_set_reg(codec_data, MT6397_ZCD_CON3, 0x000F, 0xffff); /* HP PGA gain */
  1034. mt6391_set_reg(codec_data, MT6397_AUDBUF_CFG1, 0x0900, 0xffff); /* HP enhance */
  1035. mt6391_set_reg(codec_data, MT6397_AUDBUF_CFG2, 0x0082, 0xffff); /* HS enahnce */
  1036. mt6391_set_reg(codec_data, MT6397_AUDBUF_CFG0, 0x0009, 0xffff);
  1037. mt6391_set_reg(codec_data, MT6397_AUDBUF_CFG1, 0x0940, 0xffff); /* HP vcm short */
  1038. udelay(200);
  1039. mt6391_set_reg(codec_data, MT6397_AUDBUF_CFG0, 0x000F, 0xffff); /* HP power on */
  1040. mt6391_set_reg(codec_data, MT6397_AUDBUF_CFG1, 0x0100, 0xffff); /* HP vcm not short */
  1041. udelay(100);
  1042. mt6391_set_reg(codec_data, MT6397_AUDBUF_CFG2, 0x0022, 0xffff); /* HS VCM not short */
  1043. mt6391_set_reg(codec_data, MT6397_ZCD_CON2, 0x0808, 0xffff); /* HP PGA gain */
  1044. udelay(100);
  1045. mt6391_set_reg(codec_data, MT6397_ZCD_CON4, 0x0505, 0xffff); /* HP PGA gain */
  1046. mt6391_set_reg(codec_data, MT6397_AUD_IV_CFG0, 0x1111, 0xffff); /* set IV buffer on */
  1047. udelay(100);
  1048. mt6391_set_reg(codec_data, MT6397_AUDCLKGEN_CFG0, 0x0001, 0x0001); /* reset docoder */
  1049. mt6391_set_reg(codec_data, MT6397_AUDDAC_CON0, 0x000F, 0xffff); /* power on DAC */
  1050. udelay(100);
  1051. mt6391_set_mux(codec_data, MT6391_DEV_OUT_SPEAKERR, MT6391_MUX_AUDIO);
  1052. mt6391_set_mux(codec_data, MT6391_DEV_OUT_SPEAKERL, MT6391_MUX_AUDIO);
  1053. mt6391_set_reg(codec_data, MT6397_AUDBUF_CFG0, 0x1106, 0x1106); /* set headhpone mux */
  1054. mt6391_set_reg(codec_data, MT6397_SPK_CON9, 0x0100, 0x0f00); /* set gain L */
  1055. mt6391_set_reg(codec_data, MT6397_SPK_CON5, (0x1 << 11), 0x7800); /* set gain R */
  1056. /* speaker gain setting , trim enable , spk enable , class AB or D */
  1057. mt6391_set_reg(codec_data, MT6397_SPK_CON0,
  1058. 0x3001 | (codec_data->speaker_mode << 2),
  1059. 0xffff);
  1060. /* speaker gain setting , trim enable , spk enable , class AB or D */
  1061. mt6391_set_reg(codec_data, MT6397_SPK_CON3,
  1062. 0x3001 | (codec_data->speaker_mode << 2),
  1063. 0xffff);
  1064. /* speaker gain setting , trim enable , spk enable , class AB or D */
  1065. mt6391_set_reg(codec_data, MT6397_SPK_CON2, 0x0014, 0xffff);
  1066. mt6391_set_reg(codec_data, MT6397_SPK_CON5, 0x0014, 0x07ff);
  1067. /* SPK gain setting */
  1068. mt6391_set_reg(codec_data, MT6397_SPK_CON9, 0x0400, 0xffff);
  1069. /* SPK-R gain setting */
  1070. mt6391_set_reg(codec_data, MT6397_SPK_CON5, (0x4 << 11), 0x7800);
  1071. /* spk output stage enabke and enableAudioClockPortDST */
  1072. mt6391_set_reg(codec_data, MT6397_SPK_CON11, 0x0f00, 0xffff);
  1073. mt6391_set_reg(codec_data, MT6397_AFUNC_AUD_CON2, 0x0000, 0x0080);
  1074. usleep_range(4000, 5000);
  1075. pr_debug("%s done\n", __func__);
  1076. }
  1077. static void mt6391_turn_off_headset_speaker_amp(struct mt6391_priv *codec_data)
  1078. {
  1079. pr_debug("%s\n", __func__);
  1080. if (codec_data->device_power[MT6391_DEV_OUT_SPEAKER_HEADSET_L]) {
  1081. pr_info("%s still on\n", __func__);
  1082. return;
  1083. }
  1084. mt6391_set_reg(codec_data, MT6397_AFUNC_AUD_CON2, 0x0080, 0x0080);
  1085. mt6391_set_reg(codec_data, MT6397_SPK_CON0, 0x0000, 0xffff);
  1086. mt6391_set_reg(codec_data, MT6397_SPK_CON3, 0x0000, 0xffff);
  1087. mt6391_set_reg(codec_data, MT6397_SPK_CON11, 0x0000, 0xffff);
  1088. mt6391_set_reg(codec_data, MT6397_ZCD_CON2, 0x0C0C, 0x0f0f);
  1089. mt6391_set_reg(codec_data, MT6397_AUDBUF_CFG0, 0x0000, 0x0007);
  1090. mt6391_set_reg(codec_data, MT6397_AUDBUF_CFG0, 0x0000, 0x1fe0);
  1091. mt6391_set_reg(codec_data, MT6397_IBIASDIST_CFG0, 0x1552, 0xffff);
  1092. mt6391_set_reg(codec_data, MT6397_AUDDAC_CON0, 0x0000, 0xffff);
  1093. mt6391_set_reg(codec_data, MT6397_AUDCLKGEN_CFG0, 0x0000, 0x0001);
  1094. mt6391_set_reg(codec_data, MT6397_AUD_IV_CFG0, 0x0010, 0xffff);
  1095. mt6391_set_reg(codec_data, MT6397_AUDBUF_CFG1, 0x0000, 0x0100);
  1096. mt6391_set_reg(codec_data, MT6397_AUDBUF_CFG2, 0x0000, 0x0080);
  1097. if (!mt6391_get_ul_status(codec_data))
  1098. mt6391_set_reg(codec_data, MT6397_AUDNVREGGLB_CFG0, 0x0006, 0xffff);
  1099. mt6391_set_reg(codec_data, MT6397_NCP_CLKDIV_CON1, 0x0001, 0xffff);
  1100. mt6391_set_reg(codec_data, MT6397_AUD_NCP0, 0x0000, 0x6000);
  1101. if (!mt6391_get_ul_status(codec_data))
  1102. mt6391_set_reg(codec_data, MT6397_AUDLDO_CFG0, 0x0192, 0xffff);
  1103. mt6391_set_reg(codec_data, MT6397_AFUNC_AUD_CON2, 0x0000, 0x0080);
  1104. mt6391_control_top_clk(codec_data, 0x0604, false); /* disable SPK related CLK */
  1105. if (!mt6391_get_dl_status(codec_data))
  1106. mt6391_turn_off_dac(codec_data);
  1107. /* ZCD setting gain step gain and enable */
  1108. mt6391_set_reg(codec_data, MT6397_ZCD_CON0, 0x0101, 0xffff);
  1109. pr_debug("%s done\n", __func__);
  1110. }
  1111. static void mt6391_check_and_turn_off_all_amps(struct mt6391_priv *codec_data)
  1112. {
  1113. if (codec_data->device_power[MT6391_DEV_OUT_EARPIECEL]) {
  1114. mt6391_turn_off_voice_amp(codec_data);
  1115. mt6391_ana_clk_off(codec_data);
  1116. codec_data->device_power[MT6391_DEV_OUT_EARPIECEL] = false;
  1117. }
  1118. if (codec_data->device_power[MT6391_DEV_OUT_SPEAKERL]) {
  1119. mt6391_turn_off_speaker_amp(codec_data);
  1120. mt6391_ana_clk_off(codec_data);
  1121. codec_data->device_power[MT6391_DEV_OUT_SPEAKERL] = false;
  1122. }
  1123. if (codec_data->device_power[MT6391_DEV_OUT_HEADSETL]) {
  1124. mt6391_turn_off_headphone_amp(codec_data);
  1125. mt6391_ana_clk_off(codec_data);
  1126. codec_data->device_power[MT6391_DEV_OUT_HEADSETL] = false;
  1127. }
  1128. if (codec_data->device_power[MT6391_DEV_OUT_SPEAKER_HEADSET_L]) {
  1129. mt6391_turn_off_headset_speaker_amp(codec_data);
  1130. mt6391_ana_clk_off(codec_data);
  1131. codec_data->device_power[MT6391_DEV_OUT_SPEAKER_HEADSET_L] = false;
  1132. }
  1133. }
  1134. static void mt6391_turn_on_dmic(struct mt6391_priv *codec_data)
  1135. {
  1136. uint32_t rate = codec_data->sample_rate[MT6391_ADDA_ADC];
  1137. uint32_t warmup_time = codec_data->dmic_warmup_time_us;
  1138. /* pmic digital part */
  1139. mt6391_set_reg(codec_data, MT6397_AUDCLKGEN_CFG0, 0x0000, 0x0002);
  1140. mt6391_set_reg(codec_data, MT6397_AFE_UL_SRC_CON0_L, 0x0000, 0xffff);
  1141. mt6391_control_top_clk(codec_data, 0x0003, true);
  1142. mt6391_set_reg(codec_data, MT6397_ANA_AUDIO_TOP_CON0, 0x0000, 0xffff);
  1143. mt6391_set_reg(codec_data, MT6397_AFE_UL_SRC_CON0_H,
  1144. 0x00e0 | mt6391_get_ul_voice_mode(rate),
  1145. 0xffff);
  1146. mt6391_set_reg(codec_data, MT6397_AFE_UL_DL_CON0, 0x007f, 0xffff);
  1147. mt6391_set_reg(codec_data, MT6397_AFE_UL_SRC_CON0_L, 0x0023, 0xffff);
  1148. /* AudioMachineDevice */
  1149. mt6391_set_reg(codec_data, MT6397_AUDNVREGGLB_CFG0, 0x0000, 0x0002);
  1150. mt6391_set_reg(codec_data, MT6397_AUDDIGMI_CON0, 0x0181, 0xffff);
  1151. if (warmup_time > 0)
  1152. usleep_range(warmup_time, warmup_time + 1);
  1153. }
  1154. static void mt6391_turn_off_dmic(struct mt6391_priv *codec_data)
  1155. {
  1156. /* AudioMachineDevice */
  1157. mt6391_set_reg(codec_data, MT6397_AUDDIGMI_CON0, 0x0080, 0xffff);
  1158. /* pmic digital part */
  1159. mt6391_set_reg(codec_data, MT6397_AFE_UL_SRC_CON0_H, 0x0000, 0xffff);
  1160. mt6391_set_reg(codec_data, MT6397_AFE_UL_SRC_CON0_L, 0x0000, 0xffff);
  1161. if (mt6391_get_dl_status(codec_data) == false) {
  1162. mt6391_set_reg(codec_data, MT6397_AUDNVREGGLB_CFG0, 0x0002, 0x0002);
  1163. mt6391_set_reg(codec_data, MT6397_AFE_UL_DL_CON0, 0x0000, 0xffff);
  1164. }
  1165. }
  1166. static void mt6391_turn_on_adc(struct mt6391_priv *codec_data, int adc_type)
  1167. {
  1168. if (!mt6391_get_adc_status(codec_data)) {
  1169. uint32_t rate = codec_data->sample_rate[MT6391_ADDA_ADC];
  1170. uint32_t warmup_time = codec_data->adc_warmup_time_us;
  1171. /* pmic digital part */
  1172. mt6391_set_reg(codec_data, MT6397_AUDCLKGEN_CFG0, 0x0000, 0x0002);
  1173. mt6391_set_reg(codec_data, MT6397_AFE_UL_SRC_CON0_L, 0x0000, 0xffff);
  1174. mt6391_set_reg(codec_data, MT6397_AUDCLKGEN_CFG0, 0x0002, 0x0002);
  1175. mt6391_control_top_clk(codec_data, 0x0003, true);
  1176. mt6391_set_reg(codec_data, MT6397_ANA_AUDIO_TOP_CON0, 0x0000, 0xffff);
  1177. mt6391_set_reg(codec_data, MT6397_AFE_UL_SRC_CON0_H,
  1178. 0x0000 | mt6391_get_ul_voice_mode(rate), 0xffff);
  1179. mt6391_set_reg(codec_data, MT6397_AFE_UL_DL_CON0, 0x007f, 0xffff);
  1180. mt6391_set_reg(codec_data, MT6397_AFE_UL_SRC_CON0_L, 0x0001, 0xffff);
  1181. /* pmic analog part */
  1182. mt6391_set_reg(codec_data, MT6397_AUDNVREGGLB_CFG0, 0x000c, 0xffff);
  1183. mt6391_set_reg(codec_data, MT6397_AUDLDO_CFG0, 0x0D92, 0xffff);
  1184. mt6391_set_reg(codec_data, MT6397_AUD_NCP0, 0x9000, 0x9000);
  1185. mt6391_set_mux(codec_data, MT6391_DEV_IN_ADC1, MT6391_MUX_IN_PREAMP_1);
  1186. mt6391_set_mux(codec_data, MT6391_DEV_IN_ADC2, MT6391_MUX_IN_PREAMP_2);
  1187. /* open power */
  1188. mt6391_set_reg(codec_data, MT6397_AUDPREAMP_CON0, 0x0003, 0x0003);
  1189. mt6391_set_reg(codec_data, MT6397_AUDADC_CON0, 0x0093, 0xffff);
  1190. mt6391_set_reg(codec_data, MT6397_NCP_CLKDIV_CON0, 0x102B, 0x102B);
  1191. mt6391_set_reg(codec_data, MT6397_NCP_CLKDIV_CON1, 0x0000, 0xffff);
  1192. mt6391_set_reg(codec_data, MT6397_AUDDIGMI_CON0, 0x0180, 0x0180);
  1193. mt6391_set_reg(codec_data, MT6397_AUDPREAMPGAIN_CON0, 0x0033, 0x0033);
  1194. if (warmup_time > 0)
  1195. usleep_range(warmup_time, warmup_time + 1);
  1196. }
  1197. }
  1198. static void mt6391_turn_off_adc(struct mt6391_priv *codec_data, int adc_type)
  1199. {
  1200. if (!mt6391_get_adc_status(codec_data)) {
  1201. /* pmic analog part */
  1202. mt6391_set_reg(codec_data, MT6397_AUDPREAMP_CON0, 0x0000, 0x0003);
  1203. mt6391_set_reg(codec_data, MT6397_AUDADC_CON0, 0x00B4, 0xffff);
  1204. mt6391_set_reg(codec_data, MT6397_AUDDIGMI_CON0, 0x0080, 0xffff);
  1205. mt6391_set_reg(codec_data, MT6397_AUD_NCP0, 0x0000, 0x1000);
  1206. mt6391_set_reg(codec_data, MT6397_AUDLSBUF_CON0, 0x0000, 0x0003);
  1207. if (mt6391_get_dl_status(codec_data) == false)
  1208. mt6391_set_reg(codec_data, MT6397_AUDNVREGGLB_CFG0, 0x0006, 0xffff);
  1209. if (mt6391_get_dl_status(codec_data) == false)
  1210. mt6391_set_reg(codec_data, MT6397_AUDLDO_CFG0, 0x0192, 0xffff);
  1211. mt6391_set_reg(codec_data, MT6397_AUDCLKGEN_CFG0, 0x0000, 0x0002);
  1212. /* pmic digital part */
  1213. mt6391_set_reg(codec_data, MT6397_AFE_UL_SRC_CON0_L, 0x0000, 0xffff);
  1214. if (!mt6391_get_dl_status(codec_data))
  1215. mt6391_set_reg(codec_data, MT6397_AFE_UL_DL_CON0, 0x0000, 0xffff);
  1216. }
  1217. }
  1218. /* snd kcontrol implementation */
  1219. static int mt6391_audio_amp_get(struct snd_kcontrol *kcontrol,
  1220. struct snd_ctl_elem_value *ucontrol)
  1221. {
  1222. struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
  1223. struct mt6391_priv *codec_data = snd_soc_component_get_drvdata(component);
  1224. ucontrol->value.integer.value[0] =
  1225. codec_data->device_power[MT6391_DEV_OUT_HEADSETL] ? 1 : 0;
  1226. return 0;
  1227. }
  1228. static int mt6391_audio_amp_set(struct snd_kcontrol *kcontrol,
  1229. struct snd_ctl_elem_value *ucontrol)
  1230. {
  1231. struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
  1232. struct mt6391_priv *codec_data = snd_soc_component_get_drvdata(component);
  1233. mutex_lock(&codec_data->ctrl_mutex);
  1234. pr_debug("%s gain = %ld\n ", __func__, ucontrol->value.integer.value[0]);
  1235. if (ucontrol->value.integer.value[0] &&
  1236. !codec_data->device_power[MT6391_DEV_OUT_HEADSETL]) {
  1237. mt6391_check_and_turn_off_all_amps(codec_data);
  1238. mt6391_ana_clk_on(codec_data);
  1239. mt6391_turn_on_headphone_amp(codec_data);
  1240. codec_data->device_power[MT6391_DEV_OUT_HEADSETL] = true;
  1241. } else if (!ucontrol->value.integer.value[0] &&
  1242. codec_data->device_power[MT6391_DEV_OUT_HEADSETL]) {
  1243. codec_data->device_power[MT6391_DEV_OUT_HEADSETL] = false;
  1244. mt6391_turn_off_headphone_amp(codec_data);
  1245. mt6391_ana_clk_off(codec_data);
  1246. }
  1247. mutex_unlock(&codec_data->ctrl_mutex);
  1248. return 0;
  1249. }
  1250. static int mt6391_voice_amp_get(struct snd_kcontrol *kcontrol,
  1251. struct snd_ctl_elem_value *ucontrol)
  1252. {
  1253. struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
  1254. struct mt6391_priv *codec_data = snd_soc_component_get_drvdata(component);
  1255. ucontrol->value.integer.value[0] =
  1256. codec_data->device_power[MT6391_DEV_OUT_EARPIECEL] ? 1 : 0;
  1257. return 0;
  1258. }
  1259. static int mt6391_voice_amp_set(struct snd_kcontrol *kcontrol,
  1260. struct snd_ctl_elem_value *ucontrol)
  1261. {
  1262. struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
  1263. struct mt6391_priv *codec_data = snd_soc_component_get_drvdata(component);
  1264. mutex_lock(&codec_data->ctrl_mutex);
  1265. pr_debug("%s %ld\n ", __func__, ucontrol->value.integer.value[0]);
  1266. if (ucontrol->value.integer.value[0] &&
  1267. !codec_data->device_power[MT6391_DEV_OUT_EARPIECEL]) {
  1268. mt6391_check_and_turn_off_all_amps(codec_data);
  1269. mt6391_ana_clk_on(codec_data);
  1270. mt6391_turn_on_voice_amp(codec_data);
  1271. codec_data->device_power[MT6391_DEV_OUT_EARPIECEL] = true;
  1272. } else if (!ucontrol->value.integer.value[0] &&
  1273. codec_data->device_power[MT6391_DEV_OUT_EARPIECEL]) {
  1274. codec_data->device_power[MT6391_DEV_OUT_EARPIECEL] = false;
  1275. mt6391_turn_off_voice_amp(codec_data);
  1276. mt6391_ana_clk_off(codec_data);
  1277. }
  1278. mutex_unlock(&codec_data->ctrl_mutex);
  1279. return 0;
  1280. }
  1281. static int mt6391_speaker_amp_get(struct snd_kcontrol *kcontrol,
  1282. struct snd_ctl_elem_value *ucontrol)
  1283. {
  1284. struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
  1285. struct mt6391_priv *codec_data = snd_soc_component_get_drvdata(component);
  1286. ucontrol->value.integer.value[0] =
  1287. codec_data->device_power[MT6391_DEV_OUT_SPEAKERL] ? 1 : 0;
  1288. return 0;
  1289. }
  1290. static int mt6391_speaker_amp_set(struct snd_kcontrol *kcontrol,
  1291. struct snd_ctl_elem_value *ucontrol)
  1292. {
  1293. struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
  1294. struct mt6391_priv *codec_data = snd_soc_component_get_drvdata(component);
  1295. mutex_lock(&codec_data->ctrl_mutex);
  1296. pr_debug("%s gain = %ld\n ", __func__, ucontrol->value.integer.value[0]);
  1297. if (ucontrol->value.integer.value[0] &&
  1298. !codec_data->device_power[MT6391_DEV_OUT_SPEAKERL]) {
  1299. mt6391_check_and_turn_off_all_amps(codec_data);
  1300. mt6391_ana_clk_on(codec_data);
  1301. mt6391_turn_on_speaker_amp(codec_data);
  1302. codec_data->device_power[MT6391_DEV_OUT_SPEAKERL] = true;
  1303. } else if (!ucontrol->value.integer.value[0] &&
  1304. codec_data->device_power[MT6391_DEV_OUT_SPEAKERL]) {
  1305. codec_data->device_power[MT6391_DEV_OUT_SPEAKERL] = false;
  1306. mt6391_turn_off_speaker_amp(codec_data);
  1307. mt6391_ana_clk_off(codec_data);
  1308. }
  1309. mutex_unlock(&codec_data->ctrl_mutex);
  1310. return 0;
  1311. }
  1312. static int mt6391_headset_speaker_amp_get(struct snd_kcontrol *kcontrol,
  1313. struct snd_ctl_elem_value *ucontrol)
  1314. {
  1315. struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
  1316. struct mt6391_priv *codec_data = snd_soc_component_get_drvdata(component);
  1317. ucontrol->value.integer.value[0] =
  1318. codec_data->device_power[MT6391_DEV_OUT_SPEAKER_HEADSET_L] ? 1 : 0;
  1319. return 0;
  1320. }
  1321. static int mt6391_headset_speaker_amp_set(struct snd_kcontrol *kcontrol,
  1322. struct snd_ctl_elem_value *ucontrol)
  1323. {
  1324. struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
  1325. struct mt6391_priv *codec_data = snd_soc_component_get_drvdata(component);
  1326. mutex_lock(&codec_data->ctrl_mutex);
  1327. pr_debug("%s gain = %ld\n ", __func__, ucontrol->value.integer.value[0]);
  1328. if (ucontrol->value.integer.value[0] &&
  1329. !codec_data->device_power[MT6391_DEV_OUT_SPEAKER_HEADSET_L]) {
  1330. mt6391_check_and_turn_off_all_amps(codec_data);
  1331. mt6391_ana_clk_on(codec_data);
  1332. mt6391_turn_on_headset_speaker_amp(codec_data);
  1333. codec_data->device_power[MT6391_DEV_OUT_SPEAKER_HEADSET_L] = true;
  1334. } else if (!ucontrol->value.integer.value[0] &&
  1335. codec_data->device_power[MT6391_DEV_OUT_SPEAKER_HEADSET_L]) {
  1336. codec_data->device_power[MT6391_DEV_OUT_SPEAKER_HEADSET_L] = false;
  1337. mt6391_turn_off_headset_speaker_amp(codec_data);
  1338. mt6391_ana_clk_off(codec_data);
  1339. }
  1340. mutex_unlock(&codec_data->ctrl_mutex);
  1341. return 0;
  1342. }
  1343. static int mt6391_headset_pgal_get(struct snd_kcontrol *kcontrol,
  1344. struct snd_ctl_elem_value *ucontrol)
  1345. {
  1346. struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
  1347. struct mt6391_priv *codec_data = snd_soc_component_get_drvdata(component);
  1348. ucontrol->value.integer.value[0] = codec_data->device_volume[MT6391_VOL_HPOUTL];
  1349. return 0;
  1350. }
  1351. static int mt6391_headset_pgal_set(struct snd_kcontrol *kcontrol,
  1352. struct snd_ctl_elem_value *ucontrol)
  1353. {
  1354. struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
  1355. struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
  1356. struct mt6391_priv *codec_data = snd_soc_component_get_drvdata(component);
  1357. int index = 0;
  1358. pr_debug("%s\n", __func__);
  1359. if (ucontrol->value.enumerated.item[0] > e->items) {
  1360. pr_err("%s out of bound\n", __func__);
  1361. return -EINVAL;
  1362. }
  1363. index = ucontrol->value.integer.value[0];
  1364. mt6391_set_reg(codec_data, MT6397_ZCD_CON2, index, 0x0000000F);
  1365. codec_data->device_volume[MT6391_VOL_HPOUTL] = index;
  1366. return 0;
  1367. }
  1368. static int mt6391_headset_pgar_get(struct snd_kcontrol *kcontrol,
  1369. struct snd_ctl_elem_value *ucontrol)
  1370. {
  1371. struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
  1372. struct mt6391_priv *codec_data = snd_soc_component_get_drvdata(component);
  1373. ucontrol->value.integer.value[0] = codec_data->device_volume[MT6391_VOL_HPOUTR];
  1374. return 0;
  1375. }
  1376. static int mt6391_headset_pgar_set(struct snd_kcontrol *kcontrol,
  1377. struct snd_ctl_elem_value *ucontrol)
  1378. {
  1379. struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
  1380. struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
  1381. struct mt6391_priv *codec_data = snd_soc_component_get_drvdata(component);
  1382. int index = 0;
  1383. pr_debug("%s\n", __func__);
  1384. if (ucontrol->value.enumerated.item[0] > e->items) {
  1385. pr_err("%s out of bound\n", __func__);
  1386. return -EINVAL;
  1387. }
  1388. index = ucontrol->value.integer.value[0];
  1389. mt6391_set_reg(codec_data, MT6397_ZCD_CON2, index << 8, 0x000000F00);
  1390. codec_data->device_volume[MT6391_VOL_HPOUTR] = index;
  1391. return 0;
  1392. }
  1393. static int mt6391_handset_pga_get(struct snd_kcontrol *kcontrol,
  1394. struct snd_ctl_elem_value *ucontrol)
  1395. {
  1396. struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
  1397. struct mt6391_priv *codec_data = snd_soc_component_get_drvdata(component);
  1398. ucontrol->value.integer.value[0] = codec_data->device_volume[MT6391_VOL_HSOUTL];
  1399. return 0;
  1400. }
  1401. static int mt6391_handset_pga_set(struct snd_kcontrol *kcontrol,
  1402. struct snd_ctl_elem_value *ucontrol)
  1403. {
  1404. struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
  1405. struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
  1406. struct mt6391_priv *codec_data = snd_soc_component_get_drvdata(component);
  1407. int index = 0;
  1408. pr_debug("%s %ld\n", __func__, ucontrol->value.integer.value[0]);
  1409. if (ucontrol->value.enumerated.item[0] > e->items) {
  1410. pr_err("%s out of bound\n", __func__);
  1411. return -EINVAL;
  1412. }
  1413. index = ucontrol->value.integer.value[0];
  1414. mt6391_set_reg(codec_data, MT6397_ZCD_CON3, index, 0xF);
  1415. codec_data->device_volume[MT6391_VOL_HSOUTL] = index;
  1416. return 0;
  1417. }
  1418. static int mt6391_speaker_pgal_get(struct snd_kcontrol *kcontrol,
  1419. struct snd_ctl_elem_value *ucontrol)
  1420. {
  1421. struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
  1422. struct mt6391_priv *codec_data = snd_soc_component_get_drvdata(component);
  1423. ucontrol->value.integer.value[0] = codec_data->device_volume[MT6391_VOL_SPKL];
  1424. return 0;
  1425. }
  1426. static int mt6391_speaker_pgal_set(struct snd_kcontrol *kcontrol,
  1427. struct snd_ctl_elem_value *ucontrol)
  1428. {
  1429. struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
  1430. struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
  1431. struct mt6391_priv *codec_data = snd_soc_component_get_drvdata(component);
  1432. int index = 0;
  1433. pr_debug("%s\n", __func__);
  1434. if (ucontrol->value.enumerated.item[0] > e->items) {
  1435. pr_err("%s out of bound\n", __func__);
  1436. return -EINVAL;
  1437. }
  1438. index = ucontrol->value.integer.value[0];
  1439. mt6391_set_reg(codec_data, MT6397_SPK_CON9, index << 8, 0x00000f00);
  1440. codec_data->device_volume[MT6391_VOL_SPKL] = index;
  1441. return 0;
  1442. }
  1443. static int mt6391_speaker_pgar_get(struct snd_kcontrol *kcontrol,
  1444. struct snd_ctl_elem_value *ucontrol)
  1445. {
  1446. struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
  1447. struct mt6391_priv *codec_data = snd_soc_component_get_drvdata(component);
  1448. ucontrol->value.integer.value[0] = codec_data->device_volume[MT6391_VOL_SPKR];
  1449. return 0;
  1450. }
  1451. static int mt6391_speaker_pgar_set(struct snd_kcontrol *kcontrol,
  1452. struct snd_ctl_elem_value *ucontrol)
  1453. {
  1454. struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
  1455. struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
  1456. struct mt6391_priv *codec_data = snd_soc_component_get_drvdata(component);
  1457. int index = 0;
  1458. pr_debug("%s\n", __func__);
  1459. if (ucontrol->value.enumerated.item[0] > e->items) {
  1460. pr_err("%s out of bound\n", __func__);
  1461. return -EINVAL;
  1462. }
  1463. index = ucontrol->value.integer.value[0];
  1464. mt6391_set_reg(codec_data, MT6397_SPK_CON5, index << 11, 0x00007800);
  1465. codec_data->device_volume[MT6391_VOL_SPKR] = index;
  1466. return 0;
  1467. }
  1468. static int mt6391_speaker_channel_set(struct snd_kcontrol *kcontrol,
  1469. struct snd_ctl_elem_value *ucontrol)
  1470. {
  1471. struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
  1472. struct mt6391_priv *codec_data = snd_soc_component_get_drvdata(component);
  1473. pr_debug("%s\n", __func__);
  1474. codec_data->speaker_channel_sel = ucontrol->value.integer.value[0];
  1475. return 0;
  1476. }
  1477. static int mt6391_speaker_channel_get(struct snd_kcontrol *kcontrol,
  1478. struct snd_ctl_elem_value *ucontrol)
  1479. {
  1480. struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
  1481. struct mt6391_priv *codec_data = snd_soc_component_get_drvdata(component);
  1482. pr_debug("%s = %d\n", __func__, codec_data->speaker_channel_sel);
  1483. ucontrol->value.integer.value[0] = codec_data->speaker_channel_sel;
  1484. return 0;
  1485. }
  1486. static int mt6391_speaker_oc_flag_get(struct snd_kcontrol *kcontrol,
  1487. struct snd_ctl_elem_value *ucontrol)
  1488. {
  1489. struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
  1490. struct mt6391_priv *codec_data = snd_soc_component_get_drvdata(component);
  1491. uint32_t reg_value = mt6391_get_reg(codec_data, MT6397_SPK_CON6);
  1492. if (codec_data->speaker_mode == MT6391_CLASS_AB)
  1493. ucontrol->value.integer.value[0] = (reg_value & 0xA000) ? 1 : 0;
  1494. else
  1495. ucontrol->value.integer.value[0] = (reg_value & 0x5000) ? 1 : 0;
  1496. return 0;
  1497. }
  1498. static int mt6391_speaker_oc_flag_set(struct snd_kcontrol *kcontrol,
  1499. struct snd_ctl_elem_value *ucontrol)
  1500. {
  1501. return 0;
  1502. }
  1503. static int mt6391_dac_newif_sck_get(struct snd_kcontrol *kcontrol,
  1504. struct snd_ctl_elem_value *ucontrol)
  1505. {
  1506. struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
  1507. struct mt6391_priv *codec_data = snd_soc_component_get_drvdata(component);
  1508. uint32_t reg_value = mt6391_get_reg(codec_data, MT6397_AFE_PMIC_NEWIF_CFG2);
  1509. ucontrol->value.integer.value[0] = (reg_value & 0x8000) ? 1 : 0;
  1510. return 0;
  1511. }
  1512. static int mt6391_dac_newif_sck_set(struct snd_kcontrol *kcontrol,
  1513. struct snd_ctl_elem_value *ucontrol)
  1514. {
  1515. struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
  1516. struct mt6391_priv *codec_data = snd_soc_component_get_drvdata(component);
  1517. if (ucontrol->value.integer.value[0] == 0)
  1518. mt6391_set_reg(codec_data, MT6397_AFE_PMIC_NEWIF_CFG2, 0 << 15, 1 << 15);
  1519. else if (ucontrol->value.integer.value[0] == 1)
  1520. mt6391_set_reg(codec_data, MT6397_AFE_PMIC_NEWIF_CFG2, 1 << 15, 1 << 15);
  1521. return 0;
  1522. }
  1523. static int mt6391_dmic_get(struct snd_kcontrol *kcontrol,
  1524. struct snd_ctl_elem_value *ucontrol)
  1525. {
  1526. struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
  1527. struct mt6391_priv *codec_data = snd_soc_component_get_drvdata(component);
  1528. ucontrol->value.integer.value[0] =
  1529. codec_data->device_power[MT6391_DEV_IN_DIGITAL_MIC] ? 1 : 0;
  1530. return 0;
  1531. }
  1532. static int mt6391_dmic_set(struct snd_kcontrol *kcontrol,
  1533. struct snd_ctl_elem_value *ucontrol)
  1534. {
  1535. struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
  1536. struct mt6391_priv *codec_data = snd_soc_component_get_drvdata(component);
  1537. pr_debug("%s\n", __func__);
  1538. if (ucontrol->value.integer.value[0] &&
  1539. !codec_data->device_power[MT6391_DEV_IN_DIGITAL_MIC]) {
  1540. mt6391_ana_clk_on(codec_data);
  1541. mt6391_turn_on_dmic(codec_data);
  1542. codec_data->device_power[MT6391_DEV_IN_DIGITAL_MIC] = true;
  1543. } else if (!ucontrol->value.integer.value[0] &&
  1544. codec_data->device_power[MT6391_DEV_IN_DIGITAL_MIC]) {
  1545. codec_data->device_power[MT6391_DEV_IN_DIGITAL_MIC] = false;
  1546. mt6391_turn_off_dmic(codec_data);
  1547. mt6391_ana_clk_off(codec_data);
  1548. }
  1549. return 0;
  1550. }
  1551. static int mt6391_adc1_get(struct snd_kcontrol *kcontrol,
  1552. struct snd_ctl_elem_value *ucontrol)
  1553. {
  1554. struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
  1555. struct mt6391_priv *codec_data = snd_soc_component_get_drvdata(component);
  1556. ucontrol->value.integer.value[0] =
  1557. codec_data->device_power[MT6391_DEV_IN_ADC1] ? 1 : 0;
  1558. return 0;
  1559. }
  1560. static int mt6391_adc1_set(struct snd_kcontrol *kcontrol,
  1561. struct snd_ctl_elem_value *ucontrol)
  1562. {
  1563. struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
  1564. struct mt6391_priv *codec_data = snd_soc_component_get_drvdata(component);
  1565. pr_debug("%s\n", __func__);
  1566. if (ucontrol->value.integer.value[0]
  1567. && !codec_data->device_power[MT6391_DEV_IN_ADC1]) {
  1568. mt6391_ana_clk_on(codec_data);
  1569. mt6391_turn_on_adc(codec_data, MT6391_DEV_IN_ADC1);
  1570. codec_data->device_power[MT6391_DEV_IN_ADC1] = true;
  1571. } else if (!ucontrol->value.integer.value[0] &&
  1572. codec_data->device_power[MT6391_DEV_IN_ADC1]) {
  1573. codec_data->device_power[MT6391_DEV_IN_ADC1] = false;
  1574. mt6391_turn_off_adc(codec_data, MT6391_DEV_IN_ADC1);
  1575. mt6391_ana_clk_off(codec_data);
  1576. }
  1577. return 0;
  1578. }
  1579. static int mt6391_adc2_get(struct snd_kcontrol *kcontrol,
  1580. struct snd_ctl_elem_value *ucontrol)
  1581. {
  1582. struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
  1583. struct mt6391_priv *codec_data = snd_soc_component_get_drvdata(component);
  1584. ucontrol->value.integer.value[0] =
  1585. codec_data->device_power[MT6391_DEV_IN_ADC2] ? 1 : 0;
  1586. return 0;
  1587. }
  1588. static int mt6391_adc2_set(struct snd_kcontrol *kcontrol,
  1589. struct snd_ctl_elem_value *ucontrol)
  1590. {
  1591. struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
  1592. struct mt6391_priv *codec_data = snd_soc_component_get_drvdata(component);
  1593. pr_debug("%s\n", __func__);
  1594. if (ucontrol->value.integer.value[0]
  1595. && !codec_data->device_power[MT6391_DEV_IN_ADC2]) {
  1596. mt6391_ana_clk_on(codec_data);
  1597. mt6391_turn_on_adc(codec_data, MT6391_DEV_IN_ADC2);
  1598. codec_data->device_power[MT6391_DEV_IN_ADC2] = true;
  1599. } else if (!ucontrol->value.integer.value[0] &&
  1600. codec_data->device_power[MT6391_DEV_IN_ADC2]) {
  1601. codec_data->device_power[MT6391_DEV_IN_ADC2] = false;
  1602. mt6391_turn_off_adc(codec_data, MT6391_DEV_IN_ADC2);
  1603. mt6391_ana_clk_off(codec_data);
  1604. }
  1605. return 0;
  1606. }
  1607. static int mt6391_preamp1_mux_get(struct snd_kcontrol *kcontrol,
  1608. struct snd_ctl_elem_value *ucontrol)
  1609. {
  1610. struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
  1611. struct mt6391_priv *codec_data = snd_soc_component_get_drvdata(component);
  1612. ucontrol->value.integer.value[0] = codec_data->device_mux[MT6391_MUX_IN_PREAMP_1];
  1613. return 0;
  1614. }
  1615. static int mt6391_preamp1_mux_set(struct snd_kcontrol *kcontrol,
  1616. struct snd_ctl_elem_value *ucontrol)
  1617. {
  1618. struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
  1619. struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
  1620. struct mt6391_priv *codec_data = snd_soc_component_get_drvdata(component);
  1621. pr_debug("%s\n", __func__);
  1622. if (ucontrol->value.enumerated.item[0] > e->items) {
  1623. pr_err("%s out of bound\n", __func__);
  1624. return -EINVAL;
  1625. }
  1626. if (ucontrol->value.integer.value[0] == 1)
  1627. mt6391_set_mux(codec_data, MT6391_DEV_IN_PREAMP_L, MT6391_MUX_IN_MIC1);
  1628. else if (ucontrol->value.integer.value[0] == 2)
  1629. mt6391_set_mux(codec_data, MT6391_DEV_IN_PREAMP_L, MT6391_MUX_IN_MIC2);
  1630. else if (ucontrol->value.integer.value[0] == 3)
  1631. mt6391_set_mux(codec_data, MT6391_DEV_IN_PREAMP_L, MT6391_MUX_IN_MIC3);
  1632. else if (ucontrol->value.integer.value[0] != 0)
  1633. pr_warn("%s unexpected value %ld", __func__, ucontrol->value.integer.value[0]);
  1634. pr_debug("%s done\n", __func__);
  1635. codec_data->device_mux[MT6391_MUX_IN_PREAMP_1] = ucontrol->value.integer.value[0];
  1636. return 0;
  1637. }
  1638. static int mt6391_preamp2_mux_get(struct snd_kcontrol *kcontrol,
  1639. struct snd_ctl_elem_value *ucontrol)
  1640. {
  1641. struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
  1642. struct mt6391_priv *codec_data = snd_soc_component_get_drvdata(component);
  1643. ucontrol->value.integer.value[0] = codec_data->device_mux[MT6391_MUX_IN_PREAMP_2];
  1644. return 0;
  1645. }
  1646. static int mt6391_preamp2_mux_set(struct snd_kcontrol *kcontrol,
  1647. struct snd_ctl_elem_value *ucontrol)
  1648. {
  1649. struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
  1650. struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
  1651. struct mt6391_priv *codec_data = snd_soc_component_get_drvdata(component);
  1652. pr_debug("%s\n", __func__);
  1653. if (ucontrol->value.enumerated.item[0] > e->items) {
  1654. pr_err("%s out of bound\n", __func__);
  1655. return -EINVAL;
  1656. }
  1657. if (ucontrol->value.integer.value[0] == 1)
  1658. mt6391_set_mux(codec_data, MT6391_DEV_IN_PREAMP_R, MT6391_MUX_IN_MIC1);
  1659. else if (ucontrol->value.integer.value[0] == 2)
  1660. mt6391_set_mux(codec_data, MT6391_DEV_IN_PREAMP_R, MT6391_MUX_IN_MIC2);
  1661. else if (ucontrol->value.integer.value[0] == 3)
  1662. mt6391_set_mux(codec_data, MT6391_DEV_IN_PREAMP_R, MT6391_MUX_IN_MIC3);
  1663. else if (ucontrol->value.integer.value[0] != 0)
  1664. pr_warn("%s unexpected value %ld", __func__, ucontrol->value.integer.value[0]);
  1665. pr_debug("%s done\n", __func__);
  1666. codec_data->device_mux[MT6391_MUX_IN_PREAMP_2] = ucontrol->value.integer.value[0];
  1667. return 0;
  1668. }
  1669. static int mt6391_preamp1_gain_get(struct snd_kcontrol *kcontrol,
  1670. struct snd_ctl_elem_value *ucontrol)
  1671. {
  1672. struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
  1673. struct mt6391_priv *codec_data = snd_soc_component_get_drvdata(component);
  1674. ucontrol->value.integer.value[0] =
  1675. codec_data->device_volume[MT6391_VOL_MICAMPL];
  1676. return 0;
  1677. }
  1678. static int mt6391_preamp1_gain_set(struct snd_kcontrol *kcontrol,
  1679. struct snd_ctl_elem_value *ucontrol)
  1680. {
  1681. struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
  1682. struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
  1683. struct mt6391_priv *codec_data = snd_soc_component_get_drvdata(component);
  1684. int index = 0;
  1685. pr_debug("%s\n", __func__);
  1686. if (ucontrol->value.enumerated.item[0] > e->items) {
  1687. pr_err("%s out of bound\n", __func__);
  1688. return -EINVAL;
  1689. }
  1690. index = ucontrol->value.integer.value[0];
  1691. mt6391_set_reg(codec_data, MT6397_AUDPREAMPGAIN_CON0, index << 0, 0x00000007);
  1692. codec_data->device_volume[MT6391_VOL_MICAMPL] = index;
  1693. return 0;
  1694. }
  1695. static int mt6391_preamp2_gain_get(struct snd_kcontrol *kcontrol,
  1696. struct snd_ctl_elem_value *ucontrol)
  1697. {
  1698. struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
  1699. struct mt6391_priv *codec_data = snd_soc_component_get_drvdata(component);
  1700. ucontrol->value.integer.value[0] =
  1701. codec_data->device_volume[MT6391_VOL_MICAMPR];
  1702. return 0;
  1703. }
  1704. static int mt6391_preamp2_gain_set(struct snd_kcontrol *kcontrol,
  1705. struct snd_ctl_elem_value *ucontrol)
  1706. {
  1707. struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
  1708. struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
  1709. struct mt6391_priv *codec_data = snd_soc_component_get_drvdata(component);
  1710. int index = 0;
  1711. pr_debug("%s\n", __func__);
  1712. if (ucontrol->value.enumerated.item[0] > e->items) {
  1713. pr_err("%s out of bound\n", __func__);
  1714. return -EINVAL;
  1715. }
  1716. index = ucontrol->value.integer.value[0];
  1717. mt6391_set_reg(codec_data, MT6397_AUDPREAMPGAIN_CON0, index << 4, 0x00000070);
  1718. codec_data->device_volume[MT6391_VOL_MICAMPR] = index;
  1719. return 0;
  1720. }
  1721. static int mt6391_loopback_get(struct snd_kcontrol *kcontrol,
  1722. struct snd_ctl_elem_value *ucontrol)
  1723. {
  1724. struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
  1725. struct mt6391_priv *codec_data = snd_soc_component_get_drvdata(component);
  1726. ucontrol->value.integer.value[0] = codec_data->codec_loopback_type;
  1727. return 0;
  1728. }
  1729. static int mt6391_loopback_set(struct snd_kcontrol *kcontrol,
  1730. struct snd_ctl_elem_value *ucontrol)
  1731. {
  1732. struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
  1733. struct mt6391_priv *codec_data = snd_soc_component_get_drvdata(component);
  1734. uint32_t previous_type = codec_data->codec_loopback_type;
  1735. long set_value = ucontrol->value.integer.value[0];
  1736. pr_debug("%s %ld\n", __func__, set_value);
  1737. if (previous_type == set_value) {
  1738. pr_debug("%s dummy operation for %u", __func__, codec_data->codec_loopback_type);
  1739. return 0;
  1740. }
  1741. if (previous_type != CODEC_LOOPBACK_NONE) {
  1742. /* disable uplink */
  1743. if (previous_type == CODEC_LOOPBACK_AMIC_TO_SPK ||
  1744. previous_type == CODEC_LOOPBACK_AMIC_TO_HP ||
  1745. previous_type == CODEC_LOOPBACK_HEADSET_MIC_TO_SPK ||
  1746. previous_type == CODEC_LOOPBACK_HEADSET_MIC_TO_HP) {
  1747. if (codec_data->device_power[MT6391_DEV_IN_ADC1]) {
  1748. codec_data->device_power[MT6391_DEV_IN_ADC1] = false;
  1749. mt6391_turn_off_adc(codec_data, MT6391_DEV_IN_ADC1);
  1750. }
  1751. if (codec_data->device_power[MT6391_DEV_IN_ADC2]) {
  1752. codec_data->device_power[MT6391_DEV_IN_ADC2] = false;
  1753. mt6391_turn_off_adc(codec_data, MT6391_DEV_IN_ADC2);
  1754. }
  1755. codec_data->device_mux[MT6391_MUX_IN_PREAMP_1] = 0;
  1756. codec_data->device_mux[MT6391_MUX_IN_PREAMP_2] = 0;
  1757. } else if (previous_type == CODEC_LOOPBACK_DMIC_TO_SPK ||
  1758. previous_type == CODEC_LOOPBACK_DMIC_TO_HP) {
  1759. if (codec_data->device_power[MT6391_DEV_IN_DIGITAL_MIC]) {
  1760. codec_data->device_power[MT6391_DEV_IN_DIGITAL_MIC] = false;
  1761. mt6391_turn_off_dmic(codec_data);
  1762. }
  1763. }
  1764. /* disable downlink */
  1765. if (previous_type == CODEC_LOOPBACK_AMIC_TO_SPK ||
  1766. previous_type == CODEC_LOOPBACK_HEADSET_MIC_TO_SPK ||
  1767. previous_type == CODEC_LOOPBACK_DMIC_TO_SPK) {
  1768. if (codec_data->device_power[MT6391_DEV_OUT_SPEAKERL]) {
  1769. codec_data->device_power[MT6391_DEV_OUT_SPEAKERL] = false;
  1770. mt6391_turn_off_speaker_amp(codec_data);
  1771. }
  1772. mt6391_ana_clk_off(codec_data);
  1773. } else if (previous_type == CODEC_LOOPBACK_AMIC_TO_HP ||
  1774. previous_type == CODEC_LOOPBACK_DMIC_TO_HP ||
  1775. previous_type == CODEC_LOOPBACK_HEADSET_MIC_TO_HP) {
  1776. if (codec_data->device_power[MT6391_DEV_OUT_HEADSETL]) {
  1777. codec_data->device_power[MT6391_DEV_OUT_HEADSETL] = false;
  1778. mt6391_turn_off_headphone_amp(codec_data);
  1779. }
  1780. mt6391_ana_clk_off(codec_data);
  1781. }
  1782. }
  1783. /* enable uplink */
  1784. if (set_value == CODEC_LOOPBACK_AMIC_TO_SPK ||
  1785. set_value == CODEC_LOOPBACK_AMIC_TO_HP ||
  1786. set_value == CODEC_LOOPBACK_HEADSET_MIC_TO_SPK ||
  1787. set_value == CODEC_LOOPBACK_HEADSET_MIC_TO_HP ||
  1788. set_value == CODEC_LOOPBACK_AMIC_TO_EXTDAC ||
  1789. set_value == CODEC_LOOPBACK_HEADSET_MIC_TO_EXTDAC) {
  1790. mt6391_ana_clk_on(codec_data);
  1791. codec_data->sample_rate[MT6391_ADDA_ADC] = 48000;
  1792. if (!codec_data->device_power[MT6391_DEV_IN_ADC1]) {
  1793. mt6391_turn_on_adc(codec_data, MT6391_DEV_IN_ADC1);
  1794. codec_data->device_power[MT6391_DEV_IN_ADC1] = true;
  1795. }
  1796. if (!codec_data->device_power[MT6391_DEV_IN_ADC2]) {
  1797. mt6391_turn_on_adc(codec_data, MT6391_DEV_IN_ADC2);
  1798. codec_data->device_power[MT6391_DEV_IN_ADC2] = true;
  1799. }
  1800. /* mux selection */
  1801. if (set_value == CODEC_LOOPBACK_HEADSET_MIC_TO_SPK ||
  1802. set_value == CODEC_LOOPBACK_HEADSET_MIC_TO_HP ||
  1803. set_value == CODEC_LOOPBACK_HEADSET_MIC_TO_EXTDAC) {
  1804. mt6391_set_mux(codec_data, MT6391_DEV_IN_PREAMP_L, MT6391_MUX_IN_MIC2);
  1805. mt6391_set_mux(codec_data, MT6391_DEV_IN_PREAMP_R, MT6391_MUX_IN_MIC2);
  1806. codec_data->device_mux[MT6391_MUX_IN_PREAMP_1] = 2;
  1807. codec_data->device_mux[MT6391_MUX_IN_PREAMP_2] = 2;
  1808. } else {
  1809. mt6391_set_mux(codec_data, MT6391_DEV_IN_PREAMP_L, MT6391_MUX_IN_MIC1);
  1810. mt6391_set_mux(codec_data, MT6391_DEV_IN_PREAMP_R, MT6391_MUX_IN_MIC3);
  1811. codec_data->device_mux[MT6391_MUX_IN_PREAMP_1] = 1;
  1812. codec_data->device_mux[MT6391_MUX_IN_PREAMP_2] = 3;
  1813. }
  1814. } else if (set_value == CODEC_LOOPBACK_DMIC_TO_SPK ||
  1815. set_value == CODEC_LOOPBACK_DMIC_TO_HP) {
  1816. mt6391_ana_clk_on(codec_data);
  1817. codec_data->sample_rate[MT6391_ADDA_ADC] = 32000;
  1818. if (!codec_data->device_power[MT6391_DEV_IN_DIGITAL_MIC]) {
  1819. mt6391_turn_on_dmic(codec_data);
  1820. codec_data->device_power[MT6391_DEV_IN_DIGITAL_MIC] = true;
  1821. }
  1822. }
  1823. /* enable downlink */
  1824. if (set_value == CODEC_LOOPBACK_AMIC_TO_SPK ||
  1825. set_value == CODEC_LOOPBACK_HEADSET_MIC_TO_SPK ||
  1826. set_value == CODEC_LOOPBACK_DMIC_TO_SPK) {
  1827. codec_data->sample_rate[MT6391_ADDA_DAC] =
  1828. (set_value == CODEC_LOOPBACK_DMIC_TO_SPK) ? 32000 : 48000;
  1829. if (!codec_data->device_power[MT6391_DEV_OUT_SPEAKERL]) {
  1830. mt6391_turn_on_speaker_amp(codec_data);
  1831. codec_data->device_power[MT6391_DEV_OUT_SPEAKERL] = true;
  1832. }
  1833. } else if (set_value == CODEC_LOOPBACK_AMIC_TO_HP ||
  1834. set_value == CODEC_LOOPBACK_DMIC_TO_HP ||
  1835. set_value == CODEC_LOOPBACK_HEADSET_MIC_TO_HP) {
  1836. codec_data->sample_rate[MT6391_ADDA_DAC] =
  1837. (set_value == CODEC_LOOPBACK_DMIC_TO_HP) ? 32000 : 48000;
  1838. if (!codec_data->device_power[MT6391_DEV_OUT_HEADSETL]) {
  1839. mt6391_turn_on_headphone_amp(codec_data);
  1840. codec_data->device_power[MT6391_DEV_OUT_HEADSETL] = true;
  1841. }
  1842. }
  1843. codec_data->codec_loopback_type = set_value;
  1844. return 0;
  1845. }
  1846. static int mt6391_dac_sgen_get(struct snd_kcontrol *kcontrol,
  1847. struct snd_ctl_elem_value *ucontrol)
  1848. {
  1849. struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
  1850. struct mt6391_priv *codec_data = snd_soc_component_get_drvdata(component);
  1851. ucontrol->value.integer.value[0] = codec_data->dac_sgen_switch;
  1852. return 0;
  1853. }
  1854. static int mt6391_dac_sgen_set(struct snd_kcontrol *kcontrol,
  1855. struct snd_ctl_elem_value *ucontrol)
  1856. {
  1857. struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
  1858. struct mt6391_priv *codec_data = snd_soc_component_get_drvdata(component);
  1859. if (codec_data->dac_sgen_switch == ucontrol->value.integer.value[0]) {
  1860. pr_debug("%s dummy operation for %u", __func__, codec_data->dac_sgen_switch);
  1861. return 0;
  1862. }
  1863. if (ucontrol->value.integer.value[0]) {
  1864. mt6391_set_reg(codec_data, MT6397_ANA_AFE_TOP_CON0, 0x1, 0x1);
  1865. /* mt6391_set_reg(codec_data, MT6397_AFE_SGEN_CFG0, 0x80, 0x80); */
  1866. mt6391_set_reg(codec_data, MT6397_AFE_SGEN_CFG0, 0x4480, 0xff80);
  1867. mt6391_set_reg(codec_data, MT6397_AFE_SGEN_CFG1, 0x0101, 0xffff);
  1868. } else {
  1869. mt6391_set_reg(codec_data, MT6397_ANA_AFE_TOP_CON0, 0x0, 0x1);
  1870. mt6391_set_reg(codec_data, MT6397_AFE_SGEN_CFG0, 0x0, 0x80);
  1871. }
  1872. codec_data->dac_sgen_switch = ucontrol->value.integer.value[0];
  1873. return 0;
  1874. }
  1875. static int mt6391_adc_sgen_get(struct snd_kcontrol *kcontrol,
  1876. struct snd_ctl_elem_value *ucontrol)
  1877. {
  1878. struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
  1879. struct mt6391_priv *codec_data = snd_soc_component_get_drvdata(component);
  1880. ucontrol->value.integer.value[0] = codec_data->adc_sgen_switch;
  1881. return 0;
  1882. }
  1883. static int mt6391_adc_sgen_set(struct snd_kcontrol *kcontrol,
  1884. struct snd_ctl_elem_value *ucontrol)
  1885. {
  1886. struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
  1887. struct mt6391_priv *codec_data = snd_soc_component_get_drvdata(component);
  1888. if (codec_data->adc_sgen_switch == ucontrol->value.integer.value[0]) {
  1889. pr_debug("%s dummy operation for %u", __func__, codec_data->adc_sgen_switch);
  1890. return 0;
  1891. }
  1892. if (ucontrol->value.integer.value[0]) {
  1893. mt6391_set_reg(codec_data, MT6397_ANA_AFE_TOP_CON0, 0x2, 0x2);
  1894. mt6391_set_reg(codec_data, MT6397_AFE_SGEN_CFG0, 0x80, 0x80);
  1895. mt6391_set_reg(codec_data, MT6397_AFE_SGEN_CFG1, 0x0101, 0xffff);
  1896. } else {
  1897. mt6391_set_reg(codec_data, MT6397_ANA_AFE_TOP_CON0, 0x0, 0x2);
  1898. mt6391_set_reg(codec_data, MT6397_AFE_SGEN_CFG0, 0x0, 0x80);
  1899. }
  1900. codec_data->adc_sgen_switch = ucontrol->value.integer.value[0];
  1901. return 0;
  1902. }
  1903. static int mt6391_dac_freq_get(struct snd_kcontrol *kcontrol,
  1904. struct snd_ctl_elem_value *ucontrol)
  1905. {
  1906. struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
  1907. struct mt6391_priv *codec_data = snd_soc_component_get_drvdata(component);
  1908. if (codec_data->sample_rate[MT6391_ADDA_DAC] == 48000)
  1909. ucontrol->value.integer.value[0] = DAC_FREQ_48000;
  1910. else if (codec_data->sample_rate[MT6391_ADDA_DAC] == 44100)
  1911. ucontrol->value.integer.value[0] = DAC_FREQ_44100;
  1912. else if (codec_data->sample_rate[MT6391_ADDA_DAC] == 32000)
  1913. ucontrol->value.integer.value[0] = DAC_FREQ_32000;
  1914. else if (codec_data->sample_rate[MT6391_ADDA_DAC] == 24000)
  1915. ucontrol->value.integer.value[0] = DAC_FREQ_24000;
  1916. else if (codec_data->sample_rate[MT6391_ADDA_DAC] == 22050)
  1917. ucontrol->value.integer.value[0] = DAC_FREQ_22050;
  1918. else if (codec_data->sample_rate[MT6391_ADDA_DAC] == 16000)
  1919. ucontrol->value.integer.value[0] = DAC_FREQ_16000;
  1920. else if (codec_data->sample_rate[MT6391_ADDA_DAC] == 12000)
  1921. ucontrol->value.integer.value[0] = DAC_FREQ_12000;
  1922. else if (codec_data->sample_rate[MT6391_ADDA_DAC] == 11025)
  1923. ucontrol->value.integer.value[0] = DAC_FREQ_11025;
  1924. else if (codec_data->sample_rate[MT6391_ADDA_DAC] == 8000)
  1925. ucontrol->value.integer.value[0] = DAC_FREQ_8000;
  1926. else
  1927. ucontrol->value.integer.value[0] = DAC_FREQ_48000;
  1928. return 0;
  1929. }
  1930. static int mt6391_dac_freq_set(struct snd_kcontrol *kcontrol,
  1931. struct snd_ctl_elem_value *ucontrol)
  1932. {
  1933. struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
  1934. struct mt6391_priv *codec_data = snd_soc_component_get_drvdata(component);
  1935. if (ucontrol->value.integer.value[0] == DAC_FREQ_48000)
  1936. codec_data->sample_rate[MT6391_ADDA_DAC] = 48000;
  1937. else if (ucontrol->value.integer.value[0] == DAC_FREQ_44100)
  1938. codec_data->sample_rate[MT6391_ADDA_DAC] = 44100;
  1939. else if (ucontrol->value.integer.value[0] == DAC_FREQ_32000)
  1940. codec_data->sample_rate[MT6391_ADDA_DAC] = 32000;
  1941. else if (ucontrol->value.integer.value[0] == DAC_FREQ_24000)
  1942. codec_data->sample_rate[MT6391_ADDA_DAC] = 24000;
  1943. else if (ucontrol->value.integer.value[0] == DAC_FREQ_22050)
  1944. codec_data->sample_rate[MT6391_ADDA_DAC] = 22050;
  1945. else if (ucontrol->value.integer.value[0] == DAC_FREQ_16000)
  1946. codec_data->sample_rate[MT6391_ADDA_DAC] = 16000;
  1947. else if (ucontrol->value.integer.value[0] == DAC_FREQ_12000)
  1948. codec_data->sample_rate[MT6391_ADDA_DAC] = 12000;
  1949. else if (ucontrol->value.integer.value[0] == DAC_FREQ_11025)
  1950. codec_data->sample_rate[MT6391_ADDA_DAC] = 11025;
  1951. else if (ucontrol->value.integer.value[0] == DAC_FREQ_8000)
  1952. codec_data->sample_rate[MT6391_ADDA_DAC] = 8000;
  1953. return 0;
  1954. }
  1955. static int mt6391_adc_freq_get(struct snd_kcontrol *kcontrol,
  1956. struct snd_ctl_elem_value *ucontrol)
  1957. {
  1958. struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
  1959. struct mt6391_priv *codec_data = snd_soc_component_get_drvdata(component);
  1960. if (codec_data->sample_rate[MT6391_ADDA_ADC] == 48000)
  1961. ucontrol->value.integer.value[0] = ADC_FREQ_48000;
  1962. else if (codec_data->sample_rate[MT6391_ADDA_ADC] == 32000)
  1963. ucontrol->value.integer.value[0] = ADC_FREQ_32000;
  1964. else if (codec_data->sample_rate[MT6391_ADDA_ADC] == 16000)
  1965. ucontrol->value.integer.value[0] = ADC_FREQ_16000;
  1966. else if (codec_data->sample_rate[MT6391_ADDA_ADC] == 8000)
  1967. ucontrol->value.integer.value[0] = ADC_FREQ_8000;
  1968. else
  1969. ucontrol->value.integer.value[0] = ADC_FREQ_48000;
  1970. return 0;
  1971. }
  1972. static int mt6391_adc_freq_set(struct snd_kcontrol *kcontrol,
  1973. struct snd_ctl_elem_value *ucontrol)
  1974. {
  1975. struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
  1976. struct mt6391_priv *codec_data = snd_soc_component_get_drvdata(component);
  1977. if (ucontrol->value.integer.value[0] == ADC_FREQ_48000)
  1978. codec_data->sample_rate[MT6391_ADDA_ADC] = 48000;
  1979. else if (ucontrol->value.integer.value[0] == ADC_FREQ_32000)
  1980. codec_data->sample_rate[MT6391_ADDA_ADC] = 32000;
  1981. else if (ucontrol->value.integer.value[0] == ADC_FREQ_16000)
  1982. codec_data->sample_rate[MT6391_ADDA_ADC] = 16000;
  1983. else if (ucontrol->value.integer.value[0] == ADC_FREQ_8000)
  1984. codec_data->sample_rate[MT6391_ADDA_ADC] = 8000;
  1985. return 0;
  1986. }
  1987. /* snd kcontrol function definition */
  1988. static const char *const mt6391_amp_func[] = { "Off", "On" };
  1989. static const char *const mt6391_headset_gain[] = {
  1990. "8Db", "7Db", "6Db", "5Db", "4Db", "3Db", "2Db", "1Db", "0Db", "-1Db",
  1991. "-2Db", "-3Db", "-4Db", "RES1", "RES2", "-40Db"
  1992. };
  1993. static const char *const mt6391_handset_gain[] = {
  1994. "8Db", "7Db", "6Db", "5Db", "4Db", "3Db", "2Db", "1Db", "0Db", "-1Db",
  1995. "-2Db", "-3Db", "-4Db", "RES1", "RES2", "-40Db"
  1996. };
  1997. static const char *const mt6391_speaker_gain[] = {
  1998. "Mute", "0Db", "4Db", "5Db", "6Db", "7Db", "8Db", "9Db", "10Db",
  1999. "11Db", "12Db", "13Db", "14Db", "15Db", "16Db", "17Db"
  2000. };
  2001. static const char *const mt6391_speaker_select_func[] = { "Stereo", "MonoLeft", "MonoRight" };
  2002. static const char *const mt6391_speaker_oc_func[] = { "NoOverCurrent", "OverCurrent" };
  2003. static const char *const mt6391_dac_newif_sck_func[] = { "NotInverse", "Inverse" };
  2004. static const char *const mt6391_dmic_func[] = { "Off", "On" };
  2005. static const char *const mt6391_adc_func[] = { "Off", "On" };
  2006. static const char *const mt6391_preamp_mux_func[] = { "OPEN", "AIN1", "AIN2", "AIN3" };
  2007. static const char *const mt6391_preamp_gain[] = { "2Db", "8Db", "14Db", "20Db", "26Db", "32Db" };
  2008. static const char *const mt6391_codec_loopback_func[] = {
  2009. ENUM_TO_STR(CODEC_LOOPBACK_NONE),
  2010. ENUM_TO_STR(CODEC_LOOPBACK_AMIC_TO_SPK),
  2011. ENUM_TO_STR(CODEC_LOOPBACK_AMIC_TO_HP),
  2012. ENUM_TO_STR(CODEC_LOOPBACK_DMIC_TO_SPK),
  2013. ENUM_TO_STR(CODEC_LOOPBACK_DMIC_TO_HP),
  2014. ENUM_TO_STR(CODEC_LOOPBACK_HEADSET_MIC_TO_SPK),
  2015. ENUM_TO_STR(CODEC_LOOPBACK_HEADSET_MIC_TO_HP),
  2016. ENUM_TO_STR(CODEC_LOOPBACK_AMIC_TO_EXTDAC),
  2017. ENUM_TO_STR(CODEC_LOOPBACK_HEADSET_MIC_TO_EXTDAC),
  2018. };
  2019. static const char *const mt6391_sgen_func[] = { "Off", "On" };
  2020. static const char *const mt6391_dac_freq_func[] = {
  2021. ENUM_TO_STR(DAC_FREQ_8000),
  2022. ENUM_TO_STR(DAC_FREQ_11025),
  2023. ENUM_TO_STR(DAC_FREQ_12000),
  2024. ENUM_TO_STR(DAC_FREQ_16000),
  2025. ENUM_TO_STR(DAC_FREQ_22050),
  2026. ENUM_TO_STR(DAC_FREQ_24000),
  2027. ENUM_TO_STR(DAC_FREQ_32000),
  2028. ENUM_TO_STR(DAC_FREQ_44100),
  2029. ENUM_TO_STR(DAC_FREQ_48000),
  2030. };
  2031. static const char *const mt6391_adc_freq_func[] = {
  2032. ENUM_TO_STR(ADC_FREQ_8000),
  2033. ENUM_TO_STR(ADC_FREQ_16000),
  2034. ENUM_TO_STR(ADC_FREQ_32000),
  2035. ENUM_TO_STR(ADC_FREQ_48000),
  2036. };
  2037. /* soc_enum list */
  2038. static const struct soc_enum mt6391_soc_enums[] = {
  2039. /* downlink */
  2040. [ENUM_AUDIO_AMP] = SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(mt6391_amp_func),
  2041. mt6391_amp_func),
  2042. [ENUM_VOICE_AMP] = SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(mt6391_amp_func),
  2043. mt6391_amp_func),
  2044. [ENUM_SPK_AMP] = SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(mt6391_amp_func),
  2045. mt6391_amp_func),
  2046. [ENUM_HS_SPK_AMP] = SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(mt6391_amp_func),
  2047. mt6391_amp_func),
  2048. [ENUM_HEADSETL_GAIN] = SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(mt6391_headset_gain),
  2049. mt6391_headset_gain),
  2050. [ENUM_HEADSETR_GAIN] = SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(mt6391_headset_gain),
  2051. mt6391_headset_gain),
  2052. [ENUM_HANDSET_GAIN] = SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(mt6391_handset_gain),
  2053. mt6391_handset_gain),
  2054. [ENUM_SPKL_GAIN] = SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(mt6391_speaker_gain),
  2055. mt6391_speaker_gain),
  2056. [ENUM_SPKR_GAIN] = SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(mt6391_speaker_gain),
  2057. mt6391_speaker_gain),
  2058. [ENUM_SPK_SEL] = SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(mt6391_speaker_select_func),
  2059. mt6391_speaker_select_func),
  2060. [ENUM_SPK_OC_FLAG] = SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(mt6391_speaker_oc_func),
  2061. mt6391_speaker_oc_func),
  2062. [ENUM_DAC_SCK] = SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(mt6391_dac_newif_sck_func),
  2063. mt6391_dac_newif_sck_func),
  2064. /* uplink */
  2065. [ENUM_DMIC_SWITCH] = SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(mt6391_dmic_func),
  2066. mt6391_dmic_func),
  2067. [ENUM_ADC1_SWITCH] = SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(mt6391_adc_func),
  2068. mt6391_adc_func),
  2069. [ENUM_ADC2_SWITCH] = SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(mt6391_adc_func),
  2070. mt6391_adc_func),
  2071. [ENUM_PREAMP1_MUX] = SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(mt6391_preamp_mux_func),
  2072. mt6391_preamp_mux_func),
  2073. [ENUM_PREAMP2_MUX] = SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(mt6391_preamp_mux_func),
  2074. mt6391_preamp_mux_func),
  2075. [ENUM_PREAMP1_GAIN] = SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(mt6391_preamp_gain),
  2076. mt6391_preamp_gain),
  2077. [ENUM_PREAMP2_GAIN] = SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(mt6391_preamp_gain),
  2078. mt6391_preamp_gain),
  2079. /* factory */
  2080. [ENUM_LOOPBACK_SEL] = SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(mt6391_codec_loopback_func),
  2081. mt6391_codec_loopback_func),
  2082. [ENUM_DAC_SGEN] = SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(mt6391_sgen_func),
  2083. mt6391_sgen_func),
  2084. [ENUM_ADC_SGEN] = SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(mt6391_sgen_func),
  2085. mt6391_sgen_func),
  2086. [ENUM_DAC_FREQ] = SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(mt6391_dac_freq_func),
  2087. mt6391_dac_freq_func),
  2088. [ENUM_ADC_FREQ] = SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(mt6391_adc_freq_func),
  2089. mt6391_adc_freq_func),
  2090. };
  2091. static const struct snd_kcontrol_new mt6391_dl_codec_controls[] = {
  2092. SOC_ENUM_EXT("Audio_Amp_Switch", mt6391_soc_enums[ENUM_AUDIO_AMP],
  2093. mt6391_audio_amp_get, mt6391_audio_amp_set),
  2094. SOC_ENUM_EXT("Voice_Amp_Switch", mt6391_soc_enums[ENUM_VOICE_AMP],
  2095. mt6391_voice_amp_get, mt6391_voice_amp_set),
  2096. SOC_ENUM_EXT("Speaker_Amp_Switch", mt6391_soc_enums[ENUM_SPK_AMP],
  2097. mt6391_speaker_amp_get, mt6391_speaker_amp_set),
  2098. SOC_ENUM_EXT("Headset_Speaker_Amp_Switch", mt6391_soc_enums[ENUM_HS_SPK_AMP],
  2099. mt6391_headset_speaker_amp_get, mt6391_headset_speaker_amp_set),
  2100. SOC_ENUM_EXT("Headset_PGAL_GAIN", mt6391_soc_enums[ENUM_HEADSETL_GAIN],
  2101. mt6391_headset_pgal_get, mt6391_headset_pgal_set),
  2102. SOC_ENUM_EXT("Headset_PGAR_GAIN", mt6391_soc_enums[ENUM_HEADSETR_GAIN],
  2103. mt6391_headset_pgar_get, mt6391_headset_pgar_set),
  2104. SOC_ENUM_EXT("Hanset_PGA_GAIN", mt6391_soc_enums[ENUM_HANDSET_GAIN],
  2105. mt6391_handset_pga_get, mt6391_handset_pga_set),
  2106. SOC_ENUM_EXT("Speaker_PGAL_GAIN", mt6391_soc_enums[ENUM_SPKL_GAIN],
  2107. mt6391_speaker_pgal_get, mt6391_speaker_pgal_set),
  2108. SOC_ENUM_EXT("Speaker_PGAR_GAIN", mt6391_soc_enums[ENUM_SPKR_GAIN],
  2109. mt6391_speaker_pgar_get, mt6391_speaker_pgar_set),
  2110. SOC_ENUM_EXT("Speaker_Channel_Select", mt6391_soc_enums[ENUM_SPK_SEL],
  2111. mt6391_speaker_channel_get, mt6391_speaker_channel_set),
  2112. SOC_ENUM_EXT("Speaker_OC_Flag", mt6391_soc_enums[ENUM_SPK_OC_FLAG],
  2113. mt6391_speaker_oc_flag_get, mt6391_speaker_oc_flag_set),
  2114. SOC_ENUM_EXT("DAC_Newif_Sck_Switch", mt6391_soc_enums[ENUM_DAC_SCK],
  2115. mt6391_dac_newif_sck_get, mt6391_dac_newif_sck_set),
  2116. };
  2117. static const struct snd_kcontrol_new mt6391_ul_codec_controls[] = {
  2118. SOC_ENUM_EXT("Audio_Digital_Mic_Switch", mt6391_soc_enums[ENUM_DMIC_SWITCH],
  2119. mt6391_dmic_get, mt6391_dmic_set),
  2120. SOC_ENUM_EXT("Audio_ADC_1_Switch", mt6391_soc_enums[ENUM_ADC1_SWITCH],
  2121. mt6391_adc1_get, mt6391_adc1_set),
  2122. SOC_ENUM_EXT("Audio_ADC_2_Switch", mt6391_soc_enums[ENUM_ADC2_SWITCH],
  2123. mt6391_adc2_get, mt6391_adc2_set),
  2124. SOC_ENUM_EXT("Audio_Preamp1_Switch", mt6391_soc_enums[ENUM_PREAMP1_MUX],
  2125. mt6391_preamp1_mux_get, mt6391_preamp1_mux_set),
  2126. SOC_ENUM_EXT("Audio_Preamp2_Switch", mt6391_soc_enums[ENUM_PREAMP2_MUX],
  2127. mt6391_preamp2_mux_get, mt6391_preamp2_mux_set),
  2128. SOC_ENUM_EXT("Audio_PGA1_Setting", mt6391_soc_enums[ENUM_PREAMP1_GAIN],
  2129. mt6391_preamp1_gain_get, mt6391_preamp1_gain_set),
  2130. SOC_ENUM_EXT("Audio_PGA2_Setting", mt6391_soc_enums[ENUM_PREAMP2_GAIN],
  2131. mt6391_preamp2_gain_get, mt6391_preamp2_gain_set),
  2132. };
  2133. static const struct snd_kcontrol_new mt6391_factory_controls[] = {
  2134. SOC_ENUM_EXT("Codec_Loopback_Select", mt6391_soc_enums[ENUM_LOOPBACK_SEL],
  2135. mt6391_loopback_get, mt6391_loopback_set),
  2136. SOC_ENUM_EXT("DAC_SGen_Switch", mt6391_soc_enums[ENUM_DAC_SGEN],
  2137. mt6391_dac_sgen_get, mt6391_dac_sgen_set),
  2138. SOC_ENUM_EXT("ADC_SGen_Switch", mt6391_soc_enums[ENUM_ADC_SGEN],
  2139. mt6391_adc_sgen_get, mt6391_adc_sgen_set),
  2140. SOC_ENUM_EXT("DAC_Freq_Switch", mt6391_soc_enums[ENUM_DAC_FREQ],
  2141. mt6391_dac_freq_get, mt6391_dac_freq_set),
  2142. SOC_ENUM_EXT("ADC_Freq_Switch", mt6391_soc_enums[ENUM_ADC_FREQ],
  2143. mt6391_adc_freq_get, mt6391_adc_freq_set),
  2144. };
  2145. #ifdef CONFIG_DEBUG_FS
  2146. struct mt6391_reg_attr {
  2147. uint32_t offset;
  2148. char *name;
  2149. };
  2150. #define DUMP_REG_ENTRY(reg) {reg, #reg}
  2151. static const struct mt6391_reg_attr dump_reg_list[] = {
  2152. DUMP_REG_ENTRY(MT6397_AFE_UL_DL_CON0),
  2153. DUMP_REG_ENTRY(MT6397_AFE_DL_SRC2_CON0_H),
  2154. DUMP_REG_ENTRY(MT6397_AFE_DL_SRC2_CON0_L),
  2155. DUMP_REG_ENTRY(MT6397_AFE_DL_SDM_CON0),
  2156. DUMP_REG_ENTRY(MT6397_AFE_DL_SDM_CON1),
  2157. DUMP_REG_ENTRY(MT6397_AFE_UL_SRC_CON0_H),
  2158. DUMP_REG_ENTRY(MT6397_AFE_UL_SRC_CON0_L),
  2159. DUMP_REG_ENTRY(MT6397_AFE_UL_SRC_CON1_H),
  2160. DUMP_REG_ENTRY(MT6397_AFE_UL_SRC_CON1_L),
  2161. DUMP_REG_ENTRY(MT6397_ANA_AFE_TOP_CON0),
  2162. DUMP_REG_ENTRY(MT6397_AFUNC_AUD_CON0),
  2163. DUMP_REG_ENTRY(MT6397_AFUNC_AUD_CON1),
  2164. DUMP_REG_ENTRY(MT6397_AFUNC_AUD_CON2),
  2165. DUMP_REG_ENTRY(MT6397_AFUNC_AUD_CON3),
  2166. DUMP_REG_ENTRY(MT6397_AFUNC_AUD_CON4),
  2167. DUMP_REG_ENTRY(MT6397_AFUNC_AUD_MON0),
  2168. DUMP_REG_ENTRY(MT6397_AFUNC_AUD_MON1),
  2169. DUMP_REG_ENTRY(MT6397_AUDRC_TUNE_MON0),
  2170. DUMP_REG_ENTRY(MT6397_AFE_UP8X_FIFO_CFG0),
  2171. DUMP_REG_ENTRY(MT6397_AFE_UP8X_FIFO_LOG_MON0),
  2172. DUMP_REG_ENTRY(MT6397_AFE_UP8X_FIFO_LOG_MON1),
  2173. DUMP_REG_ENTRY(MT6397_AFE_DL_DC_COMP_CFG0),
  2174. DUMP_REG_ENTRY(MT6397_AFE_DL_DC_COMP_CFG1),
  2175. DUMP_REG_ENTRY(MT6397_AFE_DL_DC_COMP_CFG2),
  2176. DUMP_REG_ENTRY(MT6397_AFE_PMIC_NEWIF_CFG0),
  2177. DUMP_REG_ENTRY(MT6397_AFE_PMIC_NEWIF_CFG1),
  2178. DUMP_REG_ENTRY(MT6397_AFE_PMIC_NEWIF_CFG2),
  2179. DUMP_REG_ENTRY(MT6397_AFE_PMIC_NEWIF_CFG3),
  2180. DUMP_REG_ENTRY(MT6397_AFE_SGEN_CFG0),
  2181. DUMP_REG_ENTRY(MT6397_AFE_SGEN_CFG1),
  2182. DUMP_REG_ENTRY(MT6397_TOP_CKPDN),
  2183. DUMP_REG_ENTRY(MT6397_TOP_CKPDN2),
  2184. DUMP_REG_ENTRY(MT6397_TOP_CKCON1),
  2185. DUMP_REG_ENTRY(MT6397_TOP_CKCON3),
  2186. DUMP_REG_ENTRY(MT6397_SPK_CON0),
  2187. DUMP_REG_ENTRY(MT6397_SPK_CON1),
  2188. DUMP_REG_ENTRY(MT6397_SPK_CON2),
  2189. DUMP_REG_ENTRY(MT6397_SPK_CON3),
  2190. DUMP_REG_ENTRY(MT6397_SPK_CON4),
  2191. DUMP_REG_ENTRY(MT6397_SPK_CON5),
  2192. DUMP_REG_ENTRY(MT6397_SPK_CON6),
  2193. DUMP_REG_ENTRY(MT6397_SPK_CON7),
  2194. DUMP_REG_ENTRY(MT6397_SPK_CON8),
  2195. DUMP_REG_ENTRY(MT6397_SPK_CON9),
  2196. DUMP_REG_ENTRY(MT6397_SPK_CON10),
  2197. DUMP_REG_ENTRY(MT6397_SPK_CON11),
  2198. DUMP_REG_ENTRY(MT6397_AUDDAC_CON0),
  2199. DUMP_REG_ENTRY(MT6397_AUDBUF_CFG0),
  2200. DUMP_REG_ENTRY(MT6397_AUDBUF_CFG1),
  2201. DUMP_REG_ENTRY(MT6397_AUDBUF_CFG2),
  2202. DUMP_REG_ENTRY(MT6397_AUDBUF_CFG3),
  2203. DUMP_REG_ENTRY(MT6397_AUDBUF_CFG4),
  2204. DUMP_REG_ENTRY(MT6397_IBIASDIST_CFG0),
  2205. DUMP_REG_ENTRY(MT6397_AUDACCDEPOP_CFG0),
  2206. DUMP_REG_ENTRY(MT6397_AUD_IV_CFG0),
  2207. DUMP_REG_ENTRY(MT6397_AUDCLKGEN_CFG0),
  2208. DUMP_REG_ENTRY(MT6397_AUDLDO_CFG0),
  2209. DUMP_REG_ENTRY(MT6397_AUDLDO_CFG1),
  2210. DUMP_REG_ENTRY(MT6397_AUDNVREGGLB_CFG0),
  2211. DUMP_REG_ENTRY(MT6397_AUD_NCP0),
  2212. DUMP_REG_ENTRY(MT6397_AUDPREAMP_CON0),
  2213. DUMP_REG_ENTRY(MT6397_AUDADC_CON0),
  2214. DUMP_REG_ENTRY(MT6397_AUDADC_CON1),
  2215. DUMP_REG_ENTRY(MT6397_AUDADC_CON2),
  2216. DUMP_REG_ENTRY(MT6397_AUDADC_CON3),
  2217. DUMP_REG_ENTRY(MT6397_AUDADC_CON4),
  2218. DUMP_REG_ENTRY(MT6397_AUDADC_CON5),
  2219. DUMP_REG_ENTRY(MT6397_AUDADC_CON6),
  2220. DUMP_REG_ENTRY(MT6397_AUDDIGMI_CON0),
  2221. DUMP_REG_ENTRY(MT6397_AUDLSBUF_CON0),
  2222. DUMP_REG_ENTRY(MT6397_AUDLSBUF_CON1),
  2223. DUMP_REG_ENTRY(MT6397_AUDENCSPARE_CON0),
  2224. DUMP_REG_ENTRY(MT6397_AUDENCCLKSQ_CON0),
  2225. DUMP_REG_ENTRY(MT6397_AUDPREAMPGAIN_CON0),
  2226. DUMP_REG_ENTRY(MT6397_ZCD_CON0),
  2227. DUMP_REG_ENTRY(MT6397_ZCD_CON1),
  2228. DUMP_REG_ENTRY(MT6397_ZCD_CON2),
  2229. DUMP_REG_ENTRY(MT6397_ZCD_CON3),
  2230. DUMP_REG_ENTRY(MT6397_ZCD_CON4),
  2231. DUMP_REG_ENTRY(MT6397_ZCD_CON5),
  2232. DUMP_REG_ENTRY(MT6397_NCP_CLKDIV_CON0),
  2233. DUMP_REG_ENTRY(MT6397_NCP_CLKDIV_CON1),
  2234. };
  2235. static ssize_t mt6391_debug_read(struct file *file, char __user *user_buf,
  2236. size_t count, loff_t *pos)
  2237. {
  2238. struct mt6391_priv *codec_data = file->private_data;
  2239. ssize_t ret, i;
  2240. char *buf;
  2241. int n = 0;
  2242. if (*pos < 0 || !count)
  2243. return -EINVAL;
  2244. buf = kmalloc(count, GFP_KERNEL);
  2245. if (!buf)
  2246. return -ENOMEM;
  2247. for (i = 0; i < ARRAY_SIZE(dump_reg_list); i++) {
  2248. n += scnprintf(buf + n, count - n, "%s = 0x%x\n",
  2249. dump_reg_list[i].name,
  2250. mt6391_get_reg(codec_data, dump_reg_list[i].offset));
  2251. }
  2252. ret = simple_read_from_buffer(user_buf, count, pos, buf, n);
  2253. kfree(buf);
  2254. return ret;
  2255. }
  2256. static const struct file_operations mt6391_debug_ops = {
  2257. .open = simple_open,
  2258. .read = mt6391_debug_read,
  2259. .llseek = default_llseek,
  2260. };
  2261. #endif
  2262. static int mt6391_codec_startup(struct snd_pcm_substream *substream,
  2263. struct snd_soc_dai *codec_dai)
  2264. {
  2265. if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
  2266. pr_debug("%s SNDRV_PCM_STREAM_CAPTURE\n", __func__);
  2267. else if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
  2268. pr_debug("%s SNDRV_PCM_STREAM_PLAYBACK\n", __func__);
  2269. return 0;
  2270. }
  2271. static int mt6391_codec_prepare(struct snd_pcm_substream *substream,
  2272. struct snd_soc_dai *codec_dai)
  2273. {
  2274. struct mt6391_priv *codec_data = snd_soc_codec_get_drvdata(codec_dai->codec);
  2275. struct snd_pcm_runtime *runtime = substream->runtime;
  2276. if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) {
  2277. pr_debug("%s capture rate = %d\n", __func__, runtime->rate);
  2278. codec_data->sample_rate[MT6391_ADDA_ADC] = runtime->rate;
  2279. } else if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
  2280. pr_debug("%s playback rate = %d\n", __func__, runtime->rate);
  2281. codec_data->sample_rate[MT6391_ADDA_DAC] = runtime->rate;
  2282. }
  2283. return 0;
  2284. }
  2285. static int mt6391_codec_trigger(struct snd_pcm_substream *substream, int command,
  2286. struct snd_soc_dai *codec_dai)
  2287. {
  2288. switch (command) {
  2289. case SNDRV_PCM_TRIGGER_START:
  2290. case SNDRV_PCM_TRIGGER_RESUME:
  2291. case SNDRV_PCM_TRIGGER_STOP:
  2292. case SNDRV_PCM_TRIGGER_SUSPEND:
  2293. break;
  2294. }
  2295. pr_debug("%s command = %d\n ", __func__, command);
  2296. return 0;
  2297. }
  2298. static const struct snd_soc_dai_ops mt6391_aif1_dai_ops = {
  2299. .startup = mt6391_codec_startup,
  2300. .prepare = mt6391_codec_prepare,
  2301. .trigger = mt6391_codec_trigger,
  2302. };
  2303. static struct snd_soc_dai_driver mt6391_codec_dai_drvs[] = {
  2304. {
  2305. .name = "mt6397-codec-tx-dai",
  2306. .ops = &mt6391_aif1_dai_ops,
  2307. .playback = {
  2308. .stream_name = "Playback",
  2309. .channels_min = 1,
  2310. .channels_max = 2,
  2311. .rates = SNDRV_PCM_RATE_8000_48000,
  2312. .formats = SNDRV_PCM_FMTBIT_S16_LE,
  2313. },
  2314. },
  2315. {
  2316. .name = "mt6397-codec-rx-dai",
  2317. .ops = &mt6391_aif1_dai_ops,
  2318. .capture = {
  2319. .stream_name = "Capture",
  2320. .channels_min = 1,
  2321. .channels_max = 2,
  2322. .rates = SNDRV_PCM_RATE_8000_48000,
  2323. .formats = SNDRV_PCM_FMTBIT_S16_LE,
  2324. },
  2325. },
  2326. };
  2327. static void mt6391_codec_init_reg(struct mt6391_priv *codec_data)
  2328. {
  2329. pr_debug("%s\n", __func__);
  2330. mt6391_set_reg(codec_data, MT6397_AFUNC_AUD_CON2, 0x0080, 0x0080);
  2331. mt6391_set_reg(codec_data, MT6397_ZCD_CON2, 0x0c0c, 0xffff);
  2332. mt6391_set_reg(codec_data, MT6397_AUDBUF_CFG0, 0x0000, 0x1fe7);
  2333. mt6391_set_reg(codec_data, MT6397_IBIASDIST_CFG0, 0x1552, 0xffff); /* RG DEV ck off; */
  2334. mt6391_set_reg(codec_data, MT6397_AUDDAC_CON0, 0x0000, 0xffff); /* NCP off */
  2335. mt6391_set_reg(codec_data, MT6397_AUDCLKGEN_CFG0, 0x0000, 0x0001);
  2336. mt6391_set_reg(codec_data, MT6397_AUDNVREGGLB_CFG0, 0x0006, 0xffff); /* need check */
  2337. mt6391_set_reg(codec_data, MT6397_NCP_CLKDIV_CON1, 0x0001, 0xffff); /* fix me */
  2338. mt6391_set_reg(codec_data, MT6397_AUD_NCP0, 0x0000, 0x6000);
  2339. mt6391_set_reg(codec_data, MT6397_AUDLDO_CFG0, 0x0192, 0xffff);
  2340. mt6391_set_reg(codec_data, MT6397_AFUNC_AUD_CON2, 0x0000, 0x0080);
  2341. /* ZCD setting gain step gain and enable */
  2342. mt6391_set_reg(codec_data, MT6397_ZCD_CON0, 0x0101, 0xffff);
  2343. /* sck inverse */
  2344. mt6391_set_reg(codec_data, MT6397_AFE_PMIC_NEWIF_CFG2, 1 << 15, 1 << 15);
  2345. /* default preamp mux */
  2346. mt6391_set_mux(codec_data, MT6391_DEV_IN_PREAMP_L, MT6391_MUX_IN_MIC1);
  2347. mt6391_set_mux(codec_data, MT6391_DEV_IN_PREAMP_R, MT6391_MUX_IN_MIC2);
  2348. }
  2349. static int mt6391_codec_probe(struct snd_soc_codec *codec)
  2350. {
  2351. struct mt6391_priv *codec_data = snd_soc_codec_get_drvdata(codec);
  2352. pr_info("%s\n", __func__);
  2353. codec_data->codec = codec;
  2354. #if defined(USE_MT6397_REGMAP)
  2355. mt6391_set_reg(codec_data, MT6397_TOP_CKCON1, 0x0010, 0x0010);
  2356. #elif defined(USE_PMIC_WRAP_DRIVER)
  2357. upmu_set_rg_clksq_en(1);
  2358. #endif
  2359. mt6391_control_top_clk(codec_data, 0x0607, true);
  2360. mt6391_codec_init_reg(codec_data);
  2361. mt6391_get_hp_trim_offset(codec_data);
  2362. mt6391_spk_auto_trim_offset(codec_data);
  2363. #if defined(USE_MT6397_REGMAP)
  2364. mt6391_set_reg(codec_data, MT6397_TOP_CKCON1, 0x0000, 0x0010);
  2365. #elif defined(USE_PMIC_WRAP_DRIVER)
  2366. upmu_set_rg_clksq_en(0);
  2367. #endif
  2368. mt6391_control_top_clk(codec_data, 0x0607, false);
  2369. snd_soc_add_codec_controls(codec, mt6391_dl_codec_controls,
  2370. ARRAY_SIZE(mt6391_dl_codec_controls));
  2371. snd_soc_add_codec_controls(codec, mt6391_ul_codec_controls,
  2372. ARRAY_SIZE(mt6391_ul_codec_controls));
  2373. snd_soc_add_codec_controls(codec, mt6391_factory_controls,
  2374. ARRAY_SIZE(mt6391_factory_controls));
  2375. #ifdef CONFIG_DEBUG_FS
  2376. codec_data->debugfs = debugfs_create_file("mt6391reg", S_IFREG | S_IRUGO,
  2377. NULL, codec_data, &mt6391_debug_ops);
  2378. #endif
  2379. return 0;
  2380. }
  2381. static int mt6391_codec_remove(struct snd_soc_codec *codec)
  2382. {
  2383. #ifdef CONFIG_DEBUG_FS
  2384. struct mt6391_priv *codec_data = snd_soc_codec_get_drvdata(codec);
  2385. debugfs_remove(codec_data->debugfs);
  2386. #endif
  2387. return 0;
  2388. }
  2389. static int mt6391_codec_suspend(struct snd_soc_codec *codec)
  2390. {
  2391. struct mt6391_priv *codec_data = snd_soc_codec_get_drvdata(codec);
  2392. mt6391_suspend_clk_off(codec_data);
  2393. return 0;
  2394. }
  2395. static int mt6391_codec_resume(struct snd_soc_codec *codec)
  2396. {
  2397. struct mt6391_priv *codec_data = snd_soc_codec_get_drvdata(codec);
  2398. mt6391_suspend_clk_on(codec_data);
  2399. return 0;
  2400. }
  2401. #if defined(USE_MT6397_REGMAP)
  2402. static struct regmap *mt6391_codec_get_regmap(struct device *dev)
  2403. {
  2404. struct mt6397_chip *mt6397;
  2405. mt6397 = dev_get_drvdata(dev->parent);
  2406. return mt6397->regmap;
  2407. }
  2408. #else
  2409. static unsigned int mt6391_read(struct snd_soc_codec *codec, unsigned int reg)
  2410. {
  2411. struct mt6391_priv *codec_data = snd_soc_codec_get_drvdata(codec);
  2412. unsigned int val = mt6391_get_reg(codec_data, reg);
  2413. pr_debug("%s reg = 0x%x val = 0x%x", __func__, reg, val);
  2414. return val;
  2415. }
  2416. static int mt6391_write(struct snd_soc_codec *codec, unsigned int reg, unsigned int value)
  2417. {
  2418. struct mt6391_priv *codec_data = snd_soc_codec_get_drvdata(codec);
  2419. pr_debug("%s reg = 0x%x value= 0x%x\n", __func__, reg, value);
  2420. mt6391_set_reg(codec_data, reg, value, 0xffffffff);
  2421. return 0;
  2422. }
  2423. #endif
  2424. static struct snd_soc_codec_driver mt6391_codec_driver = {
  2425. .probe = mt6391_codec_probe,
  2426. .remove = mt6391_codec_remove,
  2427. .suspend = mt6391_codec_suspend,
  2428. .resume = mt6391_codec_resume,
  2429. #if defined(USE_MT6397_REGMAP)
  2430. .get_regmap = mt6391_codec_get_regmap,
  2431. #else
  2432. .read = mt6391_read,
  2433. .write = mt6391_write,
  2434. #endif
  2435. };
  2436. static int mt6391_dev_probe(struct platform_device *pdev)
  2437. {
  2438. struct device *dev = &pdev->dev;
  2439. struct mt6391_priv *codec_data;
  2440. int ret;
  2441. pr_notice("%s dev name %s\n", __func__, dev_name(dev));
  2442. if (dev->of_node) {
  2443. dev_set_name(dev, "%s", MT6397_CODEC_NAME);
  2444. pr_notice("%s set dev name %s\n", __func__, dev_name(dev));
  2445. }
  2446. codec_data = devm_kzalloc(dev, sizeof(struct mt6391_priv), GFP_KERNEL);
  2447. if (unlikely(!codec_data)) {
  2448. pr_err("%s failed to allocate private data\n", __func__);
  2449. return -ENOMEM;
  2450. }
  2451. mutex_init(&codec_data->ctrl_mutex);
  2452. mutex_init(&codec_data->clk_mutex);
  2453. codec_data->sample_rate[MT6391_ADDA_DAC] = 44100;
  2454. codec_data->sample_rate[MT6391_ADDA_ADC] = 32000;
  2455. ret = of_property_read_u32(dev->of_node, "mediatek,speaker-mode",
  2456. &codec_data->speaker_mode);
  2457. if (ret) {
  2458. pr_warn("%s fail to read speaker-mode in node %s\n", __func__,
  2459. dev->of_node->full_name);
  2460. codec_data->speaker_mode = MT6391_CLASS_D;
  2461. } else if (codec_data->speaker_mode != MT6391_CLASS_D &&
  2462. codec_data->speaker_mode != MT6391_CLASS_AB) {
  2463. codec_data->speaker_mode = MT6391_CLASS_D;
  2464. }
  2465. ret = of_property_read_u32(dev->of_node, "mediatek,adc-warmup-time-us",
  2466. &codec_data->adc_warmup_time_us);
  2467. if (ret)
  2468. codec_data->adc_warmup_time_us = 0;
  2469. ret = of_property_read_u32(dev->of_node, "mediatek,dmic-warmup-time-us",
  2470. &codec_data->dmic_warmup_time_us);
  2471. if (ret)
  2472. codec_data->dmic_warmup_time_us = 0;
  2473. dev_set_drvdata(dev, codec_data);
  2474. return snd_soc_register_codec(dev, &mt6391_codec_driver, mt6391_codec_dai_drvs,
  2475. ARRAY_SIZE(mt6391_codec_dai_drvs));
  2476. }
  2477. static int mt6391_dev_remove(struct platform_device *pdev)
  2478. {
  2479. pr_debug("%s\n", __func__);
  2480. snd_soc_unregister_codec(&pdev->dev);
  2481. return 0;
  2482. }
  2483. static const struct of_device_id mt6391_codec_dt_match[] = {
  2484. {.compatible = "mediatek," MT6397_CODEC_NAME,},
  2485. {}
  2486. };
  2487. MODULE_DEVICE_TABLE(of, mt6391_codec_dt_match);
  2488. static struct platform_driver mt6391_codec_device_driver = {
  2489. .driver = {
  2490. .name = MT6397_CODEC_NAME,
  2491. .owner = THIS_MODULE,
  2492. .of_match_table = mt6391_codec_dt_match,
  2493. },
  2494. .probe = mt6391_dev_probe,
  2495. .remove = mt6391_dev_remove,
  2496. };
  2497. module_platform_driver(mt6391_codec_device_driver);
  2498. /* Module information */
  2499. MODULE_DESCRIPTION("MT6391 codec driver");
  2500. MODULE_LICENSE("GPL v2");