rt286.c 29 KB

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  1. /*
  2. * rt286.c -- RT286 ALSA SoC audio codec driver
  3. *
  4. * Copyright 2013 Realtek Semiconductor Corp.
  5. * Author: Bard Liao <bardliao@realtek.com>
  6. *
  7. * This program is free software; you can redistribute it and/or modify
  8. * it under the terms of the GNU General Public License version 2 as
  9. * published by the Free Software Foundation.
  10. */
  11. #include <linux/module.h>
  12. #include <linux/moduleparam.h>
  13. #include <linux/init.h>
  14. #include <linux/delay.h>
  15. #include <linux/pm.h>
  16. #include <linux/i2c.h>
  17. #include <linux/platform_device.h>
  18. #include <linux/spi/spi.h>
  19. #include <linux/acpi.h>
  20. #include <sound/core.h>
  21. #include <sound/pcm.h>
  22. #include <sound/pcm_params.h>
  23. #include <sound/soc.h>
  24. #include <sound/soc-dapm.h>
  25. #include <sound/initval.h>
  26. #include <sound/tlv.h>
  27. #include <sound/jack.h>
  28. #include <linux/workqueue.h>
  29. #include <sound/rt286.h>
  30. #include <sound/hda_verbs.h>
  31. #include "rt286.h"
  32. #define RT286_VENDOR_ID 0x10ec0286
  33. struct rt286_priv {
  34. struct regmap *regmap;
  35. struct rt286_platform_data pdata;
  36. struct i2c_client *i2c;
  37. struct snd_soc_jack *jack;
  38. struct delayed_work jack_detect_work;
  39. int sys_clk;
  40. struct reg_default *index_cache;
  41. };
  42. static struct reg_default rt286_index_def[] = {
  43. { 0x01, 0xaaaa },
  44. { 0x02, 0x8aaa },
  45. { 0x03, 0x0002 },
  46. { 0x04, 0xaf01 },
  47. { 0x08, 0x000d },
  48. { 0x09, 0xd810 },
  49. { 0x0a, 0x0120 },
  50. { 0x0b, 0x0000 },
  51. { 0x0d, 0x2800 },
  52. { 0x0f, 0x0000 },
  53. { 0x19, 0x0a17 },
  54. { 0x20, 0x0020 },
  55. { 0x33, 0x0208 },
  56. { 0x49, 0x0004 },
  57. { 0x4f, 0x50e9 },
  58. { 0x50, 0x2000 },
  59. { 0x63, 0x2902 },
  60. { 0x67, 0x1111 },
  61. { 0x68, 0x1016 },
  62. { 0x69, 0x273f },
  63. };
  64. #define INDEX_CACHE_SIZE ARRAY_SIZE(rt286_index_def)
  65. static const struct reg_default rt286_reg[] = {
  66. { 0x00170500, 0x00000400 },
  67. { 0x00220000, 0x00000031 },
  68. { 0x00239000, 0x0000007f },
  69. { 0x0023a000, 0x0000007f },
  70. { 0x00270500, 0x00000400 },
  71. { 0x00370500, 0x00000400 },
  72. { 0x00870500, 0x00000400 },
  73. { 0x00920000, 0x00000031 },
  74. { 0x00935000, 0x000000c3 },
  75. { 0x00936000, 0x000000c3 },
  76. { 0x00970500, 0x00000400 },
  77. { 0x00b37000, 0x00000097 },
  78. { 0x00b37200, 0x00000097 },
  79. { 0x00b37300, 0x00000097 },
  80. { 0x00c37000, 0x00000000 },
  81. { 0x00c37100, 0x00000080 },
  82. { 0x01270500, 0x00000400 },
  83. { 0x01370500, 0x00000400 },
  84. { 0x01371f00, 0x411111f0 },
  85. { 0x01439000, 0x00000080 },
  86. { 0x0143a000, 0x00000080 },
  87. { 0x01470700, 0x00000000 },
  88. { 0x01470500, 0x00000400 },
  89. { 0x01470c00, 0x00000000 },
  90. { 0x01470100, 0x00000000 },
  91. { 0x01837000, 0x00000000 },
  92. { 0x01870500, 0x00000400 },
  93. { 0x02050000, 0x00000000 },
  94. { 0x02139000, 0x00000080 },
  95. { 0x0213a000, 0x00000080 },
  96. { 0x02170100, 0x00000000 },
  97. { 0x02170500, 0x00000400 },
  98. { 0x02170700, 0x00000000 },
  99. { 0x02270100, 0x00000000 },
  100. { 0x02370100, 0x00000000 },
  101. { 0x01870700, 0x00000020 },
  102. { 0x00830000, 0x000000c3 },
  103. { 0x00930000, 0x000000c3 },
  104. { 0x01270700, 0x00000000 },
  105. };
  106. static bool rt286_volatile_register(struct device *dev, unsigned int reg)
  107. {
  108. switch (reg) {
  109. case 0 ... 0xff:
  110. case RT286_GET_PARAM(AC_NODE_ROOT, AC_PAR_VENDOR_ID):
  111. case RT286_GET_HP_SENSE:
  112. case RT286_GET_MIC1_SENSE:
  113. case RT286_PROC_COEF:
  114. return true;
  115. default:
  116. return false;
  117. }
  118. }
  119. static bool rt286_readable_register(struct device *dev, unsigned int reg)
  120. {
  121. switch (reg) {
  122. case 0 ... 0xff:
  123. case RT286_GET_PARAM(AC_NODE_ROOT, AC_PAR_VENDOR_ID):
  124. case RT286_GET_HP_SENSE:
  125. case RT286_GET_MIC1_SENSE:
  126. case RT286_SET_AUDIO_POWER:
  127. case RT286_SET_HPO_POWER:
  128. case RT286_SET_SPK_POWER:
  129. case RT286_SET_DMIC1_POWER:
  130. case RT286_SPK_MUX:
  131. case RT286_HPO_MUX:
  132. case RT286_ADC0_MUX:
  133. case RT286_ADC1_MUX:
  134. case RT286_SET_MIC1:
  135. case RT286_SET_PIN_HPO:
  136. case RT286_SET_PIN_SPK:
  137. case RT286_SET_PIN_DMIC1:
  138. case RT286_SPK_EAPD:
  139. case RT286_SET_AMP_GAIN_HPO:
  140. case RT286_SET_DMIC2_DEFAULT:
  141. case RT286_DACL_GAIN:
  142. case RT286_DACR_GAIN:
  143. case RT286_ADCL_GAIN:
  144. case RT286_ADCR_GAIN:
  145. case RT286_MIC_GAIN:
  146. case RT286_SPOL_GAIN:
  147. case RT286_SPOR_GAIN:
  148. case RT286_HPOL_GAIN:
  149. case RT286_HPOR_GAIN:
  150. case RT286_F_DAC_SWITCH:
  151. case RT286_F_RECMIX_SWITCH:
  152. case RT286_REC_MIC_SWITCH:
  153. case RT286_REC_I2S_SWITCH:
  154. case RT286_REC_LINE_SWITCH:
  155. case RT286_REC_BEEP_SWITCH:
  156. case RT286_DAC_FORMAT:
  157. case RT286_ADC_FORMAT:
  158. case RT286_COEF_INDEX:
  159. case RT286_PROC_COEF:
  160. case RT286_SET_AMP_GAIN_ADC_IN1:
  161. case RT286_SET_AMP_GAIN_ADC_IN2:
  162. case RT286_SET_POWER(RT286_DAC_OUT1):
  163. case RT286_SET_POWER(RT286_DAC_OUT2):
  164. case RT286_SET_POWER(RT286_ADC_IN1):
  165. case RT286_SET_POWER(RT286_ADC_IN2):
  166. case RT286_SET_POWER(RT286_DMIC2):
  167. case RT286_SET_POWER(RT286_MIC1):
  168. return true;
  169. default:
  170. return false;
  171. }
  172. }
  173. static int rt286_hw_write(void *context, unsigned int reg, unsigned int value)
  174. {
  175. struct i2c_client *client = context;
  176. struct rt286_priv *rt286 = i2c_get_clientdata(client);
  177. u8 data[4];
  178. int ret, i;
  179. /*handle index registers*/
  180. if (reg <= 0xff) {
  181. rt286_hw_write(client, RT286_COEF_INDEX, reg);
  182. for (i = 0; i < INDEX_CACHE_SIZE; i++) {
  183. if (reg == rt286->index_cache[i].reg) {
  184. rt286->index_cache[i].def = value;
  185. break;
  186. }
  187. }
  188. reg = RT286_PROC_COEF;
  189. }
  190. data[0] = (reg >> 24) & 0xff;
  191. data[1] = (reg >> 16) & 0xff;
  192. /*
  193. * 4 bit VID: reg should be 0
  194. * 12 bit VID: value should be 0
  195. * So we use an OR operator to handle it rather than use if condition.
  196. */
  197. data[2] = ((reg >> 8) & 0xff) | ((value >> 8) & 0xff);
  198. data[3] = value & 0xff;
  199. ret = i2c_master_send(client, data, 4);
  200. if (ret == 4)
  201. return 0;
  202. else
  203. pr_err("ret=%d\n", ret);
  204. if (ret < 0)
  205. return ret;
  206. else
  207. return -EIO;
  208. }
  209. static int rt286_hw_read(void *context, unsigned int reg, unsigned int *value)
  210. {
  211. struct i2c_client *client = context;
  212. struct i2c_msg xfer[2];
  213. int ret;
  214. __be32 be_reg;
  215. unsigned int index, vid, buf = 0x0;
  216. /*handle index registers*/
  217. if (reg <= 0xff) {
  218. rt286_hw_write(client, RT286_COEF_INDEX, reg);
  219. reg = RT286_PROC_COEF;
  220. }
  221. reg = reg | 0x80000;
  222. vid = (reg >> 8) & 0xfff;
  223. if (AC_VERB_GET_AMP_GAIN_MUTE == (vid & 0xf00)) {
  224. index = (reg >> 8) & 0xf;
  225. reg = (reg & ~0xf0f) | index;
  226. }
  227. be_reg = cpu_to_be32(reg);
  228. /* Write register */
  229. xfer[0].addr = client->addr;
  230. xfer[0].flags = 0;
  231. xfer[0].len = 4;
  232. xfer[0].buf = (u8 *)&be_reg;
  233. /* Read data */
  234. xfer[1].addr = client->addr;
  235. xfer[1].flags = I2C_M_RD;
  236. xfer[1].len = 4;
  237. xfer[1].buf = (u8 *)&buf;
  238. ret = i2c_transfer(client->adapter, xfer, 2);
  239. if (ret < 0)
  240. return ret;
  241. else if (ret != 2)
  242. return -EIO;
  243. *value = be32_to_cpu(buf);
  244. return 0;
  245. }
  246. #ifdef CONFIG_PM
  247. static void rt286_index_sync(struct snd_soc_codec *codec)
  248. {
  249. struct rt286_priv *rt286 = snd_soc_codec_get_drvdata(codec);
  250. int i;
  251. for (i = 0; i < INDEX_CACHE_SIZE; i++) {
  252. snd_soc_write(codec, rt286->index_cache[i].reg,
  253. rt286->index_cache[i].def);
  254. }
  255. }
  256. #endif
  257. static int rt286_support_power_controls[] = {
  258. RT286_DAC_OUT1,
  259. RT286_DAC_OUT2,
  260. RT286_ADC_IN1,
  261. RT286_ADC_IN2,
  262. RT286_MIC1,
  263. RT286_DMIC1,
  264. RT286_DMIC2,
  265. RT286_SPK_OUT,
  266. RT286_HP_OUT,
  267. };
  268. #define RT286_POWER_REG_LEN ARRAY_SIZE(rt286_support_power_controls)
  269. static int rt286_jack_detect(struct rt286_priv *rt286, bool *hp, bool *mic)
  270. {
  271. unsigned int val, buf;
  272. int i;
  273. *hp = false;
  274. *mic = false;
  275. if (rt286->pdata.cbj_en) {
  276. regmap_read(rt286->regmap, RT286_GET_HP_SENSE, &buf);
  277. *hp = buf & 0x80000000;
  278. if (*hp) {
  279. /* power on HV,VERF */
  280. regmap_update_bits(rt286->regmap,
  281. RT286_POWER_CTRL1, 0x1001, 0x0);
  282. /* power LDO1 */
  283. regmap_update_bits(rt286->regmap,
  284. RT286_POWER_CTRL2, 0x4, 0x4);
  285. regmap_write(rt286->regmap, RT286_SET_MIC1, 0x24);
  286. regmap_read(rt286->regmap, RT286_CBJ_CTRL2, &val);
  287. msleep(200);
  288. i = 40;
  289. while (((val & 0x0800) == 0) && (i > 0)) {
  290. regmap_read(rt286->regmap,
  291. RT286_CBJ_CTRL2, &val);
  292. i--;
  293. msleep(20);
  294. }
  295. if (0x0400 == (val & 0x0700)) {
  296. *mic = false;
  297. regmap_write(rt286->regmap,
  298. RT286_SET_MIC1, 0x20);
  299. /* power off HV,VERF */
  300. regmap_update_bits(rt286->regmap,
  301. RT286_POWER_CTRL1, 0x1001, 0x1001);
  302. regmap_update_bits(rt286->regmap,
  303. RT286_A_BIAS_CTRL3, 0xc000, 0x0000);
  304. regmap_update_bits(rt286->regmap,
  305. RT286_CBJ_CTRL1, 0x0030, 0x0000);
  306. regmap_update_bits(rt286->regmap,
  307. RT286_A_BIAS_CTRL2, 0xc000, 0x0000);
  308. } else if ((0x0200 == (val & 0x0700)) ||
  309. (0x0100 == (val & 0x0700))) {
  310. *mic = true;
  311. regmap_update_bits(rt286->regmap,
  312. RT286_A_BIAS_CTRL3, 0xc000, 0x8000);
  313. regmap_update_bits(rt286->regmap,
  314. RT286_CBJ_CTRL1, 0x0030, 0x0020);
  315. regmap_update_bits(rt286->regmap,
  316. RT286_A_BIAS_CTRL2, 0xc000, 0x8000);
  317. } else {
  318. *mic = false;
  319. }
  320. regmap_update_bits(rt286->regmap,
  321. RT286_MISC_CTRL1,
  322. 0x0060, 0x0000);
  323. } else {
  324. regmap_update_bits(rt286->regmap,
  325. RT286_MISC_CTRL1,
  326. 0x0060, 0x0020);
  327. regmap_update_bits(rt286->regmap,
  328. RT286_A_BIAS_CTRL3,
  329. 0xc000, 0x8000);
  330. regmap_update_bits(rt286->regmap,
  331. RT286_CBJ_CTRL1,
  332. 0x0030, 0x0020);
  333. regmap_update_bits(rt286->regmap,
  334. RT286_A_BIAS_CTRL2,
  335. 0xc000, 0x8000);
  336. *mic = false;
  337. }
  338. } else {
  339. regmap_read(rt286->regmap, RT286_GET_HP_SENSE, &buf);
  340. *hp = buf & 0x80000000;
  341. regmap_read(rt286->regmap, RT286_GET_MIC1_SENSE, &buf);
  342. *mic = buf & 0x80000000;
  343. }
  344. return 0;
  345. }
  346. static void rt286_jack_detect_work(struct work_struct *work)
  347. {
  348. struct rt286_priv *rt286 =
  349. container_of(work, struct rt286_priv, jack_detect_work.work);
  350. int status = 0;
  351. bool hp = false;
  352. bool mic = false;
  353. rt286_jack_detect(rt286, &hp, &mic);
  354. if (hp == true)
  355. status |= SND_JACK_HEADPHONE;
  356. if (mic == true)
  357. status |= SND_JACK_MICROPHONE;
  358. snd_soc_jack_report(rt286->jack, status,
  359. SND_JACK_MICROPHONE | SND_JACK_HEADPHONE);
  360. }
  361. int rt286_mic_detect(struct snd_soc_codec *codec, struct snd_soc_jack *jack)
  362. {
  363. struct rt286_priv *rt286 = snd_soc_codec_get_drvdata(codec);
  364. rt286->jack = jack;
  365. /* Send an initial empty report */
  366. snd_soc_jack_report(rt286->jack, 0,
  367. SND_JACK_MICROPHONE | SND_JACK_HEADPHONE);
  368. return 0;
  369. }
  370. EXPORT_SYMBOL_GPL(rt286_mic_detect);
  371. static const DECLARE_TLV_DB_SCALE(out_vol_tlv, -6350, 50, 0);
  372. static const DECLARE_TLV_DB_SCALE(mic_vol_tlv, 0, 1000, 0);
  373. static const struct snd_kcontrol_new rt286_snd_controls[] = {
  374. SOC_DOUBLE_R_TLV("DAC0 Playback Volume", RT286_DACL_GAIN,
  375. RT286_DACR_GAIN, 0, 0x7f, 0, out_vol_tlv),
  376. SOC_DOUBLE_R_TLV("ADC0 Capture Volume", RT286_ADCL_GAIN,
  377. RT286_ADCR_GAIN, 0, 0x7f, 0, out_vol_tlv),
  378. SOC_SINGLE_TLV("AMIC Volume", RT286_MIC_GAIN,
  379. 0, 0x3, 0, mic_vol_tlv),
  380. SOC_DOUBLE_R("Speaker Playback Switch", RT286_SPOL_GAIN,
  381. RT286_SPOR_GAIN, RT286_MUTE_SFT, 1, 1),
  382. };
  383. /* Digital Mixer */
  384. static const struct snd_kcontrol_new rt286_front_mix[] = {
  385. SOC_DAPM_SINGLE("DAC Switch", RT286_F_DAC_SWITCH,
  386. RT286_MUTE_SFT, 1, 1),
  387. SOC_DAPM_SINGLE("RECMIX Switch", RT286_F_RECMIX_SWITCH,
  388. RT286_MUTE_SFT, 1, 1),
  389. };
  390. /* Analog Input Mixer */
  391. static const struct snd_kcontrol_new rt286_rec_mix[] = {
  392. SOC_DAPM_SINGLE("Mic1 Switch", RT286_REC_MIC_SWITCH,
  393. RT286_MUTE_SFT, 1, 1),
  394. SOC_DAPM_SINGLE("I2S Switch", RT286_REC_I2S_SWITCH,
  395. RT286_MUTE_SFT, 1, 1),
  396. SOC_DAPM_SINGLE("Line1 Switch", RT286_REC_LINE_SWITCH,
  397. RT286_MUTE_SFT, 1, 1),
  398. SOC_DAPM_SINGLE("Beep Switch", RT286_REC_BEEP_SWITCH,
  399. RT286_MUTE_SFT, 1, 1),
  400. };
  401. static const struct snd_kcontrol_new spo_enable_control =
  402. SOC_DAPM_SINGLE("Switch", RT286_SET_PIN_SPK,
  403. RT286_SET_PIN_SFT, 1, 0);
  404. static const struct snd_kcontrol_new hpol_enable_control =
  405. SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT286_HPOL_GAIN,
  406. RT286_MUTE_SFT, 1, 1);
  407. static const struct snd_kcontrol_new hpor_enable_control =
  408. SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT286_HPOR_GAIN,
  409. RT286_MUTE_SFT, 1, 1);
  410. /* ADC0 source */
  411. static const char * const rt286_adc_src[] = {
  412. "Mic", "RECMIX", "Dmic"
  413. };
  414. static const int rt286_adc_values[] = {
  415. 0, 4, 5,
  416. };
  417. static SOC_VALUE_ENUM_SINGLE_DECL(
  418. rt286_adc0_enum, RT286_ADC0_MUX, RT286_ADC_SEL_SFT,
  419. RT286_ADC_SEL_MASK, rt286_adc_src, rt286_adc_values);
  420. static const struct snd_kcontrol_new rt286_adc0_mux =
  421. SOC_DAPM_ENUM("ADC 0 source", rt286_adc0_enum);
  422. static SOC_VALUE_ENUM_SINGLE_DECL(
  423. rt286_adc1_enum, RT286_ADC1_MUX, RT286_ADC_SEL_SFT,
  424. RT286_ADC_SEL_MASK, rt286_adc_src, rt286_adc_values);
  425. static const struct snd_kcontrol_new rt286_adc1_mux =
  426. SOC_DAPM_ENUM("ADC 1 source", rt286_adc1_enum);
  427. static const char * const rt286_dac_src[] = {
  428. "Front", "Surround"
  429. };
  430. /* HP-OUT source */
  431. static SOC_ENUM_SINGLE_DECL(rt286_hpo_enum, RT286_HPO_MUX,
  432. 0, rt286_dac_src);
  433. static const struct snd_kcontrol_new rt286_hpo_mux =
  434. SOC_DAPM_ENUM("HPO source", rt286_hpo_enum);
  435. /* SPK-OUT source */
  436. static SOC_ENUM_SINGLE_DECL(rt286_spo_enum, RT286_SPK_MUX,
  437. 0, rt286_dac_src);
  438. static const struct snd_kcontrol_new rt286_spo_mux =
  439. SOC_DAPM_ENUM("SPO source", rt286_spo_enum);
  440. static int rt286_spk_event(struct snd_soc_dapm_widget *w,
  441. struct snd_kcontrol *kcontrol, int event)
  442. {
  443. struct snd_soc_codec *codec = w->codec;
  444. switch (event) {
  445. case SND_SOC_DAPM_POST_PMU:
  446. snd_soc_write(codec,
  447. RT286_SPK_EAPD, RT286_SET_EAPD_HIGH);
  448. break;
  449. case SND_SOC_DAPM_PRE_PMD:
  450. snd_soc_write(codec,
  451. RT286_SPK_EAPD, RT286_SET_EAPD_LOW);
  452. break;
  453. default:
  454. return 0;
  455. }
  456. return 0;
  457. }
  458. static int rt286_set_dmic1_event(struct snd_soc_dapm_widget *w,
  459. struct snd_kcontrol *kcontrol, int event)
  460. {
  461. struct snd_soc_codec *codec = w->codec;
  462. switch (event) {
  463. case SND_SOC_DAPM_POST_PMU:
  464. snd_soc_write(codec, RT286_SET_PIN_DMIC1, 0x20);
  465. break;
  466. case SND_SOC_DAPM_PRE_PMD:
  467. snd_soc_write(codec, RT286_SET_PIN_DMIC1, 0);
  468. break;
  469. default:
  470. return 0;
  471. }
  472. return 0;
  473. }
  474. static int rt286_adc_event(struct snd_soc_dapm_widget *w,
  475. struct snd_kcontrol *kcontrol, int event)
  476. {
  477. struct snd_soc_codec *codec = w->codec;
  478. unsigned int nid;
  479. nid = (w->reg >> 20) & 0xff;
  480. switch (event) {
  481. case SND_SOC_DAPM_POST_PMU:
  482. snd_soc_update_bits(codec,
  483. VERB_CMD(AC_VERB_SET_AMP_GAIN_MUTE, nid, 0),
  484. 0x7080, 0x7000);
  485. break;
  486. case SND_SOC_DAPM_PRE_PMD:
  487. snd_soc_update_bits(codec,
  488. VERB_CMD(AC_VERB_SET_AMP_GAIN_MUTE, nid, 0),
  489. 0x7080, 0x7080);
  490. break;
  491. default:
  492. return 0;
  493. }
  494. return 0;
  495. }
  496. static const struct snd_soc_dapm_widget rt286_dapm_widgets[] = {
  497. /* Input Lines */
  498. SND_SOC_DAPM_INPUT("DMIC1 Pin"),
  499. SND_SOC_DAPM_INPUT("DMIC2 Pin"),
  500. SND_SOC_DAPM_INPUT("MIC1"),
  501. SND_SOC_DAPM_INPUT("LINE1"),
  502. SND_SOC_DAPM_INPUT("Beep"),
  503. /* DMIC */
  504. SND_SOC_DAPM_PGA_E("DMIC1", RT286_SET_POWER(RT286_DMIC1), 0, 1,
  505. NULL, 0, rt286_set_dmic1_event,
  506. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU),
  507. SND_SOC_DAPM_PGA("DMIC2", RT286_SET_POWER(RT286_DMIC2), 0, 1,
  508. NULL, 0),
  509. SND_SOC_DAPM_SUPPLY("DMIC Receiver", SND_SOC_NOPM,
  510. 0, 0, NULL, 0),
  511. /* REC Mixer */
  512. SND_SOC_DAPM_MIXER("RECMIX", SND_SOC_NOPM, 0, 0,
  513. rt286_rec_mix, ARRAY_SIZE(rt286_rec_mix)),
  514. /* ADCs */
  515. SND_SOC_DAPM_ADC("ADC 0", NULL, SND_SOC_NOPM, 0, 0),
  516. SND_SOC_DAPM_ADC("ADC 1", NULL, SND_SOC_NOPM, 0, 0),
  517. /* ADC Mux */
  518. SND_SOC_DAPM_MUX_E("ADC 0 Mux", RT286_SET_POWER(RT286_ADC_IN1), 0, 1,
  519. &rt286_adc0_mux, rt286_adc_event, SND_SOC_DAPM_PRE_PMD |
  520. SND_SOC_DAPM_POST_PMU),
  521. SND_SOC_DAPM_MUX_E("ADC 1 Mux", RT286_SET_POWER(RT286_ADC_IN2), 0, 1,
  522. &rt286_adc1_mux, rt286_adc_event, SND_SOC_DAPM_PRE_PMD |
  523. SND_SOC_DAPM_POST_PMU),
  524. /* Audio Interface */
  525. SND_SOC_DAPM_AIF_IN("AIF1RX", "AIF1 Playback", 0, SND_SOC_NOPM, 0, 0),
  526. SND_SOC_DAPM_AIF_OUT("AIF1TX", "AIF1 Capture", 0, SND_SOC_NOPM, 0, 0),
  527. SND_SOC_DAPM_AIF_IN("AIF2RX", "AIF2 Playback", 0, SND_SOC_NOPM, 0, 0),
  528. SND_SOC_DAPM_AIF_OUT("AIF2TX", "AIF2 Capture", 0, SND_SOC_NOPM, 0, 0),
  529. /* Output Side */
  530. /* DACs */
  531. SND_SOC_DAPM_DAC("DAC 0", NULL, SND_SOC_NOPM, 0, 0),
  532. SND_SOC_DAPM_DAC("DAC 1", NULL, SND_SOC_NOPM, 0, 0),
  533. /* Output Mux */
  534. SND_SOC_DAPM_MUX("SPK Mux", SND_SOC_NOPM, 0, 0, &rt286_spo_mux),
  535. SND_SOC_DAPM_MUX("HPO Mux", SND_SOC_NOPM, 0, 0, &rt286_hpo_mux),
  536. SND_SOC_DAPM_SUPPLY("HP Power", RT286_SET_PIN_HPO,
  537. RT286_SET_PIN_SFT, 0, NULL, 0),
  538. /* Output Mixer */
  539. SND_SOC_DAPM_MIXER("Front", RT286_SET_POWER(RT286_DAC_OUT1), 0, 1,
  540. rt286_front_mix, ARRAY_SIZE(rt286_front_mix)),
  541. SND_SOC_DAPM_PGA("Surround", RT286_SET_POWER(RT286_DAC_OUT2), 0, 1,
  542. NULL, 0),
  543. /* Output Pga */
  544. SND_SOC_DAPM_SWITCH_E("SPO", SND_SOC_NOPM, 0, 0,
  545. &spo_enable_control, rt286_spk_event,
  546. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU),
  547. SND_SOC_DAPM_SWITCH("HPO L", SND_SOC_NOPM, 0, 0,
  548. &hpol_enable_control),
  549. SND_SOC_DAPM_SWITCH("HPO R", SND_SOC_NOPM, 0, 0,
  550. &hpor_enable_control),
  551. /* Output Lines */
  552. SND_SOC_DAPM_OUTPUT("SPOL"),
  553. SND_SOC_DAPM_OUTPUT("SPOR"),
  554. SND_SOC_DAPM_OUTPUT("HPO Pin"),
  555. SND_SOC_DAPM_OUTPUT("SPDIF"),
  556. };
  557. static const struct snd_soc_dapm_route rt286_dapm_routes[] = {
  558. {"DMIC1", NULL, "DMIC1 Pin"},
  559. {"DMIC2", NULL, "DMIC2 Pin"},
  560. {"DMIC1", NULL, "DMIC Receiver"},
  561. {"DMIC2", NULL, "DMIC Receiver"},
  562. {"RECMIX", "Beep Switch", "Beep"},
  563. {"RECMIX", "Line1 Switch", "LINE1"},
  564. {"RECMIX", "Mic1 Switch", "MIC1"},
  565. {"ADC 0 Mux", "Dmic", "DMIC1"},
  566. {"ADC 0 Mux", "RECMIX", "RECMIX"},
  567. {"ADC 0 Mux", "Mic", "MIC1"},
  568. {"ADC 1 Mux", "Dmic", "DMIC2"},
  569. {"ADC 1 Mux", "RECMIX", "RECMIX"},
  570. {"ADC 1 Mux", "Mic", "MIC1"},
  571. {"ADC 0", NULL, "ADC 0 Mux"},
  572. {"ADC 1", NULL, "ADC 1 Mux"},
  573. {"AIF1TX", NULL, "ADC 0"},
  574. {"AIF2TX", NULL, "ADC 1"},
  575. {"DAC 0", NULL, "AIF1RX"},
  576. {"DAC 1", NULL, "AIF2RX"},
  577. {"Front", "DAC Switch", "DAC 0"},
  578. {"Front", "RECMIX Switch", "RECMIX"},
  579. {"Surround", NULL, "DAC 1"},
  580. {"SPK Mux", "Front", "Front"},
  581. {"SPK Mux", "Surround", "Surround"},
  582. {"HPO Mux", "Front", "Front"},
  583. {"HPO Mux", "Surround", "Surround"},
  584. {"SPO", "Switch", "SPK Mux"},
  585. {"HPO L", "Switch", "HPO Mux"},
  586. {"HPO R", "Switch", "HPO Mux"},
  587. {"HPO L", NULL, "HP Power"},
  588. {"HPO R", NULL, "HP Power"},
  589. {"SPOL", NULL, "SPO"},
  590. {"SPOR", NULL, "SPO"},
  591. {"HPO Pin", NULL, "HPO L"},
  592. {"HPO Pin", NULL, "HPO R"},
  593. };
  594. static int rt286_hw_params(struct snd_pcm_substream *substream,
  595. struct snd_pcm_hw_params *params,
  596. struct snd_soc_dai *dai)
  597. {
  598. struct snd_soc_codec *codec = dai->codec;
  599. struct rt286_priv *rt286 = snd_soc_codec_get_drvdata(codec);
  600. unsigned int val = 0;
  601. int d_len_code;
  602. switch (params_rate(params)) {
  603. /* bit 14 0:48K 1:44.1K */
  604. case 44100:
  605. val |= 0x4000;
  606. break;
  607. case 48000:
  608. break;
  609. default:
  610. dev_err(codec->dev, "Unsupported sample rate %d\n",
  611. params_rate(params));
  612. return -EINVAL;
  613. }
  614. switch (rt286->sys_clk) {
  615. case 12288000:
  616. case 24576000:
  617. if (params_rate(params) != 48000) {
  618. dev_err(codec->dev, "Sys_clk is not matched (%d %d)\n",
  619. params_rate(params), rt286->sys_clk);
  620. return -EINVAL;
  621. }
  622. break;
  623. case 11289600:
  624. case 22579200:
  625. if (params_rate(params) != 44100) {
  626. dev_err(codec->dev, "Sys_clk is not matched (%d %d)\n",
  627. params_rate(params), rt286->sys_clk);
  628. return -EINVAL;
  629. }
  630. break;
  631. }
  632. if (params_channels(params) <= 16) {
  633. /* bit 3:0 Number of Channel */
  634. val |= (params_channels(params) - 1);
  635. } else {
  636. dev_err(codec->dev, "Unsupported channels %d\n",
  637. params_channels(params));
  638. return -EINVAL;
  639. }
  640. d_len_code = 0;
  641. switch (params_width(params)) {
  642. /* bit 6:4 Bits per Sample */
  643. case 16:
  644. d_len_code = 0;
  645. val |= (0x1 << 4);
  646. break;
  647. case 32:
  648. d_len_code = 2;
  649. val |= (0x4 << 4);
  650. break;
  651. case 20:
  652. d_len_code = 1;
  653. val |= (0x2 << 4);
  654. break;
  655. case 24:
  656. d_len_code = 2;
  657. val |= (0x3 << 4);
  658. break;
  659. case 8:
  660. d_len_code = 3;
  661. break;
  662. default:
  663. return -EINVAL;
  664. }
  665. snd_soc_update_bits(codec,
  666. RT286_I2S_CTRL1, 0x0018, d_len_code << 3);
  667. dev_dbg(codec->dev, "format val = 0x%x\n", val);
  668. if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
  669. snd_soc_update_bits(codec, RT286_DAC_FORMAT, 0x407f, val);
  670. else
  671. snd_soc_update_bits(codec, RT286_ADC_FORMAT, 0x407f, val);
  672. return 0;
  673. }
  674. static int rt286_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
  675. {
  676. struct snd_soc_codec *codec = dai->codec;
  677. switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
  678. case SND_SOC_DAIFMT_CBM_CFM:
  679. snd_soc_update_bits(codec,
  680. RT286_I2S_CTRL1, 0x800, 0x800);
  681. break;
  682. case SND_SOC_DAIFMT_CBS_CFS:
  683. snd_soc_update_bits(codec,
  684. RT286_I2S_CTRL1, 0x800, 0x0);
  685. break;
  686. default:
  687. return -EINVAL;
  688. }
  689. switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
  690. case SND_SOC_DAIFMT_I2S:
  691. snd_soc_update_bits(codec,
  692. RT286_I2S_CTRL1, 0x300, 0x0);
  693. break;
  694. case SND_SOC_DAIFMT_LEFT_J:
  695. snd_soc_update_bits(codec,
  696. RT286_I2S_CTRL1, 0x300, 0x1 << 8);
  697. break;
  698. case SND_SOC_DAIFMT_DSP_A:
  699. snd_soc_update_bits(codec,
  700. RT286_I2S_CTRL1, 0x300, 0x2 << 8);
  701. break;
  702. case SND_SOC_DAIFMT_DSP_B:
  703. snd_soc_update_bits(codec,
  704. RT286_I2S_CTRL1, 0x300, 0x3 << 8);
  705. break;
  706. default:
  707. return -EINVAL;
  708. }
  709. /* bit 15 Stream Type 0:PCM 1:Non-PCM */
  710. snd_soc_update_bits(codec, RT286_DAC_FORMAT, 0x8000, 0);
  711. snd_soc_update_bits(codec, RT286_ADC_FORMAT, 0x8000, 0);
  712. return 0;
  713. }
  714. static int rt286_set_dai_sysclk(struct snd_soc_dai *dai,
  715. int clk_id, unsigned int freq, int dir)
  716. {
  717. struct snd_soc_codec *codec = dai->codec;
  718. struct rt286_priv *rt286 = snd_soc_codec_get_drvdata(codec);
  719. dev_dbg(codec->dev, "%s freq=%d\n", __func__, freq);
  720. if (RT286_SCLK_S_MCLK == clk_id) {
  721. snd_soc_update_bits(codec,
  722. RT286_I2S_CTRL2, 0x0100, 0x0);
  723. snd_soc_update_bits(codec,
  724. RT286_PLL_CTRL1, 0x20, 0x20);
  725. } else {
  726. snd_soc_update_bits(codec,
  727. RT286_I2S_CTRL2, 0x0100, 0x0100);
  728. snd_soc_update_bits(codec,
  729. RT286_PLL_CTRL, 0x4, 0x4);
  730. snd_soc_update_bits(codec,
  731. RT286_PLL_CTRL1, 0x20, 0x0);
  732. }
  733. switch (freq) {
  734. case 19200000:
  735. if (RT286_SCLK_S_MCLK == clk_id) {
  736. dev_err(codec->dev, "Should not use MCLK\n");
  737. return -EINVAL;
  738. }
  739. snd_soc_update_bits(codec,
  740. RT286_I2S_CTRL2, 0x40, 0x40);
  741. break;
  742. case 24000000:
  743. if (RT286_SCLK_S_MCLK == clk_id) {
  744. dev_err(codec->dev, "Should not use MCLK\n");
  745. return -EINVAL;
  746. }
  747. snd_soc_update_bits(codec,
  748. RT286_I2S_CTRL2, 0x40, 0x0);
  749. break;
  750. case 12288000:
  751. case 11289600:
  752. snd_soc_update_bits(codec,
  753. RT286_I2S_CTRL2, 0x8, 0x0);
  754. snd_soc_update_bits(codec,
  755. RT286_CLK_DIV, 0xfc1e, 0x0004);
  756. break;
  757. case 24576000:
  758. case 22579200:
  759. snd_soc_update_bits(codec,
  760. RT286_I2S_CTRL2, 0x8, 0x8);
  761. snd_soc_update_bits(codec,
  762. RT286_CLK_DIV, 0xfc1e, 0x5406);
  763. break;
  764. default:
  765. dev_err(codec->dev, "Unsupported system clock\n");
  766. return -EINVAL;
  767. }
  768. rt286->sys_clk = freq;
  769. return 0;
  770. }
  771. static int rt286_set_bclk_ratio(struct snd_soc_dai *dai, unsigned int ratio)
  772. {
  773. struct snd_soc_codec *codec = dai->codec;
  774. dev_dbg(codec->dev, "%s ratio=%d\n", __func__, ratio);
  775. if (50 == ratio)
  776. snd_soc_update_bits(codec,
  777. RT286_I2S_CTRL1, 0x1000, 0x1000);
  778. else
  779. snd_soc_update_bits(codec,
  780. RT286_I2S_CTRL1, 0x1000, 0x0);
  781. return 0;
  782. }
  783. static int rt286_set_bias_level(struct snd_soc_codec *codec,
  784. enum snd_soc_bias_level level)
  785. {
  786. switch (level) {
  787. case SND_SOC_BIAS_PREPARE:
  788. if (SND_SOC_BIAS_STANDBY == codec->dapm.bias_level) {
  789. snd_soc_write(codec,
  790. RT286_SET_AUDIO_POWER, AC_PWRST_D0);
  791. snd_soc_update_bits(codec,
  792. RT286_DC_GAIN, 0x200, 0x200);
  793. }
  794. break;
  795. case SND_SOC_BIAS_ON:
  796. mdelay(10);
  797. break;
  798. case SND_SOC_BIAS_STANDBY:
  799. snd_soc_write(codec,
  800. RT286_SET_AUDIO_POWER, AC_PWRST_D3);
  801. snd_soc_update_bits(codec,
  802. RT286_DC_GAIN, 0x200, 0x0);
  803. break;
  804. default:
  805. break;
  806. }
  807. codec->dapm.bias_level = level;
  808. return 0;
  809. }
  810. static irqreturn_t rt286_irq(int irq, void *data)
  811. {
  812. struct rt286_priv *rt286 = data;
  813. bool hp = false;
  814. bool mic = false;
  815. int status = 0;
  816. rt286_jack_detect(rt286, &hp, &mic);
  817. /* Clear IRQ */
  818. regmap_update_bits(rt286->regmap, RT286_IRQ_CTRL, 0x1, 0x1);
  819. if (hp == true)
  820. status |= SND_JACK_HEADPHONE;
  821. if (mic == true)
  822. status |= SND_JACK_MICROPHONE;
  823. snd_soc_jack_report(rt286->jack, status,
  824. SND_JACK_MICROPHONE | SND_JACK_HEADPHONE);
  825. pm_wakeup_event(&rt286->i2c->dev, 300);
  826. return IRQ_HANDLED;
  827. }
  828. static int rt286_probe(struct snd_soc_codec *codec)
  829. {
  830. struct rt286_priv *rt286 = snd_soc_codec_get_drvdata(codec);
  831. codec->dapm.bias_level = SND_SOC_BIAS_OFF;
  832. if (rt286->i2c->irq) {
  833. regmap_update_bits(rt286->regmap,
  834. RT286_IRQ_CTRL, 0x2, 0x2);
  835. INIT_DELAYED_WORK(&rt286->jack_detect_work,
  836. rt286_jack_detect_work);
  837. schedule_delayed_work(&rt286->jack_detect_work,
  838. msecs_to_jiffies(1250));
  839. }
  840. return 0;
  841. }
  842. static int rt286_remove(struct snd_soc_codec *codec)
  843. {
  844. struct rt286_priv *rt286 = snd_soc_codec_get_drvdata(codec);
  845. cancel_delayed_work_sync(&rt286->jack_detect_work);
  846. return 0;
  847. }
  848. #ifdef CONFIG_PM
  849. static int rt286_suspend(struct snd_soc_codec *codec)
  850. {
  851. struct rt286_priv *rt286 = snd_soc_codec_get_drvdata(codec);
  852. regcache_cache_only(rt286->regmap, true);
  853. regcache_mark_dirty(rt286->regmap);
  854. return 0;
  855. }
  856. static int rt286_resume(struct snd_soc_codec *codec)
  857. {
  858. struct rt286_priv *rt286 = snd_soc_codec_get_drvdata(codec);
  859. regcache_cache_only(rt286->regmap, false);
  860. rt286_index_sync(codec);
  861. regcache_sync(rt286->regmap);
  862. return 0;
  863. }
  864. #else
  865. #define rt286_suspend NULL
  866. #define rt286_resume NULL
  867. #endif
  868. #define RT286_STEREO_RATES (SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000)
  869. #define RT286_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \
  870. SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S8)
  871. static const struct snd_soc_dai_ops rt286_aif_dai_ops = {
  872. .hw_params = rt286_hw_params,
  873. .set_fmt = rt286_set_dai_fmt,
  874. .set_sysclk = rt286_set_dai_sysclk,
  875. .set_bclk_ratio = rt286_set_bclk_ratio,
  876. };
  877. static struct snd_soc_dai_driver rt286_dai[] = {
  878. {
  879. .name = "rt286-aif1",
  880. .id = RT286_AIF1,
  881. .playback = {
  882. .stream_name = "AIF1 Playback",
  883. .channels_min = 1,
  884. .channels_max = 2,
  885. .rates = RT286_STEREO_RATES,
  886. .formats = RT286_FORMATS,
  887. },
  888. .capture = {
  889. .stream_name = "AIF1 Capture",
  890. .channels_min = 1,
  891. .channels_max = 2,
  892. .rates = RT286_STEREO_RATES,
  893. .formats = RT286_FORMATS,
  894. },
  895. .ops = &rt286_aif_dai_ops,
  896. .symmetric_rates = 1,
  897. },
  898. {
  899. .name = "rt286-aif2",
  900. .id = RT286_AIF2,
  901. .playback = {
  902. .stream_name = "AIF2 Playback",
  903. .channels_min = 1,
  904. .channels_max = 2,
  905. .rates = RT286_STEREO_RATES,
  906. .formats = RT286_FORMATS,
  907. },
  908. .capture = {
  909. .stream_name = "AIF2 Capture",
  910. .channels_min = 1,
  911. .channels_max = 2,
  912. .rates = RT286_STEREO_RATES,
  913. .formats = RT286_FORMATS,
  914. },
  915. .ops = &rt286_aif_dai_ops,
  916. .symmetric_rates = 1,
  917. },
  918. };
  919. static struct snd_soc_codec_driver soc_codec_dev_rt286 = {
  920. .probe = rt286_probe,
  921. .remove = rt286_remove,
  922. .suspend = rt286_suspend,
  923. .resume = rt286_resume,
  924. .set_bias_level = rt286_set_bias_level,
  925. .idle_bias_off = true,
  926. .controls = rt286_snd_controls,
  927. .num_controls = ARRAY_SIZE(rt286_snd_controls),
  928. .dapm_widgets = rt286_dapm_widgets,
  929. .num_dapm_widgets = ARRAY_SIZE(rt286_dapm_widgets),
  930. .dapm_routes = rt286_dapm_routes,
  931. .num_dapm_routes = ARRAY_SIZE(rt286_dapm_routes),
  932. };
  933. static const struct regmap_config rt286_regmap = {
  934. .reg_bits = 32,
  935. .val_bits = 32,
  936. .max_register = 0x02370100,
  937. .volatile_reg = rt286_volatile_register,
  938. .readable_reg = rt286_readable_register,
  939. .reg_write = rt286_hw_write,
  940. .reg_read = rt286_hw_read,
  941. .cache_type = REGCACHE_RBTREE,
  942. .reg_defaults = rt286_reg,
  943. .num_reg_defaults = ARRAY_SIZE(rt286_reg),
  944. };
  945. static const struct i2c_device_id rt286_i2c_id[] = {
  946. {"rt286", 0},
  947. {}
  948. };
  949. MODULE_DEVICE_TABLE(i2c, rt286_i2c_id);
  950. static const struct acpi_device_id rt286_acpi_match[] = {
  951. { "INT343A", 0 },
  952. {},
  953. };
  954. MODULE_DEVICE_TABLE(acpi, rt286_acpi_match);
  955. static int rt286_i2c_probe(struct i2c_client *i2c,
  956. const struct i2c_device_id *id)
  957. {
  958. struct rt286_platform_data *pdata = dev_get_platdata(&i2c->dev);
  959. struct rt286_priv *rt286;
  960. int i, ret;
  961. rt286 = devm_kzalloc(&i2c->dev, sizeof(*rt286),
  962. GFP_KERNEL);
  963. if (NULL == rt286)
  964. return -ENOMEM;
  965. rt286->regmap = devm_regmap_init(&i2c->dev, NULL, i2c, &rt286_regmap);
  966. if (IS_ERR(rt286->regmap)) {
  967. ret = PTR_ERR(rt286->regmap);
  968. dev_err(&i2c->dev, "Failed to allocate register map: %d\n",
  969. ret);
  970. return ret;
  971. }
  972. regmap_read(rt286->regmap,
  973. RT286_GET_PARAM(AC_NODE_ROOT, AC_PAR_VENDOR_ID), &ret);
  974. if (ret != RT286_VENDOR_ID) {
  975. dev_err(&i2c->dev,
  976. "Device with ID register %x is not rt286\n", ret);
  977. return -ENODEV;
  978. }
  979. rt286->index_cache = rt286_index_def;
  980. rt286->i2c = i2c;
  981. i2c_set_clientdata(i2c, rt286);
  982. if (pdata)
  983. rt286->pdata = *pdata;
  984. regmap_write(rt286->regmap, RT286_SET_AUDIO_POWER, AC_PWRST_D3);
  985. for (i = 0; i < RT286_POWER_REG_LEN; i++)
  986. regmap_write(rt286->regmap,
  987. RT286_SET_POWER(rt286_support_power_controls[i]),
  988. AC_PWRST_D1);
  989. if (!rt286->pdata.cbj_en) {
  990. regmap_write(rt286->regmap, RT286_CBJ_CTRL2, 0x0000);
  991. regmap_write(rt286->regmap, RT286_MIC1_DET_CTRL, 0x0816);
  992. regmap_write(rt286->regmap, RT286_MISC_CTRL1, 0x0000);
  993. regmap_update_bits(rt286->regmap,
  994. RT286_CBJ_CTRL1, 0xf000, 0xb000);
  995. } else {
  996. regmap_update_bits(rt286->regmap,
  997. RT286_CBJ_CTRL1, 0xf000, 0x5000);
  998. }
  999. mdelay(10);
  1000. if (!rt286->pdata.gpio2_en)
  1001. regmap_write(rt286->regmap, RT286_SET_DMIC2_DEFAULT, 0x4000);
  1002. else
  1003. regmap_write(rt286->regmap, RT286_SET_DMIC2_DEFAULT, 0);
  1004. mdelay(10);
  1005. /*Power down LDO2*/
  1006. regmap_update_bits(rt286->regmap, RT286_POWER_CTRL2, 0x8, 0x0);
  1007. /*Set depop parameter*/
  1008. regmap_update_bits(rt286->regmap, RT286_DEPOP_CTRL2, 0x403a, 0x401a);
  1009. regmap_update_bits(rt286->regmap, RT286_DEPOP_CTRL3, 0xf777, 0x4737);
  1010. regmap_update_bits(rt286->regmap, RT286_DEPOP_CTRL4, 0x00ff, 0x003f);
  1011. if (rt286->i2c->irq) {
  1012. ret = request_threaded_irq(rt286->i2c->irq, NULL, rt286_irq,
  1013. IRQF_TRIGGER_HIGH | IRQF_ONESHOT, "rt286", rt286);
  1014. if (ret != 0) {
  1015. dev_err(&i2c->dev,
  1016. "Failed to reguest IRQ: %d\n", ret);
  1017. return ret;
  1018. }
  1019. }
  1020. ret = snd_soc_register_codec(&i2c->dev, &soc_codec_dev_rt286,
  1021. rt286_dai, ARRAY_SIZE(rt286_dai));
  1022. return ret;
  1023. }
  1024. static int rt286_i2c_remove(struct i2c_client *i2c)
  1025. {
  1026. struct rt286_priv *rt286 = i2c_get_clientdata(i2c);
  1027. if (i2c->irq)
  1028. free_irq(i2c->irq, rt286);
  1029. snd_soc_unregister_codec(&i2c->dev);
  1030. return 0;
  1031. }
  1032. static struct i2c_driver rt286_i2c_driver = {
  1033. .driver = {
  1034. .name = "rt286",
  1035. .owner = THIS_MODULE,
  1036. .acpi_match_table = ACPI_PTR(rt286_acpi_match),
  1037. },
  1038. .probe = rt286_i2c_probe,
  1039. .remove = rt286_i2c_remove,
  1040. .id_table = rt286_i2c_id,
  1041. };
  1042. module_i2c_driver(rt286_i2c_driver);
  1043. MODULE_DESCRIPTION("ASoC RT286 driver");
  1044. MODULE_AUTHOR("Bard Liao <bardliao@realtek.com>");
  1045. MODULE_LICENSE("GPL");