wm8804.c 19 KB

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  1. /*
  2. * wm8804.c -- WM8804 S/PDIF transceiver driver
  3. *
  4. * Copyright 2010-11 Wolfson Microelectronics plc
  5. *
  6. * Author: Dimitris Papastamos <dp@opensource.wolfsonmicro.com>
  7. *
  8. * This program is free software; you can redistribute it and/or modify
  9. * it under the terms of the GNU General Public License version 2 as
  10. * published by the Free Software Foundation.
  11. */
  12. #include <linux/module.h>
  13. #include <linux/moduleparam.h>
  14. #include <linux/init.h>
  15. #include <linux/delay.h>
  16. #include <linux/pm.h>
  17. #include <linux/i2c.h>
  18. #include <linux/of_device.h>
  19. #include <linux/spi/spi.h>
  20. #include <linux/regmap.h>
  21. #include <linux/regulator/consumer.h>
  22. #include <linux/slab.h>
  23. #include <sound/core.h>
  24. #include <sound/pcm.h>
  25. #include <sound/pcm_params.h>
  26. #include <sound/soc.h>
  27. #include <sound/initval.h>
  28. #include <sound/tlv.h>
  29. #include "wm8804.h"
  30. #define WM8804_NUM_SUPPLIES 2
  31. static const char *wm8804_supply_names[WM8804_NUM_SUPPLIES] = {
  32. "PVDD",
  33. "DVDD"
  34. };
  35. static const struct reg_default wm8804_reg_defaults[] = {
  36. { 3, 0x21 }, /* R3 - PLL1 */
  37. { 4, 0xFD }, /* R4 - PLL2 */
  38. { 5, 0x36 }, /* R5 - PLL3 */
  39. { 6, 0x07 }, /* R6 - PLL4 */
  40. { 7, 0x16 }, /* R7 - PLL5 */
  41. { 8, 0x18 }, /* R8 - PLL6 */
  42. { 9, 0xFF }, /* R9 - SPDMODE */
  43. { 10, 0x00 }, /* R10 - INTMASK */
  44. { 18, 0x00 }, /* R18 - SPDTX1 */
  45. { 19, 0x00 }, /* R19 - SPDTX2 */
  46. { 20, 0x00 }, /* R20 - SPDTX3 */
  47. { 21, 0x71 }, /* R21 - SPDTX4 */
  48. { 22, 0x0B }, /* R22 - SPDTX5 */
  49. { 23, 0x70 }, /* R23 - GPO0 */
  50. { 24, 0x57 }, /* R24 - GPO1 */
  51. { 26, 0x42 }, /* R26 - GPO2 */
  52. { 27, 0x06 }, /* R27 - AIFTX */
  53. { 28, 0x06 }, /* R28 - AIFRX */
  54. { 29, 0x80 }, /* R29 - SPDRX1 */
  55. { 30, 0x07 }, /* R30 - PWRDN */
  56. };
  57. struct wm8804_priv {
  58. struct regmap *regmap;
  59. struct regulator_bulk_data supplies[WM8804_NUM_SUPPLIES];
  60. struct notifier_block disable_nb[WM8804_NUM_SUPPLIES];
  61. int mclk_div;
  62. };
  63. static int txsrc_get(struct snd_kcontrol *kcontrol,
  64. struct snd_ctl_elem_value *ucontrol);
  65. static int txsrc_put(struct snd_kcontrol *kcontrol,
  66. struct snd_ctl_elem_value *ucontrol);
  67. /*
  68. * We can't use the same notifier block for more than one supply and
  69. * there's no way I can see to get from a callback to the caller
  70. * except container_of().
  71. */
  72. #define WM8804_REGULATOR_EVENT(n) \
  73. static int wm8804_regulator_event_##n(struct notifier_block *nb, \
  74. unsigned long event, void *data) \
  75. { \
  76. struct wm8804_priv *wm8804 = container_of(nb, struct wm8804_priv, \
  77. disable_nb[n]); \
  78. if (event & REGULATOR_EVENT_DISABLE) { \
  79. regcache_mark_dirty(wm8804->regmap); \
  80. } \
  81. return 0; \
  82. }
  83. WM8804_REGULATOR_EVENT(0)
  84. WM8804_REGULATOR_EVENT(1)
  85. static const char *txsrc_text[] = { "S/PDIF RX", "AIF" };
  86. static SOC_ENUM_SINGLE_EXT_DECL(txsrc, txsrc_text);
  87. static const struct snd_kcontrol_new wm8804_snd_controls[] = {
  88. SOC_ENUM_EXT("Input Source", txsrc, txsrc_get, txsrc_put),
  89. SOC_SINGLE("TX Playback Switch", WM8804_PWRDN, 2, 1, 1),
  90. SOC_SINGLE("AIF Playback Switch", WM8804_PWRDN, 4, 1, 1)
  91. };
  92. static int txsrc_get(struct snd_kcontrol *kcontrol,
  93. struct snd_ctl_elem_value *ucontrol)
  94. {
  95. struct snd_soc_codec *codec;
  96. unsigned int src;
  97. codec = snd_soc_kcontrol_codec(kcontrol);
  98. src = snd_soc_read(codec, WM8804_SPDTX4);
  99. if (src & 0x40)
  100. ucontrol->value.integer.value[0] = 1;
  101. else
  102. ucontrol->value.integer.value[0] = 0;
  103. return 0;
  104. }
  105. static int txsrc_put(struct snd_kcontrol *kcontrol,
  106. struct snd_ctl_elem_value *ucontrol)
  107. {
  108. struct snd_soc_codec *codec;
  109. unsigned int src, txpwr;
  110. codec = snd_soc_kcontrol_codec(kcontrol);
  111. if (ucontrol->value.integer.value[0] != 0
  112. && ucontrol->value.integer.value[0] != 1)
  113. return -EINVAL;
  114. src = snd_soc_read(codec, WM8804_SPDTX4);
  115. switch ((src & 0x40) >> 6) {
  116. case 0:
  117. if (!ucontrol->value.integer.value[0])
  118. return 0;
  119. break;
  120. case 1:
  121. if (ucontrol->value.integer.value[1])
  122. return 0;
  123. break;
  124. }
  125. /* save the current power state of the transmitter */
  126. txpwr = snd_soc_read(codec, WM8804_PWRDN) & 0x4;
  127. /* power down the transmitter */
  128. snd_soc_update_bits(codec, WM8804_PWRDN, 0x4, 0x4);
  129. /* set the tx source */
  130. snd_soc_update_bits(codec, WM8804_SPDTX4, 0x40,
  131. ucontrol->value.integer.value[0] << 6);
  132. if (ucontrol->value.integer.value[0]) {
  133. /* power down the receiver */
  134. snd_soc_update_bits(codec, WM8804_PWRDN, 0x2, 0x2);
  135. /* power up the AIF */
  136. snd_soc_update_bits(codec, WM8804_PWRDN, 0x10, 0);
  137. } else {
  138. /* don't power down the AIF -- may be used as an output */
  139. /* power up the receiver */
  140. snd_soc_update_bits(codec, WM8804_PWRDN, 0x2, 0);
  141. }
  142. /* restore the transmitter's configuration */
  143. snd_soc_update_bits(codec, WM8804_PWRDN, 0x4, txpwr);
  144. return 0;
  145. }
  146. static bool wm8804_volatile(struct device *dev, unsigned int reg)
  147. {
  148. switch (reg) {
  149. case WM8804_RST_DEVID1:
  150. case WM8804_DEVID2:
  151. case WM8804_DEVREV:
  152. case WM8804_INTSTAT:
  153. case WM8804_SPDSTAT:
  154. case WM8804_RXCHAN1:
  155. case WM8804_RXCHAN2:
  156. case WM8804_RXCHAN3:
  157. case WM8804_RXCHAN4:
  158. case WM8804_RXCHAN5:
  159. return true;
  160. default:
  161. return false;
  162. }
  163. }
  164. static int wm8804_reset(struct snd_soc_codec *codec)
  165. {
  166. return snd_soc_write(codec, WM8804_RST_DEVID1, 0x0);
  167. }
  168. static int wm8804_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
  169. {
  170. struct snd_soc_codec *codec;
  171. u16 format, master, bcp, lrp;
  172. codec = dai->codec;
  173. switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
  174. case SND_SOC_DAIFMT_I2S:
  175. format = 0x2;
  176. break;
  177. case SND_SOC_DAIFMT_RIGHT_J:
  178. format = 0x0;
  179. break;
  180. case SND_SOC_DAIFMT_LEFT_J:
  181. format = 0x1;
  182. break;
  183. case SND_SOC_DAIFMT_DSP_A:
  184. case SND_SOC_DAIFMT_DSP_B:
  185. format = 0x3;
  186. break;
  187. default:
  188. dev_err(dai->dev, "Unknown dai format\n");
  189. return -EINVAL;
  190. }
  191. /* set data format */
  192. snd_soc_update_bits(codec, WM8804_AIFTX, 0x3, format);
  193. snd_soc_update_bits(codec, WM8804_AIFRX, 0x3, format);
  194. switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
  195. case SND_SOC_DAIFMT_CBM_CFM:
  196. master = 1;
  197. break;
  198. case SND_SOC_DAIFMT_CBS_CFS:
  199. master = 0;
  200. break;
  201. default:
  202. dev_err(dai->dev, "Unknown master/slave configuration\n");
  203. return -EINVAL;
  204. }
  205. /* set master/slave mode */
  206. snd_soc_update_bits(codec, WM8804_AIFRX, 0x40, master << 6);
  207. bcp = lrp = 0;
  208. switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
  209. case SND_SOC_DAIFMT_NB_NF:
  210. break;
  211. case SND_SOC_DAIFMT_IB_IF:
  212. bcp = lrp = 1;
  213. break;
  214. case SND_SOC_DAIFMT_IB_NF:
  215. bcp = 1;
  216. break;
  217. case SND_SOC_DAIFMT_NB_IF:
  218. lrp = 1;
  219. break;
  220. default:
  221. dev_err(dai->dev, "Unknown polarity configuration\n");
  222. return -EINVAL;
  223. }
  224. /* set frame inversion */
  225. snd_soc_update_bits(codec, WM8804_AIFTX, 0x10 | 0x20,
  226. (bcp << 4) | (lrp << 5));
  227. snd_soc_update_bits(codec, WM8804_AIFRX, 0x10 | 0x20,
  228. (bcp << 4) | (lrp << 5));
  229. return 0;
  230. }
  231. static int wm8804_hw_params(struct snd_pcm_substream *substream,
  232. struct snd_pcm_hw_params *params,
  233. struct snd_soc_dai *dai)
  234. {
  235. struct snd_soc_codec *codec;
  236. u16 blen;
  237. codec = dai->codec;
  238. switch (params_width(params)) {
  239. case 16:
  240. blen = 0x0;
  241. break;
  242. case 20:
  243. blen = 0x1;
  244. break;
  245. case 24:
  246. blen = 0x2;
  247. break;
  248. default:
  249. dev_err(dai->dev, "Unsupported word length: %u\n",
  250. params_width(params));
  251. return -EINVAL;
  252. }
  253. /* set word length */
  254. snd_soc_update_bits(codec, WM8804_AIFTX, 0xc, blen << 2);
  255. snd_soc_update_bits(codec, WM8804_AIFRX, 0xc, blen << 2);
  256. return 0;
  257. }
  258. struct pll_div {
  259. u32 prescale:1;
  260. u32 mclkdiv:1;
  261. u32 freqmode:2;
  262. u32 n:4;
  263. u32 k:22;
  264. };
  265. /* PLL rate to output rate divisions */
  266. static struct {
  267. unsigned int div;
  268. unsigned int freqmode;
  269. unsigned int mclkdiv;
  270. } post_table[] = {
  271. { 2, 0, 0 },
  272. { 4, 0, 1 },
  273. { 4, 1, 0 },
  274. { 8, 1, 1 },
  275. { 8, 2, 0 },
  276. { 16, 2, 1 },
  277. { 12, 3, 0 },
  278. { 24, 3, 1 }
  279. };
  280. #define FIXED_PLL_SIZE ((1ULL << 22) * 10)
  281. static int pll_factors(struct pll_div *pll_div, unsigned int target,
  282. unsigned int source, unsigned int mclk_div)
  283. {
  284. u64 Kpart;
  285. unsigned long int K, Ndiv, Nmod, tmp;
  286. int i;
  287. /*
  288. * Scale the output frequency up; the PLL should run in the
  289. * region of 90-100MHz.
  290. */
  291. for (i = 0; i < ARRAY_SIZE(post_table); i++) {
  292. tmp = target * post_table[i].div;
  293. if ((tmp >= 90000000 && tmp <= 100000000) &&
  294. (mclk_div == post_table[i].mclkdiv)) {
  295. pll_div->freqmode = post_table[i].freqmode;
  296. pll_div->mclkdiv = post_table[i].mclkdiv;
  297. target *= post_table[i].div;
  298. break;
  299. }
  300. }
  301. if (i == ARRAY_SIZE(post_table)) {
  302. pr_err("%s: Unable to scale output frequency: %uHz\n",
  303. __func__, target);
  304. return -EINVAL;
  305. }
  306. pll_div->prescale = 0;
  307. Ndiv = target / source;
  308. if (Ndiv < 5) {
  309. source >>= 1;
  310. pll_div->prescale = 1;
  311. Ndiv = target / source;
  312. }
  313. if (Ndiv < 5 || Ndiv > 13) {
  314. pr_err("%s: WM8804 N value is not within the recommended range: %lu\n",
  315. __func__, Ndiv);
  316. return -EINVAL;
  317. }
  318. pll_div->n = Ndiv;
  319. Nmod = target % source;
  320. Kpart = FIXED_PLL_SIZE * (u64)Nmod;
  321. do_div(Kpart, source);
  322. K = Kpart & 0xffffffff;
  323. if ((K % 10) >= 5)
  324. K += 5;
  325. K /= 10;
  326. pll_div->k = K;
  327. return 0;
  328. }
  329. static int wm8804_set_pll(struct snd_soc_dai *dai, int pll_id,
  330. int source, unsigned int freq_in,
  331. unsigned int freq_out)
  332. {
  333. struct snd_soc_codec *codec;
  334. codec = dai->codec;
  335. if (!freq_in || !freq_out) {
  336. /* disable the PLL */
  337. snd_soc_update_bits(codec, WM8804_PWRDN, 0x1, 0x1);
  338. return 0;
  339. } else {
  340. int ret;
  341. struct pll_div pll_div;
  342. struct wm8804_priv *wm8804;
  343. wm8804 = snd_soc_codec_get_drvdata(codec);
  344. ret = pll_factors(&pll_div, freq_out, freq_in,
  345. wm8804->mclk_div);
  346. if (ret)
  347. return ret;
  348. /* power down the PLL before reprogramming it */
  349. snd_soc_update_bits(codec, WM8804_PWRDN, 0x1, 0x1);
  350. /* set PLLN and PRESCALE */
  351. snd_soc_update_bits(codec, WM8804_PLL4, 0xf | 0x10,
  352. pll_div.n | (pll_div.prescale << 4));
  353. /* set mclkdiv and freqmode */
  354. snd_soc_update_bits(codec, WM8804_PLL5, 0x3 | 0x8,
  355. pll_div.freqmode | (pll_div.mclkdiv << 3));
  356. /* set PLLK */
  357. snd_soc_write(codec, WM8804_PLL1, pll_div.k & 0xff);
  358. snd_soc_write(codec, WM8804_PLL2, (pll_div.k >> 8) & 0xff);
  359. snd_soc_write(codec, WM8804_PLL3, pll_div.k >> 16);
  360. /* power up the PLL */
  361. snd_soc_update_bits(codec, WM8804_PWRDN, 0x1, 0);
  362. }
  363. return 0;
  364. }
  365. static int wm8804_set_sysclk(struct snd_soc_dai *dai,
  366. int clk_id, unsigned int freq, int dir)
  367. {
  368. struct snd_soc_codec *codec;
  369. codec = dai->codec;
  370. switch (clk_id) {
  371. case WM8804_TX_CLKSRC_MCLK:
  372. if ((freq >= 10000000 && freq <= 14400000)
  373. || (freq >= 16280000 && freq <= 27000000))
  374. snd_soc_update_bits(codec, WM8804_PLL6, 0x80, 0x80);
  375. else {
  376. dev_err(dai->dev, "OSCCLOCK is not within the "
  377. "recommended range: %uHz\n", freq);
  378. return -EINVAL;
  379. }
  380. break;
  381. case WM8804_TX_CLKSRC_PLL:
  382. snd_soc_update_bits(codec, WM8804_PLL6, 0x80, 0);
  383. break;
  384. case WM8804_CLKOUT_SRC_CLK1:
  385. snd_soc_update_bits(codec, WM8804_PLL6, 0x8, 0);
  386. break;
  387. case WM8804_CLKOUT_SRC_OSCCLK:
  388. snd_soc_update_bits(codec, WM8804_PLL6, 0x8, 0x8);
  389. break;
  390. default:
  391. dev_err(dai->dev, "Unknown clock source: %d\n", clk_id);
  392. return -EINVAL;
  393. }
  394. return 0;
  395. }
  396. static int wm8804_set_clkdiv(struct snd_soc_dai *dai,
  397. int div_id, int div)
  398. {
  399. struct snd_soc_codec *codec;
  400. struct wm8804_priv *wm8804;
  401. codec = dai->codec;
  402. switch (div_id) {
  403. case WM8804_CLKOUT_DIV:
  404. snd_soc_update_bits(codec, WM8804_PLL5, 0x30,
  405. (div & 0x3) << 4);
  406. break;
  407. case WM8804_MCLK_DIV:
  408. wm8804 = snd_soc_codec_get_drvdata(codec);
  409. wm8804->mclk_div = div;
  410. break;
  411. default:
  412. dev_err(dai->dev, "Unknown clock divider: %d\n", div_id);
  413. return -EINVAL;
  414. }
  415. return 0;
  416. }
  417. static int wm8804_set_bias_level(struct snd_soc_codec *codec,
  418. enum snd_soc_bias_level level)
  419. {
  420. int ret;
  421. struct wm8804_priv *wm8804;
  422. wm8804 = snd_soc_codec_get_drvdata(codec);
  423. switch (level) {
  424. case SND_SOC_BIAS_ON:
  425. break;
  426. case SND_SOC_BIAS_PREPARE:
  427. /* power up the OSC and the PLL */
  428. snd_soc_update_bits(codec, WM8804_PWRDN, 0x9, 0);
  429. break;
  430. case SND_SOC_BIAS_STANDBY:
  431. if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) {
  432. ret = regulator_bulk_enable(ARRAY_SIZE(wm8804->supplies),
  433. wm8804->supplies);
  434. if (ret) {
  435. dev_err(codec->dev,
  436. "Failed to enable supplies: %d\n",
  437. ret);
  438. return ret;
  439. }
  440. regcache_sync(wm8804->regmap);
  441. }
  442. /* power down the OSC and the PLL */
  443. snd_soc_update_bits(codec, WM8804_PWRDN, 0x9, 0x9);
  444. break;
  445. case SND_SOC_BIAS_OFF:
  446. /* power down the OSC and the PLL */
  447. snd_soc_update_bits(codec, WM8804_PWRDN, 0x9, 0x9);
  448. regulator_bulk_disable(ARRAY_SIZE(wm8804->supplies),
  449. wm8804->supplies);
  450. break;
  451. }
  452. codec->dapm.bias_level = level;
  453. return 0;
  454. }
  455. static int wm8804_remove(struct snd_soc_codec *codec)
  456. {
  457. struct wm8804_priv *wm8804;
  458. int i;
  459. wm8804 = snd_soc_codec_get_drvdata(codec);
  460. wm8804_set_bias_level(codec, SND_SOC_BIAS_OFF);
  461. for (i = 0; i < ARRAY_SIZE(wm8804->supplies); ++i)
  462. regulator_unregister_notifier(wm8804->supplies[i].consumer,
  463. &wm8804->disable_nb[i]);
  464. return 0;
  465. }
  466. static int wm8804_probe(struct snd_soc_codec *codec)
  467. {
  468. struct wm8804_priv *wm8804;
  469. int i, id1, id2, ret;
  470. wm8804 = snd_soc_codec_get_drvdata(codec);
  471. for (i = 0; i < ARRAY_SIZE(wm8804->supplies); i++)
  472. wm8804->supplies[i].supply = wm8804_supply_names[i];
  473. ret = devm_regulator_bulk_get(codec->dev, ARRAY_SIZE(wm8804->supplies),
  474. wm8804->supplies);
  475. if (ret) {
  476. dev_err(codec->dev, "Failed to request supplies: %d\n", ret);
  477. return ret;
  478. }
  479. wm8804->disable_nb[0].notifier_call = wm8804_regulator_event_0;
  480. wm8804->disable_nb[1].notifier_call = wm8804_regulator_event_1;
  481. /* This should really be moved into the regulator core */
  482. for (i = 0; i < ARRAY_SIZE(wm8804->supplies); i++) {
  483. ret = regulator_register_notifier(wm8804->supplies[i].consumer,
  484. &wm8804->disable_nb[i]);
  485. if (ret != 0) {
  486. dev_err(codec->dev,
  487. "Failed to register regulator notifier: %d\n",
  488. ret);
  489. }
  490. }
  491. ret = regulator_bulk_enable(ARRAY_SIZE(wm8804->supplies),
  492. wm8804->supplies);
  493. if (ret) {
  494. dev_err(codec->dev, "Failed to enable supplies: %d\n", ret);
  495. return ret;
  496. }
  497. id1 = snd_soc_read(codec, WM8804_RST_DEVID1);
  498. if (id1 < 0) {
  499. dev_err(codec->dev, "Failed to read device ID: %d\n", id1);
  500. ret = id1;
  501. goto err_reg_enable;
  502. }
  503. id2 = snd_soc_read(codec, WM8804_DEVID2);
  504. if (id2 < 0) {
  505. dev_err(codec->dev, "Failed to read device ID: %d\n", id2);
  506. ret = id2;
  507. goto err_reg_enable;
  508. }
  509. id2 = (id2 << 8) | id1;
  510. if (id2 != 0x8805) {
  511. dev_err(codec->dev, "Invalid device ID: %#x\n", id2);
  512. ret = -EINVAL;
  513. goto err_reg_enable;
  514. }
  515. ret = snd_soc_read(codec, WM8804_DEVREV);
  516. if (ret < 0) {
  517. dev_err(codec->dev, "Failed to read device revision: %d\n",
  518. ret);
  519. goto err_reg_enable;
  520. }
  521. dev_info(codec->dev, "revision %c\n", ret + 'A');
  522. ret = wm8804_reset(codec);
  523. if (ret < 0) {
  524. dev_err(codec->dev, "Failed to issue reset: %d\n", ret);
  525. goto err_reg_enable;
  526. }
  527. wm8804_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
  528. return 0;
  529. err_reg_enable:
  530. regulator_bulk_disable(ARRAY_SIZE(wm8804->supplies), wm8804->supplies);
  531. return ret;
  532. }
  533. static const struct snd_soc_dai_ops wm8804_dai_ops = {
  534. .hw_params = wm8804_hw_params,
  535. .set_fmt = wm8804_set_fmt,
  536. .set_sysclk = wm8804_set_sysclk,
  537. .set_clkdiv = wm8804_set_clkdiv,
  538. .set_pll = wm8804_set_pll
  539. };
  540. #define WM8804_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \
  541. SNDRV_PCM_FMTBIT_S24_LE)
  542. #define WM8804_RATES (SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 | \
  543. SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_64000 | \
  544. SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000 | \
  545. SNDRV_PCM_RATE_176400 | SNDRV_PCM_RATE_192000)
  546. static struct snd_soc_dai_driver wm8804_dai = {
  547. .name = "wm8804-spdif",
  548. .playback = {
  549. .stream_name = "Playback",
  550. .channels_min = 2,
  551. .channels_max = 2,
  552. .rates = WM8804_RATES,
  553. .formats = WM8804_FORMATS,
  554. },
  555. .capture = {
  556. .stream_name = "Capture",
  557. .channels_min = 2,
  558. .channels_max = 2,
  559. .rates = WM8804_RATES,
  560. .formats = WM8804_FORMATS,
  561. },
  562. .ops = &wm8804_dai_ops,
  563. .symmetric_rates = 1
  564. };
  565. static struct snd_soc_codec_driver soc_codec_dev_wm8804 = {
  566. .probe = wm8804_probe,
  567. .remove = wm8804_remove,
  568. .set_bias_level = wm8804_set_bias_level,
  569. .idle_bias_off = true,
  570. .controls = wm8804_snd_controls,
  571. .num_controls = ARRAY_SIZE(wm8804_snd_controls),
  572. };
  573. static const struct of_device_id wm8804_of_match[] = {
  574. { .compatible = "wlf,wm8804", },
  575. { }
  576. };
  577. MODULE_DEVICE_TABLE(of, wm8804_of_match);
  578. static struct regmap_config wm8804_regmap_config = {
  579. .reg_bits = 8,
  580. .val_bits = 8,
  581. .max_register = WM8804_MAX_REGISTER,
  582. .volatile_reg = wm8804_volatile,
  583. .cache_type = REGCACHE_RBTREE,
  584. .reg_defaults = wm8804_reg_defaults,
  585. .num_reg_defaults = ARRAY_SIZE(wm8804_reg_defaults),
  586. };
  587. #if defined(CONFIG_SPI_MASTER)
  588. static int wm8804_spi_probe(struct spi_device *spi)
  589. {
  590. struct wm8804_priv *wm8804;
  591. int ret;
  592. wm8804 = devm_kzalloc(&spi->dev, sizeof *wm8804, GFP_KERNEL);
  593. if (!wm8804)
  594. return -ENOMEM;
  595. wm8804->regmap = devm_regmap_init_spi(spi, &wm8804_regmap_config);
  596. if (IS_ERR(wm8804->regmap)) {
  597. ret = PTR_ERR(wm8804->regmap);
  598. return ret;
  599. }
  600. spi_set_drvdata(spi, wm8804);
  601. ret = snd_soc_register_codec(&spi->dev,
  602. &soc_codec_dev_wm8804, &wm8804_dai, 1);
  603. return ret;
  604. }
  605. static int wm8804_spi_remove(struct spi_device *spi)
  606. {
  607. snd_soc_unregister_codec(&spi->dev);
  608. return 0;
  609. }
  610. static struct spi_driver wm8804_spi_driver = {
  611. .driver = {
  612. .name = "wm8804",
  613. .owner = THIS_MODULE,
  614. .of_match_table = wm8804_of_match,
  615. },
  616. .probe = wm8804_spi_probe,
  617. .remove = wm8804_spi_remove
  618. };
  619. #endif
  620. #if IS_ENABLED(CONFIG_I2C)
  621. static int wm8804_i2c_probe(struct i2c_client *i2c,
  622. const struct i2c_device_id *id)
  623. {
  624. struct wm8804_priv *wm8804;
  625. int ret;
  626. wm8804 = devm_kzalloc(&i2c->dev, sizeof *wm8804, GFP_KERNEL);
  627. if (!wm8804)
  628. return -ENOMEM;
  629. wm8804->regmap = devm_regmap_init_i2c(i2c, &wm8804_regmap_config);
  630. if (IS_ERR(wm8804->regmap)) {
  631. ret = PTR_ERR(wm8804->regmap);
  632. return ret;
  633. }
  634. i2c_set_clientdata(i2c, wm8804);
  635. ret = snd_soc_register_codec(&i2c->dev,
  636. &soc_codec_dev_wm8804, &wm8804_dai, 1);
  637. return ret;
  638. }
  639. static int wm8804_i2c_remove(struct i2c_client *i2c)
  640. {
  641. snd_soc_unregister_codec(&i2c->dev);
  642. return 0;
  643. }
  644. static const struct i2c_device_id wm8804_i2c_id[] = {
  645. { "wm8804", 0 },
  646. { }
  647. };
  648. MODULE_DEVICE_TABLE(i2c, wm8804_i2c_id);
  649. static struct i2c_driver wm8804_i2c_driver = {
  650. .driver = {
  651. .name = "wm8804",
  652. .owner = THIS_MODULE,
  653. .of_match_table = wm8804_of_match,
  654. },
  655. .probe = wm8804_i2c_probe,
  656. .remove = wm8804_i2c_remove,
  657. .id_table = wm8804_i2c_id
  658. };
  659. #endif
  660. static int __init wm8804_modinit(void)
  661. {
  662. int ret = 0;
  663. #if IS_ENABLED(CONFIG_I2C)
  664. ret = i2c_add_driver(&wm8804_i2c_driver);
  665. if (ret) {
  666. printk(KERN_ERR "Failed to register wm8804 I2C driver: %d\n",
  667. ret);
  668. }
  669. #endif
  670. #if defined(CONFIG_SPI_MASTER)
  671. ret = spi_register_driver(&wm8804_spi_driver);
  672. if (ret != 0) {
  673. printk(KERN_ERR "Failed to register wm8804 SPI driver: %d\n",
  674. ret);
  675. }
  676. #endif
  677. return ret;
  678. }
  679. module_init(wm8804_modinit);
  680. static void __exit wm8804_exit(void)
  681. {
  682. #if IS_ENABLED(CONFIG_I2C)
  683. i2c_del_driver(&wm8804_i2c_driver);
  684. #endif
  685. #if defined(CONFIG_SPI_MASTER)
  686. spi_unregister_driver(&wm8804_spi_driver);
  687. #endif
  688. }
  689. module_exit(wm8804_exit);
  690. MODULE_DESCRIPTION("ASoC WM8804 driver");
  691. MODULE_AUTHOR("Dimitris Papastamos <dp@opensource.wolfsonmicro.com>");
  692. MODULE_LICENSE("GPL");