clk-pll.h 2.1 KB

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  1. /*
  2. * Copyright (c) 2013 Samsung Electronics Co., Ltd.
  3. * Copyright (c) 2013 Linaro Ltd.
  4. *
  5. * This program is free software; you can redistribute it and/or modify
  6. * it under the terms of the GNU General Public License version 2 as
  7. * published by the Free Software Foundation.
  8. *
  9. * Common Clock Framework support for all PLL's in Samsung platforms
  10. */
  11. #ifndef __SAMSUNG_CLK_PLL_H
  12. #define __SAMSUNG_CLK_PLL_H
  13. enum samsung_pll_type {
  14. pll_2126,
  15. pll_3000,
  16. pll_35xx,
  17. pll_36xx,
  18. pll_2550,
  19. pll_2650,
  20. pll_4500,
  21. pll_4502,
  22. pll_4508,
  23. pll_4600,
  24. pll_4650,
  25. pll_4650c,
  26. pll_6552,
  27. pll_6552_s3c2416,
  28. pll_6553,
  29. pll_s3c2410_mpll,
  30. pll_s3c2410_upll,
  31. pll_s3c2440_mpll,
  32. pll_2550xx,
  33. pll_2650xx,
  34. };
  35. #define PLL_35XX_RATE(_rate, _m, _p, _s) \
  36. { \
  37. .rate = (_rate), \
  38. .mdiv = (_m), \
  39. .pdiv = (_p), \
  40. .sdiv = (_s), \
  41. }
  42. #define PLL_36XX_RATE(_rate, _m, _p, _s, _k) \
  43. { \
  44. .rate = (_rate), \
  45. .mdiv = (_m), \
  46. .pdiv = (_p), \
  47. .sdiv = (_s), \
  48. .kdiv = (_k), \
  49. }
  50. #define PLL_45XX_RATE(_rate, _m, _p, _s, _afc) \
  51. { \
  52. .rate = (_rate), \
  53. .mdiv = (_m), \
  54. .pdiv = (_p), \
  55. .sdiv = (_s), \
  56. .afc = (_afc), \
  57. }
  58. #define PLL_4600_RATE(_rate, _m, _p, _s, _k, _vsel) \
  59. { \
  60. .rate = (_rate), \
  61. .mdiv = (_m), \
  62. .pdiv = (_p), \
  63. .sdiv = (_s), \
  64. .kdiv = (_k), \
  65. .vsel = (_vsel), \
  66. }
  67. #define PLL_4650_RATE(_rate, _m, _p, _s, _k, _mfr, _mrr, _vsel) \
  68. { \
  69. .rate = (_rate), \
  70. .mdiv = (_m), \
  71. .pdiv = (_p), \
  72. .sdiv = (_s), \
  73. .kdiv = (_k), \
  74. .mfr = (_mfr), \
  75. .mrr = (_mrr), \
  76. .vsel = (_vsel), \
  77. }
  78. /* NOTE: Rate table should be kept sorted in descending order. */
  79. struct samsung_pll_rate_table {
  80. unsigned int rate;
  81. unsigned int pdiv;
  82. unsigned int mdiv;
  83. unsigned int sdiv;
  84. unsigned int kdiv;
  85. unsigned int afc;
  86. unsigned int mfr;
  87. unsigned int mrr;
  88. unsigned int vsel;
  89. };
  90. extern struct clk * __init samsung_clk_register_pll2550x(const char *name,
  91. const char *pname, const void __iomem *reg_base,
  92. const unsigned long offset);
  93. #endif /* __SAMSUNG_CLK_PLL_H */