qla_tmpl.c 26 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569570571572573574575576577578579580581582583584585586587588589590591592593594595596597598599600601602603604605606607608609610611612613614615616617618619620621622623624625626627628629630631632633634635636637638639640641642643644645646647648649650651652653654655656657658659660661662663664665666667668669670671672673674675676677678679680681682683684685686687688689690691692693694695696697698699700701702703704705706707708709710711712713714715716717718719720721722723724725726727728729730731732733734735736737738739740741742743744745746747748749750751752753754755756757758759760761762763764765766767768769770771772773774775776777778779780781782783784785786787788789790791792793794795796797798799800801802803804805806807808809810811812813814815816817818819820821822823824825826827828829830831832833834835836837838839840841842843844845846847848849850851852853854855856857858859860861862863864865866867868869870871872873874875876877878879880881882883884885886887888889890891892893894895896897898899900901902903904905906907908909910911912913914915916917918919920921922923924925926927928929930931932933934935936937938939940941942943944945946
  1. /*
  2. * QLogic Fibre Channel HBA Driver
  3. * Copyright (c) 2003-2014 QLogic Corporation
  4. *
  5. * See LICENSE.qla2xxx for copyright and licensing details.
  6. */
  7. #include "qla_def.h"
  8. #include "qla_tmpl.h"
  9. /* note default template is in big endian */
  10. static const uint32_t ql27xx_fwdt_default_template[] = {
  11. 0x63000000, 0xa4000000, 0x7c050000, 0x00000000,
  12. 0x30000000, 0x01000000, 0x00000000, 0xc0406eb4,
  13. 0x00000000, 0x00000000, 0x00000000, 0x00000000,
  14. 0x00000000, 0x00000000, 0x00000000, 0x00000000,
  15. 0x00000000, 0x00000000, 0x00000000, 0x00000000,
  16. 0x00000000, 0x00000000, 0x00000000, 0x00000000,
  17. 0x00000000, 0x00000000, 0x00000000, 0x00000000,
  18. 0x00000000, 0x00000000, 0x00000000, 0x00000000,
  19. 0x00000000, 0x00000000, 0x00000000, 0x00000000,
  20. 0x00000000, 0x00000000, 0x00000000, 0x00000000,
  21. 0x00000000, 0x04010000, 0x14000000, 0x00000000,
  22. 0x02000000, 0x44000000, 0x09010000, 0x10000000,
  23. 0x00000000, 0x02000000, 0x01010000, 0x1c000000,
  24. 0x00000000, 0x02000000, 0x00600000, 0x00000000,
  25. 0xc0000000, 0x01010000, 0x1c000000, 0x00000000,
  26. 0x02000000, 0x00600000, 0x00000000, 0xcc000000,
  27. 0x01010000, 0x1c000000, 0x00000000, 0x02000000,
  28. 0x10600000, 0x00000000, 0xd4000000, 0x01010000,
  29. 0x1c000000, 0x00000000, 0x02000000, 0x700f0000,
  30. 0x00000060, 0xf0000000, 0x00010000, 0x18000000,
  31. 0x00000000, 0x02000000, 0x00700000, 0x041000c0,
  32. 0x00010000, 0x18000000, 0x00000000, 0x02000000,
  33. 0x10700000, 0x041000c0, 0x00010000, 0x18000000,
  34. 0x00000000, 0x02000000, 0x40700000, 0x041000c0,
  35. 0x01010000, 0x1c000000, 0x00000000, 0x02000000,
  36. 0x007c0000, 0x01000000, 0xc0000000, 0x00010000,
  37. 0x18000000, 0x00000000, 0x02000000, 0x007c0000,
  38. 0x040300c4, 0x00010000, 0x18000000, 0x00000000,
  39. 0x02000000, 0x007c0000, 0x040100c0, 0x01010000,
  40. 0x1c000000, 0x00000000, 0x02000000, 0x007c0000,
  41. 0x00000000, 0xc0000000, 0x00010000, 0x18000000,
  42. 0x00000000, 0x02000000, 0x007c0000, 0x04200000,
  43. 0x0b010000, 0x18000000, 0x00000000, 0x02000000,
  44. 0x0c000000, 0x00000000, 0x02010000, 0x20000000,
  45. 0x00000000, 0x02000000, 0x700f0000, 0x040100fc,
  46. 0xf0000000, 0x000000b0, 0x02010000, 0x20000000,
  47. 0x00000000, 0x02000000, 0x700f0000, 0x040100fc,
  48. 0xf0000000, 0x000010b0, 0x02010000, 0x20000000,
  49. 0x00000000, 0x02000000, 0x700f0000, 0x040100fc,
  50. 0xf0000000, 0x000020b0, 0x02010000, 0x20000000,
  51. 0x00000000, 0x02000000, 0x700f0000, 0x040100fc,
  52. 0xf0000000, 0x000030b0, 0x02010000, 0x20000000,
  53. 0x00000000, 0x02000000, 0x700f0000, 0x040100fc,
  54. 0xf0000000, 0x000040b0, 0x02010000, 0x20000000,
  55. 0x00000000, 0x02000000, 0x700f0000, 0x040100fc,
  56. 0xf0000000, 0x000050b0, 0x02010000, 0x20000000,
  57. 0x00000000, 0x02000000, 0x700f0000, 0x040100fc,
  58. 0xf0000000, 0x000060b0, 0x02010000, 0x20000000,
  59. 0x00000000, 0x02000000, 0x700f0000, 0x040100fc,
  60. 0xf0000000, 0x000070b0, 0x02010000, 0x20000000,
  61. 0x00000000, 0x02000000, 0x700f0000, 0x040100fc,
  62. 0xf0000000, 0x000080b0, 0x02010000, 0x20000000,
  63. 0x00000000, 0x02000000, 0x700f0000, 0x040100fc,
  64. 0xf0000000, 0x000090b0, 0x02010000, 0x20000000,
  65. 0x00000000, 0x02000000, 0x700f0000, 0x040100fc,
  66. 0xf0000000, 0x0000a0b0, 0x00010000, 0x18000000,
  67. 0x00000000, 0x02000000, 0x0a000000, 0x040100c0,
  68. 0x00010000, 0x18000000, 0x00000000, 0x02000000,
  69. 0x0a000000, 0x04200080, 0x00010000, 0x18000000,
  70. 0x00000000, 0x02000000, 0x00be0000, 0x041000c0,
  71. 0x00010000, 0x18000000, 0x00000000, 0x02000000,
  72. 0x10be0000, 0x041000c0, 0x00010000, 0x18000000,
  73. 0x00000000, 0x02000000, 0x20be0000, 0x041000c0,
  74. 0x00010000, 0x18000000, 0x00000000, 0x02000000,
  75. 0x30be0000, 0x041000c0, 0x00010000, 0x18000000,
  76. 0x00000000, 0x02000000, 0x00b00000, 0x041000c0,
  77. 0x00010000, 0x18000000, 0x00000000, 0x02000000,
  78. 0x10b00000, 0x041000c0, 0x00010000, 0x18000000,
  79. 0x00000000, 0x02000000, 0x20b00000, 0x041000c0,
  80. 0x00010000, 0x18000000, 0x00000000, 0x02000000,
  81. 0x30b00000, 0x041000c0, 0x00010000, 0x18000000,
  82. 0x00000000, 0x02000000, 0x00300000, 0x041000c0,
  83. 0x00010000, 0x18000000, 0x00000000, 0x02000000,
  84. 0x10300000, 0x041000c0, 0x00010000, 0x18000000,
  85. 0x00000000, 0x02000000, 0x20300000, 0x041000c0,
  86. 0x00010000, 0x18000000, 0x00000000, 0x02000000,
  87. 0x30300000, 0x041000c0, 0x0a010000, 0x10000000,
  88. 0x00000000, 0x02000000, 0x06010000, 0x1c000000,
  89. 0x00000000, 0x02000000, 0x01000000, 0x00000200,
  90. 0xff230200, 0x06010000, 0x1c000000, 0x00000000,
  91. 0x02000000, 0x02000000, 0x00001000, 0x00000000,
  92. 0x07010000, 0x18000000, 0x00000000, 0x02000000,
  93. 0x00000000, 0x01000000, 0x07010000, 0x18000000,
  94. 0x00000000, 0x02000000, 0x00000000, 0x02000000,
  95. 0x07010000, 0x18000000, 0x00000000, 0x02000000,
  96. 0x00000000, 0x03000000, 0x0d010000, 0x14000000,
  97. 0x00000000, 0x02000000, 0x00000000, 0xff000000,
  98. 0x10000000, 0x00000000, 0x00000080,
  99. };
  100. static inline void __iomem *
  101. qla27xx_isp_reg(struct scsi_qla_host *vha)
  102. {
  103. return &vha->hw->iobase->isp24;
  104. }
  105. static inline void
  106. qla27xx_insert16(uint16_t value, void *buf, ulong *len)
  107. {
  108. if (buf) {
  109. buf += *len;
  110. *(__le16 *)buf = cpu_to_le16(value);
  111. }
  112. *len += sizeof(value);
  113. }
  114. static inline void
  115. qla27xx_insert32(uint32_t value, void *buf, ulong *len)
  116. {
  117. if (buf) {
  118. buf += *len;
  119. *(__le32 *)buf = cpu_to_le32(value);
  120. }
  121. *len += sizeof(value);
  122. }
  123. static inline void
  124. qla27xx_insertbuf(void *mem, ulong size, void *buf, ulong *len)
  125. {
  126. if (buf && mem && size) {
  127. buf += *len;
  128. memcpy(buf, mem, size);
  129. }
  130. *len += size;
  131. }
  132. static inline void
  133. qla27xx_read8(void *window, void *buf, ulong *len)
  134. {
  135. uint8_t value = ~0;
  136. if (buf) {
  137. value = RD_REG_BYTE((__iomem void *)window);
  138. }
  139. qla27xx_insert32(value, buf, len);
  140. }
  141. static inline void
  142. qla27xx_read16(void *window, void *buf, ulong *len)
  143. {
  144. uint16_t value = ~0;
  145. if (buf) {
  146. value = RD_REG_WORD((__iomem void *)window);
  147. }
  148. qla27xx_insert32(value, buf, len);
  149. }
  150. static inline void
  151. qla27xx_read32(void *window, void *buf, ulong *len)
  152. {
  153. uint32_t value = ~0;
  154. if (buf) {
  155. value = RD_REG_DWORD((__iomem void *)window);
  156. }
  157. qla27xx_insert32(value, buf, len);
  158. }
  159. static inline void (*qla27xx_read_vector(uint width))(void *, void *, ulong *)
  160. {
  161. return
  162. (width == 1) ? qla27xx_read8 :
  163. (width == 2) ? qla27xx_read16 :
  164. qla27xx_read32;
  165. }
  166. static inline void
  167. qla27xx_read_reg(__iomem struct device_reg_24xx *reg,
  168. uint offset, void *buf, ulong *len)
  169. {
  170. void *window = (void *)reg + offset;
  171. qla27xx_read32(window, buf, len);
  172. }
  173. static inline void
  174. qla27xx_write_reg(__iomem struct device_reg_24xx *reg,
  175. uint offset, uint32_t data, void *buf)
  176. {
  177. __iomem void *window = reg + offset;
  178. if (buf) {
  179. WRT_REG_DWORD(window, data);
  180. }
  181. }
  182. static inline void
  183. qla27xx_read_window(__iomem struct device_reg_24xx *reg,
  184. uint32_t addr, uint offset, uint count, uint width, void *buf,
  185. ulong *len)
  186. {
  187. void *window = (void *)reg + offset;
  188. void (*readn)(void *, void *, ulong *) = qla27xx_read_vector(width);
  189. qla27xx_write_reg(reg, IOBASE_ADDR, addr, buf);
  190. while (count--) {
  191. qla27xx_insert32(addr, buf, len);
  192. readn(window, buf, len);
  193. window += width;
  194. addr++;
  195. }
  196. }
  197. static inline void
  198. qla27xx_skip_entry(struct qla27xx_fwdt_entry *ent, void *buf)
  199. {
  200. if (buf)
  201. ent->hdr.driver_flags |= DRIVER_FLAG_SKIP_ENTRY;
  202. }
  203. static int
  204. qla27xx_fwdt_entry_t0(struct scsi_qla_host *vha,
  205. struct qla27xx_fwdt_entry *ent, void *buf, ulong *len)
  206. {
  207. ql_dbg(ql_dbg_misc, vha, 0xd100,
  208. "%s: nop [%lx]\n", __func__, *len);
  209. qla27xx_skip_entry(ent, buf);
  210. return false;
  211. }
  212. static int
  213. qla27xx_fwdt_entry_t255(struct scsi_qla_host *vha,
  214. struct qla27xx_fwdt_entry *ent, void *buf, ulong *len)
  215. {
  216. ql_dbg(ql_dbg_misc, vha, 0xd1ff,
  217. "%s: end [%lx]\n", __func__, *len);
  218. qla27xx_skip_entry(ent, buf);
  219. /* terminate */
  220. return true;
  221. }
  222. static int
  223. qla27xx_fwdt_entry_t256(struct scsi_qla_host *vha,
  224. struct qla27xx_fwdt_entry *ent, void *buf, ulong *len)
  225. {
  226. struct device_reg_24xx __iomem *reg = qla27xx_isp_reg(vha);
  227. ql_dbg(ql_dbg_misc, vha, 0xd200,
  228. "%s: rdio t1 [%lx]\n", __func__, *len);
  229. qla27xx_read_window(reg, ent->t256.base_addr, ent->t256.pci_offset,
  230. ent->t256.reg_count, ent->t256.reg_width, buf, len);
  231. return false;
  232. }
  233. static int
  234. qla27xx_fwdt_entry_t257(struct scsi_qla_host *vha,
  235. struct qla27xx_fwdt_entry *ent, void *buf, ulong *len)
  236. {
  237. struct device_reg_24xx __iomem *reg = qla27xx_isp_reg(vha);
  238. ql_dbg(ql_dbg_misc, vha, 0xd201,
  239. "%s: wrio t1 [%lx]\n", __func__, *len);
  240. qla27xx_write_reg(reg, IOBASE_ADDR, ent->t257.base_addr, buf);
  241. qla27xx_write_reg(reg, ent->t257.pci_offset, ent->t257.write_data, buf);
  242. return false;
  243. }
  244. static int
  245. qla27xx_fwdt_entry_t258(struct scsi_qla_host *vha,
  246. struct qla27xx_fwdt_entry *ent, void *buf, ulong *len)
  247. {
  248. struct device_reg_24xx __iomem *reg = qla27xx_isp_reg(vha);
  249. ql_dbg(ql_dbg_misc, vha, 0xd202,
  250. "%s: rdio t2 [%lx]\n", __func__, *len);
  251. qla27xx_write_reg(reg, ent->t258.banksel_offset, ent->t258.bank, buf);
  252. qla27xx_read_window(reg, ent->t258.base_addr, ent->t258.pci_offset,
  253. ent->t258.reg_count, ent->t258.reg_width, buf, len);
  254. return false;
  255. }
  256. static int
  257. qla27xx_fwdt_entry_t259(struct scsi_qla_host *vha,
  258. struct qla27xx_fwdt_entry *ent, void *buf, ulong *len)
  259. {
  260. struct device_reg_24xx __iomem *reg = qla27xx_isp_reg(vha);
  261. ql_dbg(ql_dbg_misc, vha, 0xd203,
  262. "%s: wrio t2 [%lx]\n", __func__, *len);
  263. qla27xx_write_reg(reg, IOBASE_ADDR, ent->t259.base_addr, buf);
  264. qla27xx_write_reg(reg, ent->t259.banksel_offset, ent->t259.bank, buf);
  265. qla27xx_write_reg(reg, ent->t259.pci_offset, ent->t259.write_data, buf);
  266. return false;
  267. }
  268. static int
  269. qla27xx_fwdt_entry_t260(struct scsi_qla_host *vha,
  270. struct qla27xx_fwdt_entry *ent, void *buf, ulong *len)
  271. {
  272. struct device_reg_24xx __iomem *reg = qla27xx_isp_reg(vha);
  273. ql_dbg(ql_dbg_misc, vha, 0xd204,
  274. "%s: rdpci [%lx]\n", __func__, *len);
  275. qla27xx_insert32(ent->t260.pci_offset, buf, len);
  276. qla27xx_read_reg(reg, ent->t260.pci_offset, buf, len);
  277. return false;
  278. }
  279. static int
  280. qla27xx_fwdt_entry_t261(struct scsi_qla_host *vha,
  281. struct qla27xx_fwdt_entry *ent, void *buf, ulong *len)
  282. {
  283. struct device_reg_24xx __iomem *reg = qla27xx_isp_reg(vha);
  284. ql_dbg(ql_dbg_misc, vha, 0xd205,
  285. "%s: wrpci [%lx]\n", __func__, *len);
  286. qla27xx_write_reg(reg, ent->t261.pci_offset, ent->t261.write_data, buf);
  287. return false;
  288. }
  289. static int
  290. qla27xx_fwdt_entry_t262(struct scsi_qla_host *vha,
  291. struct qla27xx_fwdt_entry *ent, void *buf, ulong *len)
  292. {
  293. ulong dwords;
  294. ulong start;
  295. ulong end;
  296. ql_dbg(ql_dbg_misc, vha, 0xd206,
  297. "%s: rdram(%x) [%lx]\n", __func__, ent->t262.ram_area, *len);
  298. start = ent->t262.start_addr;
  299. end = ent->t262.end_addr;
  300. if (ent->t262.ram_area == T262_RAM_AREA_CRITICAL_RAM) {
  301. ;
  302. } else if (ent->t262.ram_area == T262_RAM_AREA_EXTERNAL_RAM) {
  303. end = vha->hw->fw_memory_size;
  304. if (buf)
  305. ent->t262.end_addr = end;
  306. } else if (ent->t262.ram_area == T262_RAM_AREA_SHARED_RAM) {
  307. start = vha->hw->fw_shared_ram_start;
  308. end = vha->hw->fw_shared_ram_end;
  309. if (buf) {
  310. ent->t262.start_addr = start;
  311. ent->t262.end_addr = end;
  312. }
  313. } else {
  314. ql_dbg(ql_dbg_misc, vha, 0xd022,
  315. "%s: unknown area %x\n", __func__, ent->t262.ram_area);
  316. qla27xx_skip_entry(ent, buf);
  317. goto done;
  318. }
  319. if (end < start || end == 0) {
  320. ql_dbg(ql_dbg_misc, vha, 0xd023,
  321. "%s: unusable range (start=%x end=%x)\n", __func__,
  322. ent->t262.end_addr, ent->t262.start_addr);
  323. qla27xx_skip_entry(ent, buf);
  324. goto done;
  325. }
  326. dwords = end - start + 1;
  327. if (buf) {
  328. buf += *len;
  329. qla24xx_dump_ram(vha->hw, start, buf, dwords, &buf);
  330. }
  331. *len += dwords * sizeof(uint32_t);
  332. done:
  333. return false;
  334. }
  335. static int
  336. qla27xx_fwdt_entry_t263(struct scsi_qla_host *vha,
  337. struct qla27xx_fwdt_entry *ent, void *buf, ulong *len)
  338. {
  339. uint count = 0;
  340. uint i;
  341. uint length;
  342. ql_dbg(ql_dbg_misc, vha, 0xd207,
  343. "%s: getq(%x) [%lx]\n", __func__, ent->t263.queue_type, *len);
  344. if (ent->t263.queue_type == T263_QUEUE_TYPE_REQ) {
  345. for (i = 0; i < vha->hw->max_req_queues; i++) {
  346. struct req_que *req = vha->hw->req_q_map[i];
  347. if (req || !buf) {
  348. length = req ?
  349. req->length : REQUEST_ENTRY_CNT_24XX;
  350. qla27xx_insert16(i, buf, len);
  351. qla27xx_insert16(length, buf, len);
  352. qla27xx_insertbuf(req ? req->ring : NULL,
  353. length * sizeof(*req->ring), buf, len);
  354. count++;
  355. }
  356. }
  357. } else if (ent->t263.queue_type == T263_QUEUE_TYPE_RSP) {
  358. for (i = 0; i < vha->hw->max_rsp_queues; i++) {
  359. struct rsp_que *rsp = vha->hw->rsp_q_map[i];
  360. if (rsp || !buf) {
  361. length = rsp ?
  362. rsp->length : RESPONSE_ENTRY_CNT_MQ;
  363. qla27xx_insert16(i, buf, len);
  364. qla27xx_insert16(length, buf, len);
  365. qla27xx_insertbuf(rsp ? rsp->ring : NULL,
  366. length * sizeof(*rsp->ring), buf, len);
  367. count++;
  368. }
  369. }
  370. } else {
  371. ql_dbg(ql_dbg_misc, vha, 0xd026,
  372. "%s: unknown queue %x\n", __func__, ent->t263.queue_type);
  373. qla27xx_skip_entry(ent, buf);
  374. }
  375. if (buf)
  376. ent->t263.num_queues = count;
  377. return false;
  378. }
  379. static int
  380. qla27xx_fwdt_entry_t264(struct scsi_qla_host *vha,
  381. struct qla27xx_fwdt_entry *ent, void *buf, ulong *len)
  382. {
  383. ql_dbg(ql_dbg_misc, vha, 0xd208,
  384. "%s: getfce [%lx]\n", __func__, *len);
  385. if (vha->hw->fce) {
  386. if (buf) {
  387. ent->t264.fce_trace_size = FCE_SIZE;
  388. ent->t264.write_pointer = vha->hw->fce_wr;
  389. ent->t264.base_pointer = vha->hw->fce_dma;
  390. ent->t264.fce_enable_mb0 = vha->hw->fce_mb[0];
  391. ent->t264.fce_enable_mb2 = vha->hw->fce_mb[2];
  392. ent->t264.fce_enable_mb3 = vha->hw->fce_mb[3];
  393. ent->t264.fce_enable_mb4 = vha->hw->fce_mb[4];
  394. ent->t264.fce_enable_mb5 = vha->hw->fce_mb[5];
  395. ent->t264.fce_enable_mb6 = vha->hw->fce_mb[6];
  396. }
  397. qla27xx_insertbuf(vha->hw->fce, FCE_SIZE, buf, len);
  398. } else {
  399. ql_dbg(ql_dbg_misc, vha, 0xd027,
  400. "%s: missing fce\n", __func__);
  401. qla27xx_skip_entry(ent, buf);
  402. }
  403. return false;
  404. }
  405. static int
  406. qla27xx_fwdt_entry_t265(struct scsi_qla_host *vha,
  407. struct qla27xx_fwdt_entry *ent, void *buf, ulong *len)
  408. {
  409. struct device_reg_24xx __iomem *reg = qla27xx_isp_reg(vha);
  410. ql_dbg(ql_dbg_misc, vha, 0xd209,
  411. "%s: pause risc [%lx]\n", __func__, *len);
  412. if (buf)
  413. qla24xx_pause_risc(reg, vha->hw);
  414. return false;
  415. }
  416. static int
  417. qla27xx_fwdt_entry_t266(struct scsi_qla_host *vha,
  418. struct qla27xx_fwdt_entry *ent, void *buf, ulong *len)
  419. {
  420. ql_dbg(ql_dbg_misc, vha, 0xd20a,
  421. "%s: reset risc [%lx]\n", __func__, *len);
  422. if (buf)
  423. qla24xx_soft_reset(vha->hw);
  424. return false;
  425. }
  426. static int
  427. qla27xx_fwdt_entry_t267(struct scsi_qla_host *vha,
  428. struct qla27xx_fwdt_entry *ent, void *buf, ulong *len)
  429. {
  430. struct device_reg_24xx __iomem *reg = qla27xx_isp_reg(vha);
  431. ql_dbg(ql_dbg_misc, vha, 0xd20b,
  432. "%s: dis intr [%lx]\n", __func__, *len);
  433. qla27xx_write_reg(reg, ent->t267.pci_offset, ent->t267.data, buf);
  434. return false;
  435. }
  436. static int
  437. qla27xx_fwdt_entry_t268(struct scsi_qla_host *vha,
  438. struct qla27xx_fwdt_entry *ent, void *buf, ulong *len)
  439. {
  440. ql_dbg(ql_dbg_misc, vha, 0xd20c,
  441. "%s: gethb(%x) [%lx]\n", __func__, ent->t268.buf_type, *len);
  442. if (ent->t268.buf_type == T268_BUF_TYPE_EXTD_TRACE) {
  443. if (vha->hw->eft) {
  444. if (buf) {
  445. ent->t268.buf_size = EFT_SIZE;
  446. ent->t268.start_addr = vha->hw->eft_dma;
  447. }
  448. qla27xx_insertbuf(vha->hw->eft, EFT_SIZE, buf, len);
  449. } else {
  450. ql_dbg(ql_dbg_misc, vha, 0xd028,
  451. "%s: missing eft\n", __func__);
  452. qla27xx_skip_entry(ent, buf);
  453. }
  454. } else {
  455. ql_dbg(ql_dbg_misc, vha, 0xd02b,
  456. "%s: unknown buffer %x\n", __func__, ent->t268.buf_type);
  457. qla27xx_skip_entry(ent, buf);
  458. }
  459. return false;
  460. }
  461. static int
  462. qla27xx_fwdt_entry_t269(struct scsi_qla_host *vha,
  463. struct qla27xx_fwdt_entry *ent, void *buf, ulong *len)
  464. {
  465. ql_dbg(ql_dbg_misc, vha, 0xd20d,
  466. "%s: scratch [%lx]\n", __func__, *len);
  467. qla27xx_insert32(0xaaaaaaaa, buf, len);
  468. qla27xx_insert32(0xbbbbbbbb, buf, len);
  469. qla27xx_insert32(0xcccccccc, buf, len);
  470. qla27xx_insert32(0xdddddddd, buf, len);
  471. qla27xx_insert32(*len + sizeof(uint32_t), buf, len);
  472. if (buf)
  473. ent->t269.scratch_size = 5 * sizeof(uint32_t);
  474. return false;
  475. }
  476. static int
  477. qla27xx_fwdt_entry_t270(struct scsi_qla_host *vha,
  478. struct qla27xx_fwdt_entry *ent, void *buf, ulong *len)
  479. {
  480. struct device_reg_24xx __iomem *reg = qla27xx_isp_reg(vha);
  481. ulong dwords = ent->t270.count;
  482. ulong addr = ent->t270.addr;
  483. ql_dbg(ql_dbg_misc, vha, 0xd20e,
  484. "%s: rdremreg [%lx]\n", __func__, *len);
  485. qla27xx_write_reg(reg, IOBASE_ADDR, 0x40, buf);
  486. while (dwords--) {
  487. qla27xx_write_reg(reg, 0xc0, addr|0x80000000, buf);
  488. qla27xx_insert32(addr, buf, len);
  489. qla27xx_read_reg(reg, 0xc4, buf, len);
  490. addr += sizeof(uint32_t);
  491. }
  492. return false;
  493. }
  494. static int
  495. qla27xx_fwdt_entry_t271(struct scsi_qla_host *vha,
  496. struct qla27xx_fwdt_entry *ent, void *buf, ulong *len)
  497. {
  498. struct device_reg_24xx __iomem *reg = qla27xx_isp_reg(vha);
  499. ulong addr = ent->t271.addr;
  500. ulong data = ent->t271.data;
  501. ql_dbg(ql_dbg_misc, vha, 0xd20f,
  502. "%s: wrremreg [%lx]\n", __func__, *len);
  503. qla27xx_write_reg(reg, IOBASE_ADDR, 0x40, buf);
  504. qla27xx_write_reg(reg, 0xc4, data, buf);
  505. qla27xx_write_reg(reg, 0xc0, addr, buf);
  506. return false;
  507. }
  508. static int
  509. qla27xx_fwdt_entry_t272(struct scsi_qla_host *vha,
  510. struct qla27xx_fwdt_entry *ent, void *buf, ulong *len)
  511. {
  512. ulong dwords = ent->t272.count;
  513. ulong start = ent->t272.addr;
  514. ql_dbg(ql_dbg_misc, vha, 0xd210,
  515. "%s: rdremram [%lx]\n", __func__, *len);
  516. if (buf) {
  517. ql_dbg(ql_dbg_misc, vha, 0xd02c,
  518. "%s: @%lx -> (%lx dwords)\n", __func__, start, dwords);
  519. buf += *len;
  520. qla27xx_dump_mpi_ram(vha->hw, start, buf, dwords, &buf);
  521. }
  522. *len += dwords * sizeof(uint32_t);
  523. return false;
  524. }
  525. static int
  526. qla27xx_fwdt_entry_t273(struct scsi_qla_host *vha,
  527. struct qla27xx_fwdt_entry *ent, void *buf, ulong *len)
  528. {
  529. ulong dwords = ent->t273.count;
  530. ulong addr = ent->t273.addr;
  531. uint32_t value;
  532. ql_dbg(ql_dbg_misc, vha, 0xd211,
  533. "%s: pcicfg [%lx]\n", __func__, *len);
  534. while (dwords--) {
  535. value = ~0;
  536. if (pci_read_config_dword(vha->hw->pdev, addr, &value))
  537. ql_dbg(ql_dbg_misc, vha, 0xd02d,
  538. "%s: failed pcicfg read at %lx\n", __func__, addr);
  539. qla27xx_insert32(addr, buf, len);
  540. qla27xx_insert32(value, buf, len);
  541. addr += sizeof(uint32_t);
  542. }
  543. return false;
  544. }
  545. static int
  546. qla27xx_fwdt_entry_t274(struct scsi_qla_host *vha,
  547. struct qla27xx_fwdt_entry *ent, void *buf, ulong *len)
  548. {
  549. uint count = 0;
  550. uint i;
  551. ql_dbg(ql_dbg_misc, vha, 0xd212,
  552. "%s: getqsh(%x) [%lx]\n", __func__, ent->t274.queue_type, *len);
  553. if (ent->t274.queue_type == T274_QUEUE_TYPE_REQ_SHAD) {
  554. for (i = 0; i < vha->hw->max_req_queues; i++) {
  555. struct req_que *req = vha->hw->req_q_map[i];
  556. if (req || !buf) {
  557. qla27xx_insert16(i, buf, len);
  558. qla27xx_insert16(1, buf, len);
  559. qla27xx_insert32(req && req->out_ptr ?
  560. *req->out_ptr : 0, buf, len);
  561. count++;
  562. }
  563. }
  564. } else if (ent->t274.queue_type == T274_QUEUE_TYPE_RSP_SHAD) {
  565. for (i = 0; i < vha->hw->max_rsp_queues; i++) {
  566. struct rsp_que *rsp = vha->hw->rsp_q_map[i];
  567. if (rsp || !buf) {
  568. qla27xx_insert16(i, buf, len);
  569. qla27xx_insert16(1, buf, len);
  570. qla27xx_insert32(rsp && rsp->in_ptr ?
  571. *rsp->in_ptr : 0, buf, len);
  572. count++;
  573. }
  574. }
  575. } else {
  576. ql_dbg(ql_dbg_misc, vha, 0xd02f,
  577. "%s: unknown queue %x\n", __func__, ent->t274.queue_type);
  578. qla27xx_skip_entry(ent, buf);
  579. }
  580. if (buf)
  581. ent->t274.num_queues = count;
  582. if (!count)
  583. qla27xx_skip_entry(ent, buf);
  584. return false;
  585. }
  586. static int
  587. qla27xx_fwdt_entry_t275(struct scsi_qla_host *vha,
  588. struct qla27xx_fwdt_entry *ent, void *buf, ulong *len)
  589. {
  590. ulong offset = offsetof(typeof(*ent), t275.buffer);
  591. ql_dbg(ql_dbg_misc, vha, 0xd213,
  592. "%s: buffer(%x) [%lx]\n", __func__, ent->t275.length, *len);
  593. if (!ent->t275.length) {
  594. ql_dbg(ql_dbg_misc, vha, 0xd020,
  595. "%s: buffer zero length\n", __func__);
  596. qla27xx_skip_entry(ent, buf);
  597. goto done;
  598. }
  599. if (offset + ent->t275.length > ent->hdr.entry_size) {
  600. ql_dbg(ql_dbg_misc, vha, 0xd030,
  601. "%s: buffer overflow\n", __func__);
  602. qla27xx_skip_entry(ent, buf);
  603. goto done;
  604. }
  605. qla27xx_insertbuf(ent->t275.buffer, ent->t275.length, buf, len);
  606. done:
  607. return false;
  608. }
  609. static int
  610. qla27xx_fwdt_entry_other(struct scsi_qla_host *vha,
  611. struct qla27xx_fwdt_entry *ent, void *buf, ulong *len)
  612. {
  613. ql_dbg(ql_dbg_misc, vha, 0xd2ff,
  614. "%s: type %x [%lx]\n", __func__, ent->hdr.entry_type, *len);
  615. qla27xx_skip_entry(ent, buf);
  616. return false;
  617. }
  618. struct qla27xx_fwdt_entry_call {
  619. uint type;
  620. int (*call)(
  621. struct scsi_qla_host *,
  622. struct qla27xx_fwdt_entry *,
  623. void *,
  624. ulong *);
  625. };
  626. static struct qla27xx_fwdt_entry_call ql27xx_fwdt_entry_call_list[] = {
  627. { ENTRY_TYPE_NOP , qla27xx_fwdt_entry_t0 } ,
  628. { ENTRY_TYPE_TMP_END , qla27xx_fwdt_entry_t255 } ,
  629. { ENTRY_TYPE_RD_IOB_T1 , qla27xx_fwdt_entry_t256 } ,
  630. { ENTRY_TYPE_WR_IOB_T1 , qla27xx_fwdt_entry_t257 } ,
  631. { ENTRY_TYPE_RD_IOB_T2 , qla27xx_fwdt_entry_t258 } ,
  632. { ENTRY_TYPE_WR_IOB_T2 , qla27xx_fwdt_entry_t259 } ,
  633. { ENTRY_TYPE_RD_PCI , qla27xx_fwdt_entry_t260 } ,
  634. { ENTRY_TYPE_WR_PCI , qla27xx_fwdt_entry_t261 } ,
  635. { ENTRY_TYPE_RD_RAM , qla27xx_fwdt_entry_t262 } ,
  636. { ENTRY_TYPE_GET_QUEUE , qla27xx_fwdt_entry_t263 } ,
  637. { ENTRY_TYPE_GET_FCE , qla27xx_fwdt_entry_t264 } ,
  638. { ENTRY_TYPE_PSE_RISC , qla27xx_fwdt_entry_t265 } ,
  639. { ENTRY_TYPE_RST_RISC , qla27xx_fwdt_entry_t266 } ,
  640. { ENTRY_TYPE_DIS_INTR , qla27xx_fwdt_entry_t267 } ,
  641. { ENTRY_TYPE_GET_HBUF , qla27xx_fwdt_entry_t268 } ,
  642. { ENTRY_TYPE_SCRATCH , qla27xx_fwdt_entry_t269 } ,
  643. { ENTRY_TYPE_RDREMREG , qla27xx_fwdt_entry_t270 } ,
  644. { ENTRY_TYPE_WRREMREG , qla27xx_fwdt_entry_t271 } ,
  645. { ENTRY_TYPE_RDREMRAM , qla27xx_fwdt_entry_t272 } ,
  646. { ENTRY_TYPE_PCICFG , qla27xx_fwdt_entry_t273 } ,
  647. { ENTRY_TYPE_GET_SHADOW , qla27xx_fwdt_entry_t274 } ,
  648. { ENTRY_TYPE_WRITE_BUF , qla27xx_fwdt_entry_t275 } ,
  649. { -1 , qla27xx_fwdt_entry_other }
  650. };
  651. static inline int (*qla27xx_find_entry(uint type))
  652. (struct scsi_qla_host *, struct qla27xx_fwdt_entry *, void *, ulong *)
  653. {
  654. struct qla27xx_fwdt_entry_call *list = ql27xx_fwdt_entry_call_list;
  655. while (list->type < type)
  656. list++;
  657. if (list->type == type)
  658. return list->call;
  659. return qla27xx_fwdt_entry_other;
  660. }
  661. static inline void *
  662. qla27xx_next_entry(void *p)
  663. {
  664. struct qla27xx_fwdt_entry *ent = p;
  665. return p + ent->hdr.entry_size;
  666. }
  667. static void
  668. qla27xx_walk_template(struct scsi_qla_host *vha,
  669. struct qla27xx_fwdt_template *tmp, void *buf, ulong *len)
  670. {
  671. struct qla27xx_fwdt_entry *ent = (void *)tmp + tmp->entry_offset;
  672. ulong count = tmp->entry_count;
  673. ql_dbg(ql_dbg_misc, vha, 0xd01a,
  674. "%s: entry count %lx\n", __func__, count);
  675. while (count--) {
  676. if (qla27xx_find_entry(ent->hdr.entry_type)(vha, ent, buf, len))
  677. break;
  678. ent = qla27xx_next_entry(ent);
  679. }
  680. if (count)
  681. ql_dbg(ql_dbg_misc, vha, 0xd018,
  682. "%s: residual count (%lx)\n", __func__, count);
  683. if (ent->hdr.entry_type != ENTRY_TYPE_TMP_END)
  684. ql_dbg(ql_dbg_misc, vha, 0xd019,
  685. "%s: missing end (%lx)\n", __func__, count);
  686. ql_dbg(ql_dbg_misc, vha, 0xd01b,
  687. "%s: len=%lx\n", __func__, *len);
  688. }
  689. static void
  690. qla27xx_time_stamp(struct qla27xx_fwdt_template *tmp)
  691. {
  692. tmp->capture_timestamp = jiffies;
  693. }
  694. static void
  695. qla27xx_driver_info(struct qla27xx_fwdt_template *tmp)
  696. {
  697. uint8_t v[] = { 0, 0, 0, 0, 0, 0 };
  698. int rval = 0;
  699. rval = sscanf(qla2x00_version_str, "%hhu.%hhu.%hhu.%hhu.%hhu.%hhu",
  700. v+0, v+1, v+2, v+3, v+4, v+5);
  701. tmp->driver_info[0] = v[3] << 24 | v[2] << 16 | v[1] << 8 | v[0];
  702. tmp->driver_info[1] = v[5] << 8 | v[4];
  703. tmp->driver_info[2] = 0x12345678;
  704. }
  705. static void
  706. qla27xx_firmware_info(struct qla27xx_fwdt_template *tmp,
  707. struct scsi_qla_host *vha)
  708. {
  709. tmp->firmware_version[0] = vha->hw->fw_major_version;
  710. tmp->firmware_version[1] = vha->hw->fw_minor_version;
  711. tmp->firmware_version[2] = vha->hw->fw_subminor_version;
  712. tmp->firmware_version[3] =
  713. vha->hw->fw_attributes_h << 16 | vha->hw->fw_attributes;
  714. tmp->firmware_version[4] =
  715. vha->hw->fw_attributes_ext[1] << 16 | vha->hw->fw_attributes_ext[0];
  716. }
  717. static void
  718. ql27xx_edit_template(struct scsi_qla_host *vha,
  719. struct qla27xx_fwdt_template *tmp)
  720. {
  721. qla27xx_time_stamp(tmp);
  722. qla27xx_driver_info(tmp);
  723. qla27xx_firmware_info(tmp, vha);
  724. }
  725. static inline uint32_t
  726. qla27xx_template_checksum(void *p, ulong size)
  727. {
  728. uint32_t *buf = p;
  729. uint64_t sum = 0;
  730. size /= sizeof(*buf);
  731. while (size--)
  732. sum += *buf++;
  733. sum = (sum & 0xffffffff) + (sum >> 32);
  734. return ~sum;
  735. }
  736. static inline int
  737. qla27xx_verify_template_checksum(struct qla27xx_fwdt_template *tmp)
  738. {
  739. return qla27xx_template_checksum(tmp, tmp->template_size) == 0;
  740. }
  741. static inline int
  742. qla27xx_verify_template_header(struct qla27xx_fwdt_template *tmp)
  743. {
  744. return tmp->template_type == TEMPLATE_TYPE_FWDUMP;
  745. }
  746. static void
  747. qla27xx_execute_fwdt_template(struct scsi_qla_host *vha)
  748. {
  749. struct qla27xx_fwdt_template *tmp = vha->hw->fw_dump_template;
  750. ulong len;
  751. if (qla27xx_fwdt_template_valid(tmp)) {
  752. len = tmp->template_size;
  753. tmp = memcpy(vha->hw->fw_dump, tmp, len);
  754. ql27xx_edit_template(vha, tmp);
  755. qla27xx_walk_template(vha, tmp, tmp, &len);
  756. vha->hw->fw_dump_len = len;
  757. vha->hw->fw_dumped = 1;
  758. }
  759. }
  760. ulong
  761. qla27xx_fwdt_calculate_dump_size(struct scsi_qla_host *vha)
  762. {
  763. struct qla27xx_fwdt_template *tmp = vha->hw->fw_dump_template;
  764. ulong len = 0;
  765. if (qla27xx_fwdt_template_valid(tmp)) {
  766. len = tmp->template_size;
  767. qla27xx_walk_template(vha, tmp, NULL, &len);
  768. }
  769. return len;
  770. }
  771. ulong
  772. qla27xx_fwdt_template_size(void *p)
  773. {
  774. struct qla27xx_fwdt_template *tmp = p;
  775. return tmp->template_size;
  776. }
  777. ulong
  778. qla27xx_fwdt_template_default_size(void)
  779. {
  780. return sizeof(ql27xx_fwdt_default_template);
  781. }
  782. const void *
  783. qla27xx_fwdt_template_default(void)
  784. {
  785. return ql27xx_fwdt_default_template;
  786. }
  787. int
  788. qla27xx_fwdt_template_valid(void *p)
  789. {
  790. struct qla27xx_fwdt_template *tmp = p;
  791. if (!qla27xx_verify_template_header(tmp)) {
  792. ql_log(ql_log_warn, NULL, 0xd01c,
  793. "%s: template type %x\n", __func__, tmp->template_type);
  794. return false;
  795. }
  796. if (!qla27xx_verify_template_checksum(tmp)) {
  797. ql_log(ql_log_warn, NULL, 0xd01d,
  798. "%s: failed template checksum\n", __func__);
  799. return false;
  800. }
  801. return true;
  802. }
  803. void
  804. qla27xx_fwdump(scsi_qla_host_t *vha, int hardware_locked)
  805. {
  806. ulong flags = 0;
  807. if (!hardware_locked)
  808. spin_lock_irqsave(&vha->hw->hardware_lock, flags);
  809. if (!vha->hw->fw_dump)
  810. ql_log(ql_log_warn, vha, 0xd01e, "fwdump buffer missing.\n");
  811. else if (!vha->hw->fw_dump_template)
  812. ql_log(ql_log_warn, vha, 0xd01f, "fwdump template missing.\n");
  813. else
  814. qla27xx_execute_fwdt_template(vha);
  815. if (!hardware_locked)
  816. spin_unlock_irqrestore(&vha->hw->hardware_lock, flags);
  817. }