am335x-evm.dts 16 KB

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  1. /*
  2. * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
  3. *
  4. * This program is free software; you can redistribute it and/or modify
  5. * it under the terms of the GNU General Public License version 2 as
  6. * published by the Free Software Foundation.
  7. */
  8. /dts-v1/;
  9. #include "am33xx.dtsi"
  10. / {
  11. model = "TI AM335x EVM";
  12. compatible = "ti,am335x-evm", "ti,am33xx";
  13. cpus {
  14. cpu@0 {
  15. cpu0-supply = <&vdd1_reg>;
  16. };
  17. };
  18. memory {
  19. device_type = "memory";
  20. reg = <0x80000000 0x10000000>; /* 256 MB */
  21. };
  22. vbat: fixedregulator@0 {
  23. compatible = "regulator-fixed";
  24. regulator-name = "vbat";
  25. regulator-min-microvolt = <5000000>;
  26. regulator-max-microvolt = <5000000>;
  27. regulator-boot-on;
  28. };
  29. lis3_reg: fixedregulator@1 {
  30. compatible = "regulator-fixed";
  31. regulator-name = "lis3_reg";
  32. regulator-boot-on;
  33. };
  34. matrix_keypad: matrix_keypad@0 {
  35. compatible = "gpio-matrix-keypad";
  36. debounce-delay-ms = <5>;
  37. col-scan-delay-us = <2>;
  38. row-gpios = <&gpio1 25 GPIO_ACTIVE_HIGH /* Bank1, pin25 */
  39. &gpio1 26 GPIO_ACTIVE_HIGH /* Bank1, pin26 */
  40. &gpio1 27 GPIO_ACTIVE_HIGH>; /* Bank1, pin27 */
  41. col-gpios = <&gpio1 21 GPIO_ACTIVE_HIGH /* Bank1, pin21 */
  42. &gpio1 22 GPIO_ACTIVE_HIGH>; /* Bank1, pin22 */
  43. linux,keymap = <0x0000008b /* MENU */
  44. 0x0100009e /* BACK */
  45. 0x02000069 /* LEFT */
  46. 0x0001006a /* RIGHT */
  47. 0x0101001c /* ENTER */
  48. 0x0201006c>; /* DOWN */
  49. };
  50. gpio_keys: volume_keys@0 {
  51. compatible = "gpio-keys";
  52. #address-cells = <1>;
  53. #size-cells = <0>;
  54. autorepeat;
  55. switch@9 {
  56. label = "volume-up";
  57. linux,code = <115>;
  58. gpios = <&gpio0 2 GPIO_ACTIVE_LOW>;
  59. gpio-key,wakeup;
  60. };
  61. switch@10 {
  62. label = "volume-down";
  63. linux,code = <114>;
  64. gpios = <&gpio0 3 GPIO_ACTIVE_LOW>;
  65. gpio-key,wakeup;
  66. };
  67. };
  68. backlight {
  69. compatible = "pwm-backlight";
  70. pwms = <&ecap0 0 50000 0>;
  71. brightness-levels = <0 51 53 56 62 75 101 152 255>;
  72. default-brightness-level = <8>;
  73. };
  74. panel {
  75. compatible = "ti,tilcdc,panel";
  76. status = "okay";
  77. pinctrl-names = "default";
  78. pinctrl-0 = <&lcd_pins_s0>;
  79. panel-info {
  80. ac-bias = <255>;
  81. ac-bias-intrpt = <0>;
  82. dma-burst-sz = <16>;
  83. bpp = <32>;
  84. fdd = <0x80>;
  85. sync-edge = <0>;
  86. sync-ctrl = <1>;
  87. raster-order = <0>;
  88. fifo-th = <0>;
  89. };
  90. display-timings {
  91. 800x480p62 {
  92. clock-frequency = <30000000>;
  93. hactive = <800>;
  94. vactive = <480>;
  95. hfront-porch = <39>;
  96. hback-porch = <39>;
  97. hsync-len = <47>;
  98. vback-porch = <29>;
  99. vfront-porch = <13>;
  100. vsync-len = <2>;
  101. hsync-active = <1>;
  102. vsync-active = <1>;
  103. };
  104. };
  105. };
  106. sound {
  107. compatible = "ti,da830-evm-audio";
  108. ti,model = "AM335x-EVM";
  109. ti,audio-codec = <&tlv320aic3106>;
  110. ti,mcasp-controller = <&mcasp1>;
  111. ti,codec-clock-rate = <12000000>;
  112. ti,audio-routing =
  113. "Headphone Jack", "HPLOUT",
  114. "Headphone Jack", "HPROUT",
  115. "LINE1L", "Line In",
  116. "LINE1R", "Line In";
  117. };
  118. };
  119. &am33xx_pinmux {
  120. pinctrl-names = "default";
  121. pinctrl-0 = <&matrix_keypad_s0 &volume_keys_s0 &clkout2_pin>;
  122. matrix_keypad_s0: matrix_keypad_s0 {
  123. pinctrl-single,pins = <
  124. 0x54 (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_a5.gpio1_21 */
  125. 0x58 (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_a6.gpio1_22 */
  126. 0x64 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_a9.gpio1_25 */
  127. 0x68 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_a10.gpio1_26 */
  128. 0x6c (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_a11.gpio1_27 */
  129. >;
  130. };
  131. volume_keys_s0: volume_keys_s0 {
  132. pinctrl-single,pins = <
  133. 0x150 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* spi0_sclk.gpio0_2 */
  134. 0x154 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* spi0_d0.gpio0_3 */
  135. >;
  136. };
  137. i2c0_pins: pinmux_i2c0_pins {
  138. pinctrl-single,pins = <
  139. 0x188 (PIN_INPUT_PULLUP | MUX_MODE0) /* i2c0_sda.i2c0_sda */
  140. 0x18c (PIN_INPUT_PULLUP | MUX_MODE0) /* i2c0_scl.i2c0_scl */
  141. >;
  142. };
  143. i2c1_pins: pinmux_i2c1_pins {
  144. pinctrl-single,pins = <
  145. 0x158 (PIN_INPUT_PULLUP | MUX_MODE2) /* spi0_d1.i2c1_sda */
  146. 0x15c (PIN_INPUT_PULLUP | MUX_MODE2) /* spi0_cs0.i2c1_scl */
  147. >;
  148. };
  149. uart0_pins: pinmux_uart0_pins {
  150. pinctrl-single,pins = <
  151. 0x170 (PIN_INPUT_PULLUP | MUX_MODE0) /* uart0_rxd.uart0_rxd */
  152. 0x174 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart0_txd.uart0_txd */
  153. >;
  154. };
  155. clkout2_pin: pinmux_clkout2_pin {
  156. pinctrl-single,pins = <
  157. 0x1b4 (PIN_OUTPUT_PULLDOWN | MUX_MODE3) /* xdma_event_intr1.clkout2 */
  158. >;
  159. };
  160. nandflash_pins_s0: nandflash_pins_s0 {
  161. pinctrl-single,pins = <
  162. 0x0 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad0.gpmc_ad0 */
  163. 0x4 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad1.gpmc_ad1 */
  164. 0x8 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad2.gpmc_ad2 */
  165. 0xc (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad3.gpmc_ad3 */
  166. 0x10 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad4.gpmc_ad4 */
  167. 0x14 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad5.gpmc_ad5 */
  168. 0x18 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad6.gpmc_ad6 */
  169. 0x1c (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad7.gpmc_ad7 */
  170. 0x70 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_wait0.gpmc_wait0 */
  171. 0x74 (PIN_INPUT_PULLUP | MUX_MODE7) /* gpmc_wpn.gpio0_30 */
  172. 0x7c (PIN_OUTPUT | MUX_MODE0) /* gpmc_csn0.gpmc_csn0 */
  173. 0x90 (PIN_OUTPUT | MUX_MODE0) /* gpmc_advn_ale.gpmc_advn_ale */
  174. 0x94 (PIN_OUTPUT | MUX_MODE0) /* gpmc_oen_ren.gpmc_oen_ren */
  175. 0x98 (PIN_OUTPUT | MUX_MODE0) /* gpmc_wen.gpmc_wen */
  176. 0x9c (PIN_OUTPUT | MUX_MODE0) /* gpmc_be0n_cle.gpmc_be0n_cle */
  177. >;
  178. };
  179. ecap0_pins: backlight_pins {
  180. pinctrl-single,pins = <
  181. 0x164 0x0 /* eCAP0_in_PWM0_out.eCAP0_in_PWM0_out MODE0 */
  182. >;
  183. };
  184. cpsw_default: cpsw_default {
  185. pinctrl-single,pins = <
  186. /* Slave 1 */
  187. 0x114 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txen.rgmii1_tctl */
  188. 0x118 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxdv.rgmii1_rctl */
  189. 0x11c (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd3.rgmii1_td3 */
  190. 0x120 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd2.rgmii1_td2 */
  191. 0x124 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd1.rgmii1_td1 */
  192. 0x128 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd0.rgmii1_td0 */
  193. 0x12c (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txclk.rgmii1_tclk */
  194. 0x130 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxclk.rgmii1_rclk */
  195. 0x134 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd3.rgmii1_rd3 */
  196. 0x138 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd2.rgmii1_rd2 */
  197. 0x13c (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd1.rgmii1_rd1 */
  198. 0x140 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd0.rgmii1_rd0 */
  199. >;
  200. };
  201. cpsw_sleep: cpsw_sleep {
  202. pinctrl-single,pins = <
  203. /* Slave 1 reset value */
  204. 0x114 (PIN_INPUT_PULLDOWN | MUX_MODE7)
  205. 0x118 (PIN_INPUT_PULLDOWN | MUX_MODE7)
  206. 0x11c (PIN_INPUT_PULLDOWN | MUX_MODE7)
  207. 0x120 (PIN_INPUT_PULLDOWN | MUX_MODE7)
  208. 0x124 (PIN_INPUT_PULLDOWN | MUX_MODE7)
  209. 0x128 (PIN_INPUT_PULLDOWN | MUX_MODE7)
  210. 0x12c (PIN_INPUT_PULLDOWN | MUX_MODE7)
  211. 0x130 (PIN_INPUT_PULLDOWN | MUX_MODE7)
  212. 0x134 (PIN_INPUT_PULLDOWN | MUX_MODE7)
  213. 0x138 (PIN_INPUT_PULLDOWN | MUX_MODE7)
  214. 0x13c (PIN_INPUT_PULLDOWN | MUX_MODE7)
  215. 0x140 (PIN_INPUT_PULLDOWN | MUX_MODE7)
  216. >;
  217. };
  218. davinci_mdio_default: davinci_mdio_default {
  219. pinctrl-single,pins = <
  220. /* MDIO */
  221. 0x148 (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* mdio_data.mdio_data */
  222. 0x14c (PIN_OUTPUT_PULLUP | MUX_MODE0) /* mdio_clk.mdio_clk */
  223. >;
  224. };
  225. davinci_mdio_sleep: davinci_mdio_sleep {
  226. pinctrl-single,pins = <
  227. /* MDIO reset value */
  228. 0x148 (PIN_INPUT_PULLDOWN | MUX_MODE7)
  229. 0x14c (PIN_INPUT_PULLDOWN | MUX_MODE7)
  230. >;
  231. };
  232. mmc1_pins: pinmux_mmc1_pins {
  233. pinctrl-single,pins = <
  234. 0x160 (PIN_INPUT | MUX_MODE7) /* spi0_cs1.gpio0_6 */
  235. >;
  236. };
  237. lcd_pins_s0: lcd_pins_s0 {
  238. pinctrl-single,pins = <
  239. 0x20 (PIN_OUTPUT | MUX_MODE1) /* gpmc_ad8.lcd_data23 */
  240. 0x24 (PIN_OUTPUT | MUX_MODE1) /* gpmc_ad9.lcd_data22 */
  241. 0x28 (PIN_OUTPUT | MUX_MODE1) /* gpmc_ad10.lcd_data21 */
  242. 0x2c (PIN_OUTPUT | MUX_MODE1) /* gpmc_ad11.lcd_data20 */
  243. 0x30 (PIN_OUTPUT | MUX_MODE1) /* gpmc_ad12.lcd_data19 */
  244. 0x34 (PIN_OUTPUT | MUX_MODE1) /* gpmc_ad13.lcd_data18 */
  245. 0x38 (PIN_OUTPUT | MUX_MODE1) /* gpmc_ad14.lcd_data17 */
  246. 0x3c (PIN_OUTPUT | MUX_MODE1) /* gpmc_ad15.lcd_data16 */
  247. 0xa0 (PIN_OUTPUT | MUX_MODE0) /* lcd_data0.lcd_data0 */
  248. 0xa4 (PIN_OUTPUT | MUX_MODE0) /* lcd_data1.lcd_data1 */
  249. 0xa8 (PIN_OUTPUT | MUX_MODE0) /* lcd_data2.lcd_data2 */
  250. 0xac (PIN_OUTPUT | MUX_MODE0) /* lcd_data3.lcd_data3 */
  251. 0xb0 (PIN_OUTPUT | MUX_MODE0) /* lcd_data4.lcd_data4 */
  252. 0xb4 (PIN_OUTPUT | MUX_MODE0) /* lcd_data5.lcd_data5 */
  253. 0xb8 (PIN_OUTPUT | MUX_MODE0) /* lcd_data6.lcd_data6 */
  254. 0xbc (PIN_OUTPUT | MUX_MODE0) /* lcd_data7.lcd_data7 */
  255. 0xc0 (PIN_OUTPUT | MUX_MODE0) /* lcd_data8.lcd_data8 */
  256. 0xc4 (PIN_OUTPUT | MUX_MODE0) /* lcd_data9.lcd_data9 */
  257. 0xc8 (PIN_OUTPUT | MUX_MODE0) /* lcd_data10.lcd_data10 */
  258. 0xcc (PIN_OUTPUT | MUX_MODE0) /* lcd_data11.lcd_data11 */
  259. 0xd0 (PIN_OUTPUT | MUX_MODE0) /* lcd_data12.lcd_data12 */
  260. 0xd4 (PIN_OUTPUT | MUX_MODE0) /* lcd_data13.lcd_data13 */
  261. 0xd8 (PIN_OUTPUT | MUX_MODE0) /* lcd_data14.lcd_data14 */
  262. 0xdc (PIN_OUTPUT | MUX_MODE0) /* lcd_data15.lcd_data15 */
  263. 0xe0 (PIN_OUTPUT | MUX_MODE0) /* lcd_vsync.lcd_vsync */
  264. 0xe4 (PIN_OUTPUT | MUX_MODE0) /* lcd_hsync.lcd_hsync */
  265. 0xe8 (PIN_OUTPUT | MUX_MODE0) /* lcd_pclk.lcd_pclk */
  266. 0xec (PIN_OUTPUT | MUX_MODE0) /* lcd_ac_bias_en.lcd_ac_bias_en */
  267. >;
  268. };
  269. am335x_evm_audio_pins: am335x_evm_audio_pins {
  270. pinctrl-single,pins = <
  271. 0x10c (PIN_INPUT_PULLDOWN | MUX_MODE4) /* mii1_crs.mcasp1_aclkx */
  272. 0x110 (PIN_INPUT_PULLDOWN | MUX_MODE4) /* mii1_rxerr.mcasp1_fsx */
  273. 0x108 (PIN_OUTPUT_PULLDOWN | MUX_MODE4) /* mii1_col.mcasp1_axr2 */
  274. 0x144 (PIN_INPUT_PULLDOWN | MUX_MODE4) /* rmii1_ref_clk.mcasp1_axr3 */
  275. >;
  276. };
  277. };
  278. &uart0 {
  279. pinctrl-names = "default";
  280. pinctrl-0 = <&uart0_pins>;
  281. status = "okay";
  282. };
  283. &i2c0 {
  284. pinctrl-names = "default";
  285. pinctrl-0 = <&i2c0_pins>;
  286. status = "okay";
  287. clock-frequency = <400000>;
  288. tps: tps@2d {
  289. reg = <0x2d>;
  290. };
  291. };
  292. &usb {
  293. status = "okay";
  294. };
  295. &usb_ctrl_mod {
  296. status = "okay";
  297. };
  298. &usb0_phy {
  299. status = "okay";
  300. };
  301. &usb1_phy {
  302. status = "okay";
  303. };
  304. &usb0 {
  305. status = "okay";
  306. };
  307. &usb1 {
  308. status = "okay";
  309. dr_mode = "host";
  310. };
  311. &cppi41dma {
  312. status = "okay";
  313. };
  314. &i2c1 {
  315. pinctrl-names = "default";
  316. pinctrl-0 = <&i2c1_pins>;
  317. status = "okay";
  318. clock-frequency = <100000>;
  319. lis331dlh: lis331dlh@18 {
  320. compatible = "st,lis331dlh", "st,lis3lv02d";
  321. reg = <0x18>;
  322. Vdd-supply = <&lis3_reg>;
  323. Vdd_IO-supply = <&lis3_reg>;
  324. st,click-single-x;
  325. st,click-single-y;
  326. st,click-single-z;
  327. st,click-thresh-x = <10>;
  328. st,click-thresh-y = <10>;
  329. st,click-thresh-z = <10>;
  330. st,irq1-click;
  331. st,irq2-click;
  332. st,wakeup-x-lo;
  333. st,wakeup-x-hi;
  334. st,wakeup-y-lo;
  335. st,wakeup-y-hi;
  336. st,wakeup-z-lo;
  337. st,wakeup-z-hi;
  338. st,min-limit-x = <120>;
  339. st,min-limit-y = <120>;
  340. st,min-limit-z = <140>;
  341. st,max-limit-x = <550>;
  342. st,max-limit-y = <550>;
  343. st,max-limit-z = <750>;
  344. };
  345. tsl2550: tsl2550@39 {
  346. compatible = "taos,tsl2550";
  347. reg = <0x39>;
  348. };
  349. tmp275: tmp275@48 {
  350. compatible = "ti,tmp275";
  351. reg = <0x48>;
  352. };
  353. tlv320aic3106: tlv320aic3106@1b {
  354. compatible = "ti,tlv320aic3106";
  355. reg = <0x1b>;
  356. status = "okay";
  357. /* Regulators */
  358. AVDD-supply = <&vaux2_reg>;
  359. IOVDD-supply = <&vaux2_reg>;
  360. DRVDD-supply = <&vaux2_reg>;
  361. DVDD-supply = <&vbat>;
  362. };
  363. };
  364. &lcdc {
  365. status = "okay";
  366. };
  367. &elm {
  368. status = "okay";
  369. };
  370. &epwmss0 {
  371. status = "okay";
  372. ecap0: ecap@48300100 {
  373. status = "okay";
  374. pinctrl-names = "default";
  375. pinctrl-0 = <&ecap0_pins>;
  376. };
  377. };
  378. &gpmc {
  379. status = "okay";
  380. pinctrl-names = "default";
  381. pinctrl-0 = <&nandflash_pins_s0>;
  382. ranges = <0 0 0x08000000 0x10000000>; /* CS0: NAND */
  383. nand@0,0 {
  384. reg = <0 0 0>; /* CS0, offset 0 */
  385. ti,nand-ecc-opt = "bch8";
  386. ti,elm-id = <&elm>;
  387. nand-bus-width = <8>;
  388. gpmc,device-width = <1>;
  389. gpmc,sync-clk-ps = <0>;
  390. gpmc,cs-on-ns = <0>;
  391. gpmc,cs-rd-off-ns = <44>;
  392. gpmc,cs-wr-off-ns = <44>;
  393. gpmc,adv-on-ns = <6>;
  394. gpmc,adv-rd-off-ns = <34>;
  395. gpmc,adv-wr-off-ns = <44>;
  396. gpmc,we-on-ns = <0>;
  397. gpmc,we-off-ns = <40>;
  398. gpmc,oe-on-ns = <0>;
  399. gpmc,oe-off-ns = <54>;
  400. gpmc,access-ns = <64>;
  401. gpmc,rd-cycle-ns = <82>;
  402. gpmc,wr-cycle-ns = <82>;
  403. gpmc,wait-on-read = "true";
  404. gpmc,wait-on-write = "true";
  405. gpmc,bus-turnaround-ns = <0>;
  406. gpmc,cycle2cycle-delay-ns = <0>;
  407. gpmc,clk-activation-ns = <0>;
  408. gpmc,wait-monitoring-ns = <0>;
  409. gpmc,wr-access-ns = <40>;
  410. gpmc,wr-data-mux-bus-ns = <0>;
  411. /* MTD partition table */
  412. /* All SPL-* partitions are sized to minimal length
  413. * which can be independently programmable. For
  414. * NAND flash this is equal to size of erase-block */
  415. #address-cells = <1>;
  416. #size-cells = <1>;
  417. partition@0 {
  418. label = "NAND.SPL";
  419. reg = <0x00000000 0x000020000>;
  420. };
  421. partition@1 {
  422. label = "NAND.SPL.backup1";
  423. reg = <0x00020000 0x00020000>;
  424. };
  425. partition@2 {
  426. label = "NAND.SPL.backup2";
  427. reg = <0x00040000 0x00020000>;
  428. };
  429. partition@3 {
  430. label = "NAND.SPL.backup3";
  431. reg = <0x00060000 0x00020000>;
  432. };
  433. partition@4 {
  434. label = "NAND.u-boot-spl-os";
  435. reg = <0x00080000 0x00040000>;
  436. };
  437. partition@5 {
  438. label = "NAND.u-boot";
  439. reg = <0x000C0000 0x00100000>;
  440. };
  441. partition@6 {
  442. label = "NAND.u-boot-env";
  443. reg = <0x001C0000 0x00020000>;
  444. };
  445. partition@7 {
  446. label = "NAND.u-boot-env.backup1";
  447. reg = <0x001E0000 0x00020000>;
  448. };
  449. partition@8 {
  450. label = "NAND.kernel";
  451. reg = <0x00200000 0x00800000>;
  452. };
  453. partition@9 {
  454. label = "NAND.file-system";
  455. reg = <0x00A00000 0x0F600000>;
  456. };
  457. };
  458. };
  459. #include "tps65910.dtsi"
  460. &mcasp1 {
  461. pinctrl-names = "default";
  462. pinctrl-0 = <&am335x_evm_audio_pins>;
  463. status = "okay";
  464. op-mode = <0>; /* MCASP_IIS_MODE */
  465. tdm-slots = <2>;
  466. /* 4 serializers */
  467. serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */
  468. 0 0 1 2
  469. >;
  470. tx-num-evt = <32>;
  471. rx-num-evt = <32>;
  472. };
  473. &tps {
  474. vcc1-supply = <&vbat>;
  475. vcc2-supply = <&vbat>;
  476. vcc3-supply = <&vbat>;
  477. vcc4-supply = <&vbat>;
  478. vcc5-supply = <&vbat>;
  479. vcc6-supply = <&vbat>;
  480. vcc7-supply = <&vbat>;
  481. vccio-supply = <&vbat>;
  482. regulators {
  483. vrtc_reg: regulator@0 {
  484. regulator-always-on;
  485. };
  486. vio_reg: regulator@1 {
  487. regulator-always-on;
  488. };
  489. vdd1_reg: regulator@2 {
  490. /* VDD_MPU voltage limits 0.95V - 1.26V with +/-4% tolerance */
  491. regulator-name = "vdd_mpu";
  492. regulator-min-microvolt = <912500>;
  493. regulator-max-microvolt = <1312500>;
  494. regulator-boot-on;
  495. regulator-always-on;
  496. };
  497. vdd2_reg: regulator@3 {
  498. /* VDD_CORE voltage limits 0.95V - 1.1V with +/-4% tolerance */
  499. regulator-name = "vdd_core";
  500. regulator-min-microvolt = <912500>;
  501. regulator-max-microvolt = <1150000>;
  502. regulator-boot-on;
  503. regulator-always-on;
  504. };
  505. vdd3_reg: regulator@4 {
  506. regulator-always-on;
  507. };
  508. vdig1_reg: regulator@5 {
  509. regulator-always-on;
  510. };
  511. vdig2_reg: regulator@6 {
  512. regulator-always-on;
  513. };
  514. vpll_reg: regulator@7 {
  515. regulator-always-on;
  516. };
  517. vdac_reg: regulator@8 {
  518. regulator-always-on;
  519. };
  520. vaux1_reg: regulator@9 {
  521. regulator-always-on;
  522. };
  523. vaux2_reg: regulator@10 {
  524. regulator-always-on;
  525. };
  526. vaux33_reg: regulator@11 {
  527. regulator-always-on;
  528. };
  529. vmmc_reg: regulator@12 {
  530. regulator-min-microvolt = <1800000>;
  531. regulator-max-microvolt = <3300000>;
  532. regulator-always-on;
  533. };
  534. };
  535. };
  536. &mac {
  537. pinctrl-names = "default", "sleep";
  538. pinctrl-0 = <&cpsw_default>;
  539. pinctrl-1 = <&cpsw_sleep>;
  540. status = "okay";
  541. };
  542. &davinci_mdio {
  543. pinctrl-names = "default", "sleep";
  544. pinctrl-0 = <&davinci_mdio_default>;
  545. pinctrl-1 = <&davinci_mdio_sleep>;
  546. status = "okay";
  547. };
  548. &cpsw_emac0 {
  549. phy_id = <&davinci_mdio>, <0>;
  550. phy-mode = "rgmii-txid";
  551. };
  552. &cpsw_emac1 {
  553. phy_id = <&davinci_mdio>, <1>;
  554. phy-mode = "rgmii-txid";
  555. };
  556. &tscadc {
  557. status = "okay";
  558. tsc {
  559. ti,wires = <4>;
  560. ti,x-plate-resistance = <200>;
  561. ti,coordinate-readouts = <5>;
  562. ti,wire-config = <0x00 0x11 0x22 0x33>;
  563. };
  564. adc {
  565. ti,adc-channels = <4 5 6 7>;
  566. };
  567. };
  568. &mmc1 {
  569. status = "okay";
  570. vmmc-supply = <&vmmc_reg>;
  571. bus-width = <4>;
  572. pinctrl-names = "default";
  573. pinctrl-0 = <&mmc1_pins>;
  574. cd-gpios = <&gpio0 6 GPIO_ACTIVE_HIGH>;
  575. };
  576. &sham {
  577. status = "okay";
  578. };
  579. &aes {
  580. status = "okay";
  581. };