am335x-igep0033.dtsi 6.1 KB

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  1. /*
  2. * am335x-igep0033.dtsi - Device Tree file for IGEP COM AQUILA AM335x
  3. *
  4. * Copyright (C) 2013 ISEE 2007 SL - http://www.isee.biz
  5. *
  6. * This program is free software; you can redistribute it and/or modify
  7. * it under the terms of the GNU General Public License version 2 as
  8. * published by the Free Software Foundation.
  9. */
  10. /dts-v1/;
  11. #include "am33xx.dtsi"
  12. / {
  13. cpus {
  14. cpu@0 {
  15. cpu0-supply = <&vdd1_reg>;
  16. };
  17. };
  18. memory {
  19. device_type = "memory";
  20. reg = <0x80000000 0x10000000>; /* 256 MB */
  21. };
  22. leds {
  23. pinctrl-names = "default";
  24. pinctrl-0 = <&leds_pins>;
  25. compatible = "gpio-leds";
  26. led@0 {
  27. label = "com:green:user";
  28. gpios = <&gpio1 23 GPIO_ACTIVE_HIGH>;
  29. default-state = "on";
  30. };
  31. };
  32. vbat: fixedregulator@0 {
  33. compatible = "regulator-fixed";
  34. regulator-name = "vbat";
  35. regulator-min-microvolt = <5000000>;
  36. regulator-max-microvolt = <5000000>;
  37. regulator-boot-on;
  38. };
  39. vmmc: fixedregulator@0 {
  40. compatible = "regulator-fixed";
  41. regulator-name = "vmmc";
  42. regulator-min-microvolt = <3300000>;
  43. regulator-max-microvolt = <3300000>;
  44. };
  45. };
  46. &am33xx_pinmux {
  47. i2c0_pins: pinmux_i2c0_pins {
  48. pinctrl-single,pins = <
  49. 0x188 (PIN_INPUT_PULLUP | MUX_MODE0) /* i2c0_sda.i2c0_sda */
  50. 0x18c (PIN_INPUT_PULLUP | MUX_MODE0) /* i2c0_scl.i2c0_scl */
  51. >;
  52. };
  53. nandflash_pins: pinmux_nandflash_pins {
  54. pinctrl-single,pins = <
  55. 0x0 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad0.gpmc_ad0 */
  56. 0x4 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad1.gpmc_ad1 */
  57. 0x8 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad2.gpmc_ad2 */
  58. 0xc (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad3.gpmc_ad3 */
  59. 0x10 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad4.gpmc_ad4 */
  60. 0x14 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad5.gpmc_ad5 */
  61. 0x18 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad6.gpmc_ad6 */
  62. 0x1c (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad7.gpmc_ad7 */
  63. 0x70 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_wait0.gpmc_wait0 */
  64. 0x74 (PIN_INPUT_PULLUP | MUX_MODE7) /* gpmc_wpn.gpio0_30 */
  65. 0x7c (PIN_OUTPUT | MUX_MODE0) /* gpmc_csn0.gpmc_csn0 */
  66. 0x90 (PIN_OUTPUT | MUX_MODE0) /* gpmc_advn_ale.gpmc_advn_ale */
  67. 0x94 (PIN_OUTPUT | MUX_MODE0) /* gpmc_oen_ren.gpmc_oen_ren */
  68. 0x98 (PIN_OUTPUT | MUX_MODE0) /* gpmc_wen.gpmc_wen */
  69. 0x9c (PIN_OUTPUT | MUX_MODE0) /* gpmc_be0n_cle.gpmc_be0n_cle */
  70. >;
  71. };
  72. uart0_pins: pinmux_uart0_pins {
  73. pinctrl-single,pins = <
  74. 0x170 (PIN_INPUT_PULLUP | MUX_MODE0) /* uart0_rxd.uart0_rxd */
  75. 0x174 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart0_txd.uart0_txd */
  76. >;
  77. };
  78. leds_pins: pinmux_leds_pins {
  79. pinctrl-single,pins = <
  80. 0x5c (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_a7.gpio1_23 */
  81. >;
  82. };
  83. };
  84. &mac {
  85. status = "okay";
  86. };
  87. &davinci_mdio {
  88. status = "okay";
  89. };
  90. &cpsw_emac0 {
  91. phy_id = <&davinci_mdio>, <0>;
  92. phy-mode = "rmii";
  93. };
  94. &cpsw_emac1 {
  95. phy_id = <&davinci_mdio>, <1>;
  96. phy-mode = "rmii";
  97. };
  98. &phy_sel {
  99. rmii-clock-ext;
  100. };
  101. &elm {
  102. status = "okay";
  103. };
  104. &gpmc {
  105. status = "okay";
  106. pinctrl-names = "default";
  107. pinctrl-0 = <&nandflash_pins>;
  108. ranges = <0 0 0x08000000 0x10000000>; /* CS0: NAND */
  109. nand@0,0 {
  110. reg = <0 0 0>; /* CS0, offset 0 */
  111. nand-bus-width = <8>;
  112. ti,nand-ecc-opt = "bch8";
  113. gpmc,device-width = <1>;
  114. gpmc,sync-clk-ps = <0>;
  115. gpmc,cs-on-ns = <0>;
  116. gpmc,cs-rd-off-ns = <44>;
  117. gpmc,cs-wr-off-ns = <44>;
  118. gpmc,adv-on-ns = <6>;
  119. gpmc,adv-rd-off-ns = <34>;
  120. gpmc,adv-wr-off-ns = <44>;
  121. gpmc,we-on-ns = <0>;
  122. gpmc,we-off-ns = <40>;
  123. gpmc,oe-on-ns = <0>;
  124. gpmc,oe-off-ns = <54>;
  125. gpmc,access-ns = <64>;
  126. gpmc,rd-cycle-ns = <82>;
  127. gpmc,wr-cycle-ns = <82>;
  128. gpmc,wait-on-read = "true";
  129. gpmc,wait-on-write = "true";
  130. gpmc,bus-turnaround-ns = <0>;
  131. gpmc,cycle2cycle-delay-ns = <0>;
  132. gpmc,clk-activation-ns = <0>;
  133. gpmc,wait-monitoring-ns = <0>;
  134. gpmc,wr-access-ns = <40>;
  135. gpmc,wr-data-mux-bus-ns = <0>;
  136. #address-cells = <1>;
  137. #size-cells = <1>;
  138. elm_id = <&elm>;
  139. /* MTD partition table */
  140. partition@0 {
  141. label = "SPL";
  142. reg = <0x00000000 0x000080000>;
  143. };
  144. partition@1 {
  145. label = "U-boot";
  146. reg = <0x00080000 0x001e0000>;
  147. };
  148. partition@2 {
  149. label = "U-Boot Env";
  150. reg = <0x00260000 0x00020000>;
  151. };
  152. partition@3 {
  153. label = "Kernel";
  154. reg = <0x00280000 0x00500000>;
  155. };
  156. partition@4 {
  157. label = "File System";
  158. reg = <0x00780000 0x007880000>;
  159. };
  160. };
  161. };
  162. &i2c0 {
  163. status = "okay";
  164. pinctrl-names = "default";
  165. pinctrl-0 = <&i2c0_pins>;
  166. clock-frequency = <400000>;
  167. tps: tps@2d {
  168. reg = <0x2d>;
  169. };
  170. };
  171. &mmc1 {
  172. status = "okay";
  173. vmmc-supply = <&vmmc>;
  174. bus-width = <4>;
  175. };
  176. &uart0 {
  177. status = "okay";
  178. pinctrl-names = "default";
  179. pinctrl-0 = <&uart0_pins>;
  180. };
  181. &usb {
  182. status = "okay";
  183. };
  184. &usb_ctrl_mod {
  185. status = "okay";
  186. };
  187. &usb0_phy {
  188. status = "okay";
  189. };
  190. &usb1_phy {
  191. status = "okay";
  192. };
  193. &usb0 {
  194. status = "okay";
  195. };
  196. &usb1 {
  197. status = "okay";
  198. dr_mode = "host";
  199. };
  200. &cppi41dma {
  201. status = "okay";
  202. };
  203. #include "tps65910.dtsi"
  204. &tps {
  205. vcc1-supply = <&vbat>;
  206. vcc2-supply = <&vbat>;
  207. vcc3-supply = <&vbat>;
  208. vcc4-supply = <&vbat>;
  209. vcc5-supply = <&vbat>;
  210. vcc6-supply = <&vbat>;
  211. vcc7-supply = <&vbat>;
  212. vccio-supply = <&vbat>;
  213. regulators {
  214. vrtc_reg: regulator@0 {
  215. regulator-always-on;
  216. };
  217. vio_reg: regulator@1 {
  218. regulator-always-on;
  219. };
  220. vdd1_reg: regulator@2 {
  221. /* VDD_MPU voltage limits 0.95V - 1.26V with +/-4% tolerance */
  222. regulator-name = "vdd_mpu";
  223. regulator-min-microvolt = <912500>;
  224. regulator-max-microvolt = <1312500>;
  225. regulator-boot-on;
  226. regulator-always-on;
  227. };
  228. vdd2_reg: regulator@3 {
  229. /* VDD_CORE voltage limits 0.95V - 1.1V with +/-4% tolerance */
  230. regulator-name = "vdd_core";
  231. regulator-min-microvolt = <912500>;
  232. regulator-max-microvolt = <1150000>;
  233. regulator-boot-on;
  234. regulator-always-on;
  235. };
  236. vdd3_reg: regulator@4 {
  237. regulator-always-on;
  238. };
  239. vdig1_reg: regulator@5 {
  240. regulator-always-on;
  241. };
  242. vdig2_reg: regulator@6 {
  243. regulator-always-on;
  244. };
  245. vpll_reg: regulator@7 {
  246. regulator-always-on;
  247. };
  248. vdac_reg: regulator@8 {
  249. regulator-always-on;
  250. };
  251. vaux1_reg: regulator@9 {
  252. regulator-always-on;
  253. };
  254. vaux2_reg: regulator@10 {
  255. regulator-always-on;
  256. };
  257. vaux33_reg: regulator@11 {
  258. regulator-always-on;
  259. };
  260. vmmc_reg: regulator@12 {
  261. regulator-always-on;
  262. };
  263. };
  264. };