am33xx.dtsi 19 KB

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  1. /*
  2. * Device Tree Source for AM33XX SoC
  3. *
  4. * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
  5. *
  6. * This file is licensed under the terms of the GNU General Public License
  7. * version 2. This program is licensed "as is" without any warranty of any
  8. * kind, whether express or implied.
  9. */
  10. #include <dt-bindings/gpio/gpio.h>
  11. #include <dt-bindings/pinctrl/am33xx.h>
  12. #include "skeleton.dtsi"
  13. / {
  14. compatible = "ti,am33xx";
  15. interrupt-parent = <&intc>;
  16. aliases {
  17. i2c0 = &i2c0;
  18. i2c1 = &i2c1;
  19. i2c2 = &i2c2;
  20. serial0 = &uart0;
  21. serial1 = &uart1;
  22. serial2 = &uart2;
  23. serial3 = &uart3;
  24. serial4 = &uart4;
  25. serial5 = &uart5;
  26. d_can0 = &dcan0;
  27. d_can1 = &dcan1;
  28. usb0 = &usb0;
  29. usb1 = &usb1;
  30. phy0 = &usb0_phy;
  31. phy1 = &usb1_phy;
  32. ethernet0 = &cpsw_emac0;
  33. ethernet1 = &cpsw_emac1;
  34. };
  35. cpus {
  36. #address-cells = <1>;
  37. #size-cells = <0>;
  38. cpu@0 {
  39. compatible = "arm,cortex-a8";
  40. device_type = "cpu";
  41. reg = <0>;
  42. /*
  43. * To consider voltage drop between PMIC and SoC,
  44. * tolerance value is reduced to 2% from 4% and
  45. * voltage value is increased as a precaution.
  46. */
  47. operating-points = <
  48. /* kHz uV */
  49. 720000 1285000
  50. 600000 1225000
  51. 500000 1125000
  52. 275000 1125000
  53. >;
  54. voltage-tolerance = <2>; /* 2 percentage */
  55. clocks = <&dpll_mpu_ck>;
  56. clock-names = "cpu";
  57. clock-latency = <300000>; /* From omap-cpufreq driver */
  58. };
  59. };
  60. pmu {
  61. compatible = "arm,cortex-a8-pmu";
  62. interrupts = <3>;
  63. };
  64. /*
  65. * The soc node represents the soc top level view. It is used for IPs
  66. * that are not memory mapped in the MPU view or for the MPU itself.
  67. */
  68. soc {
  69. compatible = "ti,omap-infra";
  70. mpu {
  71. compatible = "ti,omap3-mpu";
  72. ti,hwmods = "mpu";
  73. };
  74. };
  75. am33xx_pinmux: pinmux@44e10800 {
  76. compatible = "pinctrl-single";
  77. reg = <0x44e10800 0x0238>;
  78. #address-cells = <1>;
  79. #size-cells = <0>;
  80. pinctrl-single,register-width = <32>;
  81. pinctrl-single,function-mask = <0x7f>;
  82. };
  83. /*
  84. * XXX: Use a flat representation of the AM33XX interconnect.
  85. * The real AM33XX interconnect network is quite complex. Since
  86. * it will not bring real advantage to represent that in DT
  87. * for the moment, just use a fake OCP bus entry to represent
  88. * the whole bus hierarchy.
  89. */
  90. ocp {
  91. compatible = "simple-bus";
  92. #address-cells = <1>;
  93. #size-cells = <1>;
  94. ranges;
  95. ti,hwmods = "l3_main";
  96. prcm: prcm@44e00000 {
  97. compatible = "ti,am3-prcm";
  98. reg = <0x44e00000 0x4000>;
  99. prcm_clocks: clocks {
  100. #address-cells = <1>;
  101. #size-cells = <0>;
  102. };
  103. prcm_clockdomains: clockdomains {
  104. };
  105. };
  106. scrm: scrm@44e10000 {
  107. compatible = "ti,am3-scrm";
  108. reg = <0x44e10000 0x2000>;
  109. scrm_clocks: clocks {
  110. #address-cells = <1>;
  111. #size-cells = <0>;
  112. };
  113. scrm_clockdomains: clockdomains {
  114. };
  115. };
  116. cm: syscon@44e10000 {
  117. compatible = "ti,am33xx-controlmodule", "syscon";
  118. reg = <0x44e10000 0x800>;
  119. };
  120. intc: interrupt-controller@48200000 {
  121. compatible = "ti,am33xx-intc";
  122. interrupt-controller;
  123. #interrupt-cells = <1>;
  124. reg = <0x48200000 0x1000>;
  125. };
  126. edma: edma@49000000 {
  127. compatible = "ti,edma3";
  128. ti,hwmods = "tpcc", "tptc0", "tptc1", "tptc2";
  129. reg = <0x49000000 0x10000>,
  130. <0x44e10f90 0x40>;
  131. interrupts = <12 13 14>;
  132. #dma-cells = <1>;
  133. };
  134. gpio0: gpio@44e07000 {
  135. compatible = "ti,omap4-gpio";
  136. ti,hwmods = "gpio1";
  137. gpio-controller;
  138. #gpio-cells = <2>;
  139. interrupt-controller;
  140. #interrupt-cells = <2>;
  141. reg = <0x44e07000 0x1000>;
  142. interrupts = <96>;
  143. };
  144. gpio1: gpio@4804c000 {
  145. compatible = "ti,omap4-gpio";
  146. ti,hwmods = "gpio2";
  147. gpio-controller;
  148. #gpio-cells = <2>;
  149. interrupt-controller;
  150. #interrupt-cells = <2>;
  151. reg = <0x4804c000 0x1000>;
  152. interrupts = <98>;
  153. };
  154. gpio2: gpio@481ac000 {
  155. compatible = "ti,omap4-gpio";
  156. ti,hwmods = "gpio3";
  157. gpio-controller;
  158. #gpio-cells = <2>;
  159. interrupt-controller;
  160. #interrupt-cells = <2>;
  161. reg = <0x481ac000 0x1000>;
  162. interrupts = <32>;
  163. };
  164. gpio3: gpio@481ae000 {
  165. compatible = "ti,omap4-gpio";
  166. ti,hwmods = "gpio4";
  167. gpio-controller;
  168. #gpio-cells = <2>;
  169. interrupt-controller;
  170. #interrupt-cells = <2>;
  171. reg = <0x481ae000 0x1000>;
  172. interrupts = <62>;
  173. };
  174. uart0: serial@44e09000 {
  175. compatible = "ti,omap3-uart";
  176. ti,hwmods = "uart1";
  177. clock-frequency = <48000000>;
  178. reg = <0x44e09000 0x2000>;
  179. interrupts = <72>;
  180. status = "disabled";
  181. };
  182. uart1: serial@48022000 {
  183. compatible = "ti,omap3-uart";
  184. ti,hwmods = "uart2";
  185. clock-frequency = <48000000>;
  186. reg = <0x48022000 0x2000>;
  187. interrupts = <73>;
  188. status = "disabled";
  189. };
  190. uart2: serial@48024000 {
  191. compatible = "ti,omap3-uart";
  192. ti,hwmods = "uart3";
  193. clock-frequency = <48000000>;
  194. reg = <0x48024000 0x2000>;
  195. interrupts = <74>;
  196. status = "disabled";
  197. };
  198. uart3: serial@481a6000 {
  199. compatible = "ti,omap3-uart";
  200. ti,hwmods = "uart4";
  201. clock-frequency = <48000000>;
  202. reg = <0x481a6000 0x2000>;
  203. interrupts = <44>;
  204. status = "disabled";
  205. };
  206. uart4: serial@481a8000 {
  207. compatible = "ti,omap3-uart";
  208. ti,hwmods = "uart5";
  209. clock-frequency = <48000000>;
  210. reg = <0x481a8000 0x2000>;
  211. interrupts = <45>;
  212. status = "disabled";
  213. };
  214. uart5: serial@481aa000 {
  215. compatible = "ti,omap3-uart";
  216. ti,hwmods = "uart6";
  217. clock-frequency = <48000000>;
  218. reg = <0x481aa000 0x2000>;
  219. interrupts = <46>;
  220. status = "disabled";
  221. };
  222. i2c0: i2c@44e0b000 {
  223. compatible = "ti,omap4-i2c";
  224. #address-cells = <1>;
  225. #size-cells = <0>;
  226. ti,hwmods = "i2c1";
  227. reg = <0x44e0b000 0x1000>;
  228. interrupts = <70>;
  229. status = "disabled";
  230. };
  231. i2c1: i2c@4802a000 {
  232. compatible = "ti,omap4-i2c";
  233. #address-cells = <1>;
  234. #size-cells = <0>;
  235. ti,hwmods = "i2c2";
  236. reg = <0x4802a000 0x1000>;
  237. interrupts = <71>;
  238. status = "disabled";
  239. };
  240. i2c2: i2c@4819c000 {
  241. compatible = "ti,omap4-i2c";
  242. #address-cells = <1>;
  243. #size-cells = <0>;
  244. ti,hwmods = "i2c3";
  245. reg = <0x4819c000 0x1000>;
  246. interrupts = <30>;
  247. status = "disabled";
  248. };
  249. mmc1: mmc@48060000 {
  250. compatible = "ti,omap4-hsmmc";
  251. ti,hwmods = "mmc1";
  252. ti,dual-volt;
  253. ti,needs-special-reset;
  254. ti,needs-special-hs-handling;
  255. dmas = <&edma 24
  256. &edma 25>;
  257. dma-names = "tx", "rx";
  258. interrupts = <64>;
  259. interrupt-parent = <&intc>;
  260. reg = <0x48060000 0x1000>;
  261. status = "disabled";
  262. };
  263. mmc2: mmc@481d8000 {
  264. compatible = "ti,omap4-hsmmc";
  265. ti,hwmods = "mmc2";
  266. ti,needs-special-reset;
  267. dmas = <&edma 2
  268. &edma 3>;
  269. dma-names = "tx", "rx";
  270. interrupts = <28>;
  271. interrupt-parent = <&intc>;
  272. reg = <0x481d8000 0x1000>;
  273. status = "disabled";
  274. };
  275. mmc3: mmc@47810000 {
  276. compatible = "ti,omap4-hsmmc";
  277. ti,hwmods = "mmc3";
  278. ti,needs-special-reset;
  279. interrupts = <29>;
  280. interrupt-parent = <&intc>;
  281. reg = <0x47810000 0x1000>;
  282. status = "disabled";
  283. };
  284. hwspinlock: spinlock@480ca000 {
  285. compatible = "ti,omap4-hwspinlock";
  286. reg = <0x480ca000 0x1000>;
  287. ti,hwmods = "spinlock";
  288. #hwlock-cells = <1>;
  289. };
  290. wdt2: wdt@44e35000 {
  291. compatible = "ti,omap3-wdt";
  292. ti,hwmods = "wd_timer2";
  293. reg = <0x44e35000 0x1000>;
  294. interrupts = <91>;
  295. };
  296. dcan0: d_can@481cc000 {
  297. compatible = "bosch,d_can";
  298. ti,hwmods = "d_can0";
  299. reg = <0x481cc000 0x2000
  300. 0x44e10644 0x4>;
  301. interrupts = <52>;
  302. status = "disabled";
  303. };
  304. dcan1: d_can@481d0000 {
  305. compatible = "bosch,d_can";
  306. ti,hwmods = "d_can1";
  307. reg = <0x481d0000 0x2000
  308. 0x44e10644 0x4>;
  309. interrupts = <55>;
  310. status = "disabled";
  311. };
  312. mailbox: mailbox@480C8000 {
  313. compatible = "ti,omap4-mailbox";
  314. reg = <0x480C8000 0x200>;
  315. interrupts = <77>;
  316. ti,hwmods = "mailbox";
  317. ti,mbox-num-users = <4>;
  318. ti,mbox-num-fifos = <8>;
  319. mbox_wkupm3: wkup_m3 {
  320. ti,mbox-tx = <0 0 0>;
  321. ti,mbox-rx = <0 0 3>;
  322. };
  323. };
  324. timer1: timer@44e31000 {
  325. compatible = "ti,am335x-timer-1ms";
  326. reg = <0x44e31000 0x400>;
  327. interrupts = <67>;
  328. ti,hwmods = "timer1";
  329. ti,timer-alwon;
  330. };
  331. timer2: timer@48040000 {
  332. compatible = "ti,am335x-timer";
  333. reg = <0x48040000 0x400>;
  334. interrupts = <68>;
  335. ti,hwmods = "timer2";
  336. };
  337. timer3: timer@48042000 {
  338. compatible = "ti,am335x-timer";
  339. reg = <0x48042000 0x400>;
  340. interrupts = <69>;
  341. ti,hwmods = "timer3";
  342. };
  343. timer4: timer@48044000 {
  344. compatible = "ti,am335x-timer";
  345. reg = <0x48044000 0x400>;
  346. interrupts = <92>;
  347. ti,hwmods = "timer4";
  348. ti,timer-pwm;
  349. };
  350. timer5: timer@48046000 {
  351. compatible = "ti,am335x-timer";
  352. reg = <0x48046000 0x400>;
  353. interrupts = <93>;
  354. ti,hwmods = "timer5";
  355. ti,timer-pwm;
  356. };
  357. timer6: timer@48048000 {
  358. compatible = "ti,am335x-timer";
  359. reg = <0x48048000 0x400>;
  360. interrupts = <94>;
  361. ti,hwmods = "timer6";
  362. ti,timer-pwm;
  363. };
  364. timer7: timer@4804a000 {
  365. compatible = "ti,am335x-timer";
  366. reg = <0x4804a000 0x400>;
  367. interrupts = <95>;
  368. ti,hwmods = "timer7";
  369. ti,timer-pwm;
  370. };
  371. rtc: rtc@44e3e000 {
  372. compatible = "ti,da830-rtc";
  373. reg = <0x44e3e000 0x1000>;
  374. interrupts = <75
  375. 76>;
  376. ti,hwmods = "rtc";
  377. };
  378. spi0: spi@48030000 {
  379. compatible = "ti,omap4-mcspi";
  380. #address-cells = <1>;
  381. #size-cells = <0>;
  382. reg = <0x48030000 0x400>;
  383. interrupts = <65>;
  384. ti,spi-num-cs = <2>;
  385. ti,hwmods = "spi0";
  386. dmas = <&edma 16
  387. &edma 17
  388. &edma 18
  389. &edma 19>;
  390. dma-names = "tx0", "rx0", "tx1", "rx1";
  391. status = "disabled";
  392. };
  393. spi1: spi@481a0000 {
  394. compatible = "ti,omap4-mcspi";
  395. #address-cells = <1>;
  396. #size-cells = <0>;
  397. reg = <0x481a0000 0x400>;
  398. interrupts = <125>;
  399. ti,spi-num-cs = <2>;
  400. ti,hwmods = "spi1";
  401. dmas = <&edma 42
  402. &edma 43
  403. &edma 44
  404. &edma 45>;
  405. dma-names = "tx0", "rx0", "tx1", "rx1";
  406. status = "disabled";
  407. };
  408. usb: usb@47400000 {
  409. compatible = "ti,am33xx-usb";
  410. reg = <0x47400000 0x1000>;
  411. ranges;
  412. #address-cells = <1>;
  413. #size-cells = <1>;
  414. ti,hwmods = "usb_otg_hs";
  415. status = "disabled";
  416. usb_ctrl_mod: control@44e10620 {
  417. compatible = "ti,am335x-usb-ctrl-module";
  418. reg = <0x44e10620 0x10
  419. 0x44e10648 0x4>;
  420. reg-names = "phy_ctrl", "wakeup";
  421. status = "disabled";
  422. };
  423. usb0_phy: usb-phy@47401300 {
  424. compatible = "ti,am335x-usb-phy";
  425. reg = <0x47401300 0x100>;
  426. reg-names = "phy";
  427. status = "disabled";
  428. ti,ctrl_mod = <&usb_ctrl_mod>;
  429. };
  430. usb0: usb@47401000 {
  431. compatible = "ti,musb-am33xx";
  432. status = "disabled";
  433. reg = <0x47401400 0x400
  434. 0x47401000 0x200>;
  435. reg-names = "mc", "control";
  436. interrupts = <18>;
  437. interrupt-names = "mc";
  438. dr_mode = "otg";
  439. mentor,multipoint = <1>;
  440. mentor,num-eps = <16>;
  441. mentor,ram-bits = <12>;
  442. mentor,power = <500>;
  443. phys = <&usb0_phy>;
  444. dmas = <&cppi41dma 0 0 &cppi41dma 1 0
  445. &cppi41dma 2 0 &cppi41dma 3 0
  446. &cppi41dma 4 0 &cppi41dma 5 0
  447. &cppi41dma 6 0 &cppi41dma 7 0
  448. &cppi41dma 8 0 &cppi41dma 9 0
  449. &cppi41dma 10 0 &cppi41dma 11 0
  450. &cppi41dma 12 0 &cppi41dma 13 0
  451. &cppi41dma 14 0 &cppi41dma 0 1
  452. &cppi41dma 1 1 &cppi41dma 2 1
  453. &cppi41dma 3 1 &cppi41dma 4 1
  454. &cppi41dma 5 1 &cppi41dma 6 1
  455. &cppi41dma 7 1 &cppi41dma 8 1
  456. &cppi41dma 9 1 &cppi41dma 10 1
  457. &cppi41dma 11 1 &cppi41dma 12 1
  458. &cppi41dma 13 1 &cppi41dma 14 1>;
  459. dma-names =
  460. "rx1", "rx2", "rx3", "rx4", "rx5", "rx6", "rx7",
  461. "rx8", "rx9", "rx10", "rx11", "rx12", "rx13",
  462. "rx14", "rx15",
  463. "tx1", "tx2", "tx3", "tx4", "tx5", "tx6", "tx7",
  464. "tx8", "tx9", "tx10", "tx11", "tx12", "tx13",
  465. "tx14", "tx15";
  466. };
  467. usb1_phy: usb-phy@47401b00 {
  468. compatible = "ti,am335x-usb-phy";
  469. reg = <0x47401b00 0x100>;
  470. reg-names = "phy";
  471. status = "disabled";
  472. ti,ctrl_mod = <&usb_ctrl_mod>;
  473. };
  474. usb1: usb@47401800 {
  475. compatible = "ti,musb-am33xx";
  476. status = "disabled";
  477. reg = <0x47401c00 0x400
  478. 0x47401800 0x200>;
  479. reg-names = "mc", "control";
  480. interrupts = <19>;
  481. interrupt-names = "mc";
  482. dr_mode = "otg";
  483. mentor,multipoint = <1>;
  484. mentor,num-eps = <16>;
  485. mentor,ram-bits = <12>;
  486. mentor,power = <500>;
  487. phys = <&usb1_phy>;
  488. dmas = <&cppi41dma 15 0 &cppi41dma 16 0
  489. &cppi41dma 17 0 &cppi41dma 18 0
  490. &cppi41dma 19 0 &cppi41dma 20 0
  491. &cppi41dma 21 0 &cppi41dma 22 0
  492. &cppi41dma 23 0 &cppi41dma 24 0
  493. &cppi41dma 25 0 &cppi41dma 26 0
  494. &cppi41dma 27 0 &cppi41dma 28 0
  495. &cppi41dma 29 0 &cppi41dma 15 1
  496. &cppi41dma 16 1 &cppi41dma 17 1
  497. &cppi41dma 18 1 &cppi41dma 19 1
  498. &cppi41dma 20 1 &cppi41dma 21 1
  499. &cppi41dma 22 1 &cppi41dma 23 1
  500. &cppi41dma 24 1 &cppi41dma 25 1
  501. &cppi41dma 26 1 &cppi41dma 27 1
  502. &cppi41dma 28 1 &cppi41dma 29 1>;
  503. dma-names =
  504. "rx1", "rx2", "rx3", "rx4", "rx5", "rx6", "rx7",
  505. "rx8", "rx9", "rx10", "rx11", "rx12", "rx13",
  506. "rx14", "rx15",
  507. "tx1", "tx2", "tx3", "tx4", "tx5", "tx6", "tx7",
  508. "tx8", "tx9", "tx10", "tx11", "tx12", "tx13",
  509. "tx14", "tx15";
  510. };
  511. cppi41dma: dma-controller@47402000 {
  512. compatible = "ti,am3359-cppi41";
  513. reg = <0x47400000 0x1000
  514. 0x47402000 0x1000
  515. 0x47403000 0x1000
  516. 0x47404000 0x4000>;
  517. reg-names = "glue", "controller", "scheduler", "queuemgr";
  518. interrupts = <17>;
  519. interrupt-names = "glue";
  520. #dma-cells = <2>;
  521. #dma-channels = <30>;
  522. #dma-requests = <256>;
  523. status = "disabled";
  524. };
  525. };
  526. epwmss0: epwmss@48300000 {
  527. compatible = "ti,am33xx-pwmss";
  528. reg = <0x48300000 0x10>;
  529. ti,hwmods = "epwmss0";
  530. #address-cells = <1>;
  531. #size-cells = <1>;
  532. status = "disabled";
  533. ranges = <0x48300100 0x48300100 0x80 /* ECAP */
  534. 0x48300180 0x48300180 0x80 /* EQEP */
  535. 0x48300200 0x48300200 0x80>; /* EHRPWM */
  536. ecap0: ecap@48300100 {
  537. compatible = "ti,am33xx-ecap";
  538. #pwm-cells = <3>;
  539. reg = <0x48300100 0x80>;
  540. interrupts = <31>;
  541. interrupt-names = "ecap0";
  542. ti,hwmods = "ecap0";
  543. status = "disabled";
  544. };
  545. ehrpwm0: ehrpwm@48300200 {
  546. compatible = "ti,am33xx-ehrpwm";
  547. #pwm-cells = <3>;
  548. reg = <0x48300200 0x80>;
  549. ti,hwmods = "ehrpwm0";
  550. status = "disabled";
  551. };
  552. };
  553. epwmss1: epwmss@48302000 {
  554. compatible = "ti,am33xx-pwmss";
  555. reg = <0x48302000 0x10>;
  556. ti,hwmods = "epwmss1";
  557. #address-cells = <1>;
  558. #size-cells = <1>;
  559. status = "disabled";
  560. ranges = <0x48302100 0x48302100 0x80 /* ECAP */
  561. 0x48302180 0x48302180 0x80 /* EQEP */
  562. 0x48302200 0x48302200 0x80>; /* EHRPWM */
  563. ecap1: ecap@48302100 {
  564. compatible = "ti,am33xx-ecap";
  565. #pwm-cells = <3>;
  566. reg = <0x48302100 0x80>;
  567. interrupts = <47>;
  568. interrupt-names = "ecap1";
  569. ti,hwmods = "ecap1";
  570. status = "disabled";
  571. };
  572. ehrpwm1: ehrpwm@48302200 {
  573. compatible = "ti,am33xx-ehrpwm";
  574. #pwm-cells = <3>;
  575. reg = <0x48302200 0x80>;
  576. ti,hwmods = "ehrpwm1";
  577. status = "disabled";
  578. };
  579. };
  580. epwmss2: epwmss@48304000 {
  581. compatible = "ti,am33xx-pwmss";
  582. reg = <0x48304000 0x10>;
  583. ti,hwmods = "epwmss2";
  584. #address-cells = <1>;
  585. #size-cells = <1>;
  586. status = "disabled";
  587. ranges = <0x48304100 0x48304100 0x80 /* ECAP */
  588. 0x48304180 0x48304180 0x80 /* EQEP */
  589. 0x48304200 0x48304200 0x80>; /* EHRPWM */
  590. ecap2: ecap@48304100 {
  591. compatible = "ti,am33xx-ecap";
  592. #pwm-cells = <3>;
  593. reg = <0x48304100 0x80>;
  594. interrupts = <61>;
  595. interrupt-names = "ecap2";
  596. ti,hwmods = "ecap2";
  597. status = "disabled";
  598. };
  599. ehrpwm2: ehrpwm@48304200 {
  600. compatible = "ti,am33xx-ehrpwm";
  601. #pwm-cells = <3>;
  602. reg = <0x48304200 0x80>;
  603. ti,hwmods = "ehrpwm2";
  604. status = "disabled";
  605. };
  606. };
  607. mac: ethernet@4a100000 {
  608. compatible = "ti,cpsw";
  609. ti,hwmods = "cpgmac0";
  610. clocks = <&cpsw_125mhz_gclk>, <&cpsw_cpts_rft_clk>;
  611. clock-names = "fck", "cpts";
  612. cpdma_channels = <8>;
  613. ale_entries = <1024>;
  614. bd_ram_size = <0x2000>;
  615. no_bd_ram = <0>;
  616. rx_descs = <64>;
  617. mac_control = <0x20>;
  618. slaves = <2>;
  619. active_slave = <0>;
  620. cpts_clock_mult = <0x80000000>;
  621. cpts_clock_shift = <29>;
  622. reg = <0x4a100000 0x800
  623. 0x4a101200 0x100>;
  624. #address-cells = <1>;
  625. #size-cells = <1>;
  626. interrupt-parent = <&intc>;
  627. /*
  628. * c0_rx_thresh_pend
  629. * c0_rx_pend
  630. * c0_tx_pend
  631. * c0_misc_pend
  632. */
  633. interrupts = <40 41 42 43>;
  634. ranges;
  635. syscon = <&cm>;
  636. status = "disabled";
  637. davinci_mdio: mdio@4a101000 {
  638. compatible = "ti,davinci_mdio";
  639. #address-cells = <1>;
  640. #size-cells = <0>;
  641. ti,hwmods = "davinci_mdio";
  642. bus_freq = <1000000>;
  643. reg = <0x4a101000 0x100>;
  644. status = "disabled";
  645. };
  646. cpsw_emac0: slave@4a100200 {
  647. /* Filled in by U-Boot */
  648. mac-address = [ 00 00 00 00 00 00 ];
  649. };
  650. cpsw_emac1: slave@4a100300 {
  651. /* Filled in by U-Boot */
  652. mac-address = [ 00 00 00 00 00 00 ];
  653. };
  654. phy_sel: cpsw-phy-sel@44e10650 {
  655. compatible = "ti,am3352-cpsw-phy-sel";
  656. reg= <0x44e10650 0x4>;
  657. reg-names = "gmii-sel";
  658. };
  659. };
  660. ocmcram: ocmcram@40300000 {
  661. compatible = "mmio-sram";
  662. reg = <0x40300000 0x10000>; /* 64k */
  663. };
  664. wkup_m3: wkup_m3@44d00000 {
  665. compatible = "ti,am3353-wkup-m3";
  666. reg = <0x44d00000 0x4000 /* M3 UMEM */
  667. 0x44d80000 0x2000>; /* M3 DMEM */
  668. ti,hwmods = "wkup_m3";
  669. ti,no-reset-on-init;
  670. };
  671. elm: elm@48080000 {
  672. compatible = "ti,am3352-elm";
  673. reg = <0x48080000 0x2000>;
  674. interrupts = <4>;
  675. ti,hwmods = "elm";
  676. status = "disabled";
  677. };
  678. lcdc: lcdc@4830e000 {
  679. compatible = "ti,am33xx-tilcdc";
  680. reg = <0x4830e000 0x1000>;
  681. interrupt-parent = <&intc>;
  682. interrupts = <36>;
  683. ti,hwmods = "lcdc";
  684. status = "disabled";
  685. };
  686. tscadc: tscadc@44e0d000 {
  687. compatible = "ti,am3359-tscadc";
  688. reg = <0x44e0d000 0x1000>;
  689. interrupt-parent = <&intc>;
  690. interrupts = <16>;
  691. ti,hwmods = "adc_tsc";
  692. status = "disabled";
  693. tsc {
  694. compatible = "ti,am3359-tsc";
  695. };
  696. am335x_adc: adc {
  697. #io-channel-cells = <1>;
  698. compatible = "ti,am3359-adc";
  699. };
  700. };
  701. gpmc: gpmc@50000000 {
  702. compatible = "ti,am3352-gpmc";
  703. ti,hwmods = "gpmc";
  704. ti,no-idle-on-init;
  705. reg = <0x50000000 0x2000>;
  706. interrupts = <100>;
  707. gpmc,num-cs = <7>;
  708. gpmc,num-waitpins = <2>;
  709. #address-cells = <2>;
  710. #size-cells = <1>;
  711. status = "disabled";
  712. };
  713. sham: sham@53100000 {
  714. compatible = "ti,omap4-sham";
  715. ti,hwmods = "sham";
  716. reg = <0x53100000 0x200>;
  717. interrupts = <109>;
  718. dmas = <&edma 36>;
  719. dma-names = "rx";
  720. };
  721. aes: aes@53500000 {
  722. compatible = "ti,omap4-aes";
  723. ti,hwmods = "aes";
  724. reg = <0x53500000 0xa0>;
  725. interrupts = <103>;
  726. dmas = <&edma 6>,
  727. <&edma 5>;
  728. dma-names = "tx", "rx";
  729. };
  730. mcasp0: mcasp@48038000 {
  731. compatible = "ti,am33xx-mcasp-audio";
  732. ti,hwmods = "mcasp0";
  733. reg = <0x48038000 0x2000>,
  734. <0x46000000 0x400000>;
  735. reg-names = "mpu", "dat";
  736. interrupts = <80>, <81>;
  737. interrupt-names = "tx", "rx";
  738. status = "disabled";
  739. dmas = <&edma 8>,
  740. <&edma 9>;
  741. dma-names = "tx", "rx";
  742. };
  743. mcasp1: mcasp@4803C000 {
  744. compatible = "ti,am33xx-mcasp-audio";
  745. ti,hwmods = "mcasp1";
  746. reg = <0x4803C000 0x2000>,
  747. <0x46400000 0x400000>;
  748. reg-names = "mpu", "dat";
  749. interrupts = <82>, <83>;
  750. interrupt-names = "tx", "rx";
  751. status = "disabled";
  752. dmas = <&edma 10>,
  753. <&edma 11>;
  754. dma-names = "tx", "rx";
  755. };
  756. rng: rng@48310000 {
  757. compatible = "ti,omap4-rng";
  758. ti,hwmods = "rng";
  759. reg = <0x48310000 0x2000>;
  760. interrupts = <111>;
  761. };
  762. };
  763. };
  764. /include/ "am33xx-clocks.dtsi"