armada-375-db.dts 3.2 KB

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  1. /*
  2. * Device Tree file for Marvell Armada 375 evaluation board
  3. * (DB-88F6720)
  4. *
  5. * Copyright (C) 2014 Marvell
  6. *
  7. * Gregory CLEMENT <gregory.clement@free-electrons.com>
  8. * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
  9. *
  10. * This file is licensed under the terms of the GNU General Public
  11. * License version 2. This program is licensed "as is" without any
  12. * warranty of any kind, whether express or implied.
  13. */
  14. /dts-v1/;
  15. #include <dt-bindings/gpio/gpio.h>
  16. #include "armada-375.dtsi"
  17. / {
  18. model = "Marvell Armada 375 Development Board";
  19. compatible = "marvell,a375-db", "marvell,armada375";
  20. chosen {
  21. bootargs = "console=ttyS0,115200 earlyprintk";
  22. };
  23. memory {
  24. device_type = "memory";
  25. reg = <0x00000000 0x40000000>; /* 1 GB */
  26. };
  27. soc {
  28. ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000
  29. MBUS_ID(0x01, 0x1d) 0 0xfff00000 0x100000>;
  30. internal-regs {
  31. spi@10600 {
  32. pinctrl-0 = <&spi0_pins>;
  33. pinctrl-names = "default";
  34. /*
  35. * SPI conflicts with NAND, so we disable it
  36. * here, and select NAND as the enabled device
  37. * by default.
  38. */
  39. status = "disabled";
  40. spi-flash@0 {
  41. #address-cells = <1>;
  42. #size-cells = <1>;
  43. compatible = "n25q128a13";
  44. reg = <0>; /* Chip select 0 */
  45. spi-max-frequency = <108000000>;
  46. };
  47. };
  48. i2c@11000 {
  49. status = "okay";
  50. clock-frequency = <100000>;
  51. pinctrl-0 = <&i2c0_pins>;
  52. pinctrl-names = "default";
  53. };
  54. i2c@11100 {
  55. status = "okay";
  56. clock-frequency = <100000>;
  57. pinctrl-0 = <&i2c1_pins>;
  58. pinctrl-names = "default";
  59. };
  60. serial@12000 {
  61. status = "okay";
  62. };
  63. pinctrl {
  64. sdio_st_pins: sdio-st-pins {
  65. marvell,pins = "mpp44", "mpp45";
  66. marvell,function = "gpio";
  67. };
  68. };
  69. sata@a0000 {
  70. status = "okay";
  71. nr-ports = <2>;
  72. };
  73. nand: nand@d0000 {
  74. pinctrl-0 = <&nand_pins>;
  75. pinctrl-names = "default";
  76. status = "okay";
  77. num-cs = <1>;
  78. marvell,nand-keep-config;
  79. marvell,nand-enable-arbiter;
  80. nand-on-flash-bbt;
  81. nand-ecc-strength = <4>;
  82. nand-ecc-step-size = <512>;
  83. partition@0 {
  84. label = "U-Boot";
  85. reg = <0 0x800000>;
  86. };
  87. partition@800000 {
  88. label = "Linux";
  89. reg = <0x800000 0x800000>;
  90. };
  91. partition@1000000 {
  92. label = "Filesystem";
  93. reg = <0x1000000 0x3f000000>;
  94. };
  95. };
  96. usb@54000 {
  97. status = "okay";
  98. };
  99. usb3@58000 {
  100. status = "okay";
  101. };
  102. mvsdio@d4000 {
  103. pinctrl-0 = <&sdio_pins &sdio_st_pins>;
  104. pinctrl-names = "default";
  105. status = "okay";
  106. cd-gpios = <&gpio1 12 GPIO_ACTIVE_HIGH>;
  107. wp-gpios = <&gpio1 13 GPIO_ACTIVE_HIGH>;
  108. };
  109. mdio {
  110. phy0: ethernet-phy@0 {
  111. reg = <0>;
  112. };
  113. phy3: ethernet-phy@3 {
  114. reg = <3>;
  115. };
  116. };
  117. ethernet@f0000 {
  118. status = "okay";
  119. eth0@c4000 {
  120. status = "okay";
  121. phy = <&phy0>;
  122. phy-mode = "rgmii-id";
  123. };
  124. eth1@c5000 {
  125. status = "okay";
  126. phy = <&phy3>;
  127. phy-mode = "gmii";
  128. };
  129. };
  130. };
  131. pcie-controller {
  132. status = "okay";
  133. /*
  134. * The two PCIe units are accessible through
  135. * standard PCIe slots on the board.
  136. */
  137. pcie@1,0 {
  138. /* Port 0, Lane 0 */
  139. status = "okay";
  140. };
  141. pcie@2,0 {
  142. /* Port 1, Lane 0 */
  143. status = "okay";
  144. };
  145. };
  146. };
  147. };