armada-xp-axpwifiap.dts 3.4 KB

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  1. /*
  2. * Device Tree file for Marvell RD-AXPWiFiAP.
  3. *
  4. * Note: this board is shipped with a new generation boot loader that
  5. * remaps internal registers at 0xf1000000. Therefore, if earlyprintk
  6. * is used, the CONFIG_DEBUG_MVEBU_UART_ALTERNATE option should be
  7. * used.
  8. *
  9. * Copyright (C) 2013 Marvell
  10. *
  11. * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
  12. *
  13. * This file is licensed under the terms of the GNU General Public
  14. * License version 2. This program is licensed "as is" without any
  15. * warranty of any kind, whether express or implied.
  16. */
  17. /dts-v1/;
  18. #include <dt-bindings/gpio/gpio.h>
  19. #include <dt-bindings/input/input.h>
  20. #include "armada-xp-mv78230.dtsi"
  21. / {
  22. model = "Marvell RD-AXPWiFiAP";
  23. compatible = "marvell,rd-axpwifiap", "marvell,armadaxp-mv78230", "marvell,armadaxp", "marvell,armada-370-xp";
  24. chosen {
  25. bootargs = "console=ttyS0,115200 earlyprintk";
  26. };
  27. memory {
  28. device_type = "memory";
  29. reg = <0x00000000 0x00000000 0x00000000 0x40000000>; /* 1GB */
  30. };
  31. soc {
  32. ranges = <MBUS_ID(0xf0, 0x01) 0 0 0xf1000000 0x100000
  33. MBUS_ID(0x01, 0x1d) 0 0 0xfff00000 0x100000>;
  34. pcie-controller {
  35. status = "okay";
  36. /* First mini-PCIe port */
  37. pcie@1,0 {
  38. /* Port 0, Lane 0 */
  39. status = "okay";
  40. };
  41. /* Second mini-PCIe port */
  42. pcie@2,0 {
  43. /* Port 0, Lane 1 */
  44. status = "okay";
  45. };
  46. /* Renesas uPD720202 USB 3.0 controller */
  47. pcie@3,0 {
  48. /* Port 0, Lane 3 */
  49. status = "okay";
  50. };
  51. };
  52. internal-regs {
  53. pinctrl {
  54. pinctrl-0 = <&pmx_phy_int>;
  55. pinctrl-names = "default";
  56. pmx_ge0: pmx-ge0 {
  57. marvell,pins = "mpp0", "mpp1", "mpp2", "mpp3",
  58. "mpp4", "mpp5", "mpp6", "mpp7",
  59. "mpp8", "mpp9", "mpp10", "mpp11";
  60. marvell,function = "ge0";
  61. };
  62. pmx_ge1: pmx-ge1 {
  63. marvell,pins = "mpp12", "mpp13", "mpp14", "mpp15",
  64. "mpp16", "mpp17", "mpp18", "mpp19",
  65. "mpp20", "mpp21", "mpp22", "mpp23";
  66. marvell,function = "ge1";
  67. };
  68. pmx_keys: pmx-keys {
  69. marvell,pins = "mpp33";
  70. marvell,function = "gpio";
  71. };
  72. pmx_spi: pmx-spi {
  73. marvell,pins = "mpp36", "mpp37", "mpp38", "mpp39";
  74. marvell,function = "spi";
  75. };
  76. pmx_phy_int: pmx-phy-int {
  77. marvell,pins = "mpp32";
  78. marvell,function = "gpio";
  79. };
  80. };
  81. serial@12000 {
  82. status = "okay";
  83. };
  84. serial@12100 {
  85. status = "okay";
  86. };
  87. sata@a0000 {
  88. nr-ports = <1>;
  89. status = "okay";
  90. };
  91. mdio {
  92. phy0: ethernet-phy@0 {
  93. reg = <0>;
  94. };
  95. phy1: ethernet-phy@1 {
  96. reg = <1>;
  97. };
  98. };
  99. ethernet@70000 {
  100. pinctrl-0 = <&pmx_ge0>;
  101. pinctrl-names = "default";
  102. status = "okay";
  103. phy = <&phy0>;
  104. phy-mode = "rgmii-id";
  105. };
  106. ethernet@74000 {
  107. pinctrl-0 = <&pmx_ge1>;
  108. pinctrl-names = "default";
  109. status = "okay";
  110. phy = <&phy1>;
  111. phy-mode = "rgmii-id";
  112. };
  113. spi0: spi@10600 {
  114. status = "okay";
  115. pinctrl-0 = <&pmx_spi>;
  116. pinctrl-names = "default";
  117. spi-flash@0 {
  118. #address-cells = <1>;
  119. #size-cells = <1>;
  120. compatible = "n25q128a13";
  121. reg = <0>; /* Chip select 0 */
  122. spi-max-frequency = <108000000>;
  123. };
  124. };
  125. };
  126. };
  127. gpio_keys {
  128. compatible = "gpio-keys";
  129. #address-cells = <1>;
  130. #size-cells = <0>;
  131. pinctrl-0 = <&pmx_keys>;
  132. pinctrl-names = "default";
  133. button@1 {
  134. label = "Factory Reset Button";
  135. linux,code = <KEY_SETUP>;
  136. gpios = <&gpio1 1 GPIO_ACTIVE_LOW>;
  137. };
  138. };
  139. };