at91sam9261.dtsi 20 KB

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  1. /*
  2. * at91sam9261.dtsi - Device Tree Include file for AT91SAM9261 SoC
  3. *
  4. * Copyright (C) 2013 Jean-Jacques Hiblot <jjhiblot@traphandler.com>
  5. *
  6. * Licensed under GPLv2 only.
  7. */
  8. #include "skeleton.dtsi"
  9. #include <dt-bindings/pinctrl/at91.h>
  10. #include <dt-bindings/interrupt-controller/irq.h>
  11. #include <dt-bindings/gpio/gpio.h>
  12. #include <dt-bindings/clock/at91.h>
  13. / {
  14. model = "Atmel AT91SAM9261 family SoC";
  15. compatible = "atmel,at91sam9261";
  16. interrupt-parent = <&aic>;
  17. aliases {
  18. serial0 = &dbgu;
  19. serial1 = &usart0;
  20. serial2 = &usart1;
  21. serial3 = &usart2;
  22. gpio0 = &pioA;
  23. gpio1 = &pioB;
  24. gpio2 = &pioC;
  25. tcb0 = &tcb0;
  26. i2c0 = &i2c0;
  27. ssc0 = &ssc0;
  28. ssc1 = &ssc1;
  29. ssc2 = &ssc2;
  30. };
  31. cpus {
  32. #address-cells = <0>;
  33. #size-cells = <0>;
  34. cpu {
  35. compatible = "arm,arm926ej-s";
  36. device_type = "cpu";
  37. };
  38. };
  39. memory {
  40. reg = <0x20000000 0x08000000>;
  41. };
  42. clocks {
  43. main_xtal: main_xtal {
  44. compatible = "fixed-clock";
  45. #clock-cells = <0>;
  46. clock-frequency = <0>;
  47. };
  48. slow_xtal: slow_xtal {
  49. compatible = "fixed-clock";
  50. #clock-cells = <0>;
  51. clock-frequency = <0>;
  52. };
  53. };
  54. ahb {
  55. compatible = "simple-bus";
  56. #address-cells = <1>;
  57. #size-cells = <1>;
  58. ranges;
  59. usb0: ohci@00500000 {
  60. compatible = "atmel,at91rm9200-ohci", "usb-ohci";
  61. reg = <0x00500000 0x100000>;
  62. interrupts = <20 IRQ_TYPE_LEVEL_HIGH 2>;
  63. clocks = <&usb>, <&ohci_clk>, <&hclk0>, <&uhpck>;
  64. clock-names = "usb_clk", "ohci_clk", "hclk", "uhpck";
  65. status = "disabled";
  66. };
  67. fb0: fb@0x00600000 {
  68. compatible = "atmel,at91sam9261-lcdc";
  69. reg = <0x00600000 0x1000>;
  70. interrupts = <21 IRQ_TYPE_LEVEL_HIGH 3>;
  71. pinctrl-names = "default";
  72. pinctrl-0 = <&pinctrl_fb>;
  73. clocks = <&lcd_clk>, <&hclk1>;
  74. clock-names = "lcdc_clk", "hclk";
  75. status = "disabled";
  76. };
  77. nand0: nand@40000000 {
  78. compatible = "atmel,at91rm9200-nand";
  79. #address-cells = <1>;
  80. #size-cells = <1>;
  81. reg = <0x40000000 0x10000000>;
  82. atmel,nand-addr-offset = <22>;
  83. atmel,nand-cmd-offset = <21>;
  84. pinctrl-names = "default";
  85. pinctrl-0 = <&pinctrl_nand>;
  86. gpios = <&pioC 15 GPIO_ACTIVE_HIGH>,
  87. <&pioC 14 GPIO_ACTIVE_HIGH>,
  88. <0>;
  89. status = "disabled";
  90. };
  91. apb {
  92. compatible = "simple-bus";
  93. #address-cells = <1>;
  94. #size-cells = <1>;
  95. ranges;
  96. tcb0: timer@fffa0000 {
  97. compatible = "atmel,at91rm9200-tcb";
  98. reg = <0xfffa0000 0x100>;
  99. interrupts = <17 IRQ_TYPE_LEVEL_HIGH 0>,
  100. <18 IRQ_TYPE_LEVEL_HIGH 0>,
  101. <19 IRQ_TYPE_LEVEL_HIGH 0>;
  102. clocks = <&tc0_clk>, <&tc1_clk>, <&tc2_clk>;
  103. clock-names = "t0_clk", "t1_clk", "t2_clk";
  104. };
  105. usb1: gadget@fffa4000 {
  106. compatible = "atmel,at91rm9200-udc";
  107. reg = <0xfffa4000 0x4000>;
  108. interrupts = <10 IRQ_TYPE_LEVEL_HIGH 2>;
  109. clocks = <&usb>, <&udc_clk>, <&udpck>;
  110. clock-names = "usb_clk", "udc_clk", "udpck";
  111. status = "disabled";
  112. };
  113. mmc0: mmc@fffa8000 {
  114. compatible = "atmel,hsmci";
  115. reg = <0xfffa8000 0x600>;
  116. interrupts = <9 IRQ_TYPE_LEVEL_HIGH 0>;
  117. pinctrl-names = "default";
  118. pinctrl-0 = <&pinctrl_mmc0_clk>, <&pinctrl_mmc0_slot0_cmd_dat0>, <&pinctrl_mmc0_slot0_dat1_3>;
  119. #address-cells = <1>;
  120. #size-cells = <0>;
  121. clocks = <&mci0_clk>;
  122. clock-names = "mci_clk";
  123. status = "disabled";
  124. };
  125. i2c0: i2c@fffac000 {
  126. compatible = "atmel,at91sam9261-i2c";
  127. pinctrl-names = "default";
  128. pinctrl-0 = <&pinctrl_i2c_twi>;
  129. reg = <0xfffac000 0x100>;
  130. interrupts = <11 IRQ_TYPE_LEVEL_HIGH 6>;
  131. #address-cells = <1>;
  132. #size-cells = <0>;
  133. clocks = <&twi0_clk>;
  134. status = "disabled";
  135. };
  136. usart0: serial@fffb0000 {
  137. compatible = "atmel,at91sam9260-usart";
  138. reg = <0xfffb0000 0x200>;
  139. interrupts = <6 IRQ_TYPE_LEVEL_HIGH 5>;
  140. atmel,use-dma-rx;
  141. atmel,use-dma-tx;
  142. pinctrl-names = "default";
  143. pinctrl-0 = <&pinctrl_usart0>;
  144. clocks = <&usart0_clk>;
  145. clock-names = "usart";
  146. status = "disabled";
  147. };
  148. usart1: serial@fffb4000 {
  149. compatible = "atmel,at91sam9260-usart";
  150. reg = <0xfffb4000 0x200>;
  151. interrupts = <7 IRQ_TYPE_LEVEL_HIGH 5>;
  152. atmel,use-dma-rx;
  153. atmel,use-dma-tx;
  154. pinctrl-names = "default";
  155. pinctrl-0 = <&pinctrl_usart1>;
  156. clocks = <&usart1_clk>;
  157. clock-names = "usart";
  158. status = "disabled";
  159. };
  160. usart2: serial@fffb8000{
  161. compatible = "atmel,at91sam9260-usart";
  162. reg = <0xfffb8000 0x200>;
  163. interrupts = <8 IRQ_TYPE_LEVEL_HIGH 5>;
  164. atmel,use-dma-rx;
  165. atmel,use-dma-tx;
  166. pinctrl-names = "default";
  167. pinctrl-0 = <&pinctrl_usart2>;
  168. clocks = <&usart2_clk>;
  169. clock-names = "usart";
  170. status = "disabled";
  171. };
  172. ssc0: ssc@fffbc000 {
  173. compatible = "atmel,at91rm9200-ssc";
  174. reg = <0xfffbc000 0x4000>;
  175. interrupts = <14 IRQ_TYPE_LEVEL_HIGH 5>;
  176. pinctrl-names = "default";
  177. pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>;
  178. clocks = <&ssc0_clk>;
  179. clock-names = "pclk";
  180. status = "disabled";
  181. };
  182. ssc1: ssc@fffc0000 {
  183. compatible = "atmel,at91rm9200-ssc";
  184. reg = <0xfffc0000 0x4000>;
  185. interrupts = <15 IRQ_TYPE_LEVEL_HIGH 5>;
  186. pinctrl-names = "default";
  187. pinctrl-0 = <&pinctrl_ssc1_tx &pinctrl_ssc1_rx>;
  188. clocks = <&ssc1_clk>;
  189. clock-names = "pclk";
  190. status = "disabled";
  191. };
  192. ssc2: ssc@fffc4000 {
  193. compatible = "atmel,at91rm9200-ssc";
  194. reg = <0xfffc4000 0x4000>;
  195. interrupts = <16 IRQ_TYPE_LEVEL_HIGH 5>;
  196. pinctrl-names = "default";
  197. pinctrl-0 = <&pinctrl_ssc2_tx &pinctrl_ssc2_rx>;
  198. clocks = <&ssc2_clk>;
  199. clock-names = "pclk";
  200. status = "disabled";
  201. };
  202. spi0: spi@fffc8000 {
  203. #address-cells = <1>;
  204. #size-cells = <0>;
  205. compatible = "atmel,at91rm9200-spi";
  206. reg = <0xfffc8000 0x200>;
  207. cs-gpios = <0>, <0>, <0>, <0>;
  208. interrupts = <12 IRQ_TYPE_LEVEL_HIGH 3>;
  209. pinctrl-names = "default";
  210. pinctrl-0 = <&pinctrl_spi0>;
  211. clocks = <&spi0_clk>;
  212. clock-names = "spi_clk";
  213. status = "disabled";
  214. };
  215. spi1: spi@fffcc000 {
  216. #address-cells = <1>;
  217. #size-cells = <0>;
  218. compatible = "atmel,at91rm9200-spi";
  219. reg = <0xfffcc000 0x200>;
  220. interrupts = <13 IRQ_TYPE_LEVEL_HIGH 3>;
  221. pinctrl-names = "default";
  222. pinctrl-0 = <&pinctrl_spi1>;
  223. clocks = <&spi1_clk>;
  224. clock-names = "spi_clk";
  225. status = "disabled";
  226. };
  227. ramc: ramc@ffffea00 {
  228. compatible = "atmel,at91sam9260-sdramc";
  229. reg = <0xffffea00 0x200>;
  230. };
  231. matrix: matrix@ffffee00 {
  232. compatible = "atmel,at91sam9260-bus-matrix";
  233. reg = <0xffffee00 0x200>;
  234. };
  235. aic: interrupt-controller@fffff000 {
  236. #interrupt-cells = <3>;
  237. compatible = "atmel,at91rm9200-aic";
  238. interrupt-controller;
  239. reg = <0xfffff000 0x200>;
  240. atmel,external-irqs = <29 30 31>;
  241. };
  242. dbgu: serial@fffff200 {
  243. compatible = "atmel,at91sam9260-usart";
  244. reg = <0xfffff200 0x200>;
  245. interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
  246. pinctrl-names = "default";
  247. pinctrl-0 = <&pinctrl_dbgu>;
  248. clocks = <&mck>;
  249. clock-names = "usart";
  250. status = "disabled";
  251. };
  252. pinctrl@fffff400 {
  253. #address-cells = <1>;
  254. #size-cells = <1>;
  255. compatible = "atmel,at91rm9200-pinctrl", "simple-bus";
  256. ranges = <0xfffff400 0xfffff400 0x600>;
  257. atmel,mux-mask =
  258. /* A B */
  259. <0xffffffff 0xfffffff7>, /* pioA */
  260. <0xffffffff 0xfffffff4>, /* pioB */
  261. <0xffffffff 0xffffff07>; /* pioC */
  262. /* shared pinctrl settings */
  263. dbgu {
  264. pinctrl_dbgu: dbgu-0 {
  265. atmel,pins =
  266. <AT91_PIOA 9 AT91_PERIPH_A AT91_PINCTRL_NONE>,
  267. <AT91_PIOA 10 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>;
  268. };
  269. };
  270. usart0 {
  271. pinctrl_usart0: usart0-0 {
  272. atmel,pins =
  273. <AT91_PIOC 8 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>,
  274. <AT91_PIOC 9 AT91_PERIPH_A AT91_PINCTRL_NONE>;
  275. };
  276. pinctrl_usart0_rts: usart0_rts-0 {
  277. atmel,pins =
  278. <AT91_PIOC 10 AT91_PERIPH_A AT91_PINCTRL_NONE>;
  279. };
  280. pinctrl_usart0_cts: usart0_cts-0 {
  281. atmel,pins =
  282. <AT91_PIOC 11 AT91_PERIPH_A AT91_PINCTRL_NONE>;
  283. };
  284. };
  285. usart1 {
  286. pinctrl_usart1: usart1-0 {
  287. atmel,pins =
  288. <AT91_PIOC 12 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>,
  289. <AT91_PIOC 13 AT91_PERIPH_A AT91_PINCTRL_NONE>;
  290. };
  291. pinctrl_usart1_rts: usart1_rts-0 {
  292. atmel,pins =
  293. <AT91_PIOA 12 AT91_PERIPH_B AT91_PINCTRL_NONE>;
  294. };
  295. pinctrl_usart1_cts: usart1_cts-0 {
  296. atmel,pins =
  297. <AT91_PIOA 13 AT91_PERIPH_B AT91_PINCTRL_NONE>;
  298. };
  299. };
  300. usart2 {
  301. pinctrl_usart2: usart2-0 {
  302. atmel,pins =
  303. <AT91_PIOC 14 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>,
  304. <AT91_PIOC 15 AT91_PERIPH_A AT91_PINCTRL_NONE>;
  305. };
  306. pinctrl_usart2_rts: usart2_rts-0 {
  307. atmel,pins =
  308. <AT91_PIOA 15 AT91_PERIPH_B AT91_PINCTRL_NONE>;
  309. };
  310. pinctrl_usart2_cts: usart2_cts-0 {
  311. atmel,pins =
  312. <AT91_PIOA 16 AT91_PERIPH_B AT91_PINCTRL_NONE>;
  313. };
  314. };
  315. nand {
  316. pinctrl_nand: nand-0 {
  317. atmel,pins =
  318. <AT91_PIOC 15 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP>,
  319. <AT91_PIOC 14 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP>;
  320. };
  321. };
  322. mmc0 {
  323. pinctrl_mmc0_clk: mmc0_clk-0 {
  324. atmel,pins =
  325. <AT91_PIOA 2 AT91_PERIPH_B AT91_PINCTRL_NONE>;
  326. };
  327. pinctrl_mmc0_slot0_cmd_dat0: mmc0_slot0_cmd_dat0-0 {
  328. atmel,pins =
  329. <AT91_PIOA 1 AT91_PERIPH_B AT91_PINCTRL_PULL_UP>,
  330. <AT91_PIOA 0 AT91_PERIPH_B AT91_PINCTRL_PULL_UP>;
  331. };
  332. pinctrl_mmc0_slot0_dat1_3: mmc0_slot0_dat1_3-0 {
  333. atmel,pins =
  334. <AT91_PIOA 4 AT91_PERIPH_B AT91_PINCTRL_PULL_UP>,
  335. <AT91_PIOA 5 AT91_PERIPH_B AT91_PINCTRL_PULL_UP>,
  336. <AT91_PIOA 6 AT91_PERIPH_B AT91_PINCTRL_PULL_UP>;
  337. };
  338. };
  339. ssc0 {
  340. pinctrl_ssc0_tx: ssc0_tx-0 {
  341. atmel,pins =
  342. <AT91_PIOB 21 AT91_PERIPH_A AT91_PINCTRL_NONE>,
  343. <AT91_PIOB 22 AT91_PERIPH_A AT91_PINCTRL_NONE>,
  344. <AT91_PIOB 23 AT91_PERIPH_A AT91_PINCTRL_NONE>;
  345. };
  346. pinctrl_ssc0_rx: ssc0_rx-0 {
  347. atmel,pins =
  348. <AT91_PIOB 24 AT91_PERIPH_A AT91_PINCTRL_NONE>,
  349. <AT91_PIOB 25 AT91_PERIPH_A AT91_PINCTRL_NONE>,
  350. <AT91_PIOB 26 AT91_PERIPH_A AT91_PINCTRL_NONE>;
  351. };
  352. };
  353. ssc1 {
  354. pinctrl_ssc1_tx: ssc1_tx-0 {
  355. atmel,pins =
  356. <AT91_PIOA 17 AT91_PERIPH_B AT91_PINCTRL_NONE>,
  357. <AT91_PIOA 18 AT91_PERIPH_B AT91_PINCTRL_NONE>,
  358. <AT91_PIOA 19 AT91_PERIPH_B AT91_PINCTRL_NONE>;
  359. };
  360. pinctrl_ssc1_rx: ssc1_rx-0 {
  361. atmel,pins =
  362. <AT91_PIOA 20 AT91_PERIPH_B AT91_PINCTRL_NONE>,
  363. <AT91_PIOA 21 AT91_PERIPH_B AT91_PINCTRL_NONE>,
  364. <AT91_PIOA 22 AT91_PERIPH_B AT91_PINCTRL_NONE>;
  365. };
  366. };
  367. ssc2 {
  368. pinctrl_ssc2_tx: ssc2_tx-0 {
  369. atmel,pins =
  370. <AT91_PIOC 25 AT91_PERIPH_B AT91_PINCTRL_NONE>,
  371. <AT91_PIOC 26 AT91_PERIPH_B AT91_PINCTRL_NONE>,
  372. <AT91_PIOC 27 AT91_PERIPH_B AT91_PINCTRL_NONE>;
  373. };
  374. pinctrl_ssc2_rx: ssc2_rx-0 {
  375. atmel,pins =
  376. <AT91_PIOC 28 AT91_PERIPH_B AT91_PINCTRL_NONE>,
  377. <AT91_PIOC 29 AT91_PERIPH_B AT91_PINCTRL_NONE>,
  378. <AT91_PIOC 30 AT91_PERIPH_B AT91_PINCTRL_NONE>;
  379. };
  380. };
  381. spi0 {
  382. pinctrl_spi0: spi0-0 {
  383. atmel,pins =
  384. <AT91_PIOA 0 AT91_PERIPH_A AT91_PINCTRL_NONE>,
  385. <AT91_PIOA 1 AT91_PERIPH_A AT91_PINCTRL_NONE>,
  386. <AT91_PIOA 2 AT91_PERIPH_A AT91_PINCTRL_NONE>;
  387. };
  388. };
  389. spi1 {
  390. pinctrl_spi1: spi1-0 {
  391. atmel,pins =
  392. <AT91_PIOB 30 AT91_PERIPH_A AT91_PINCTRL_NONE>,
  393. <AT91_PIOB 31 AT91_PERIPH_A AT91_PINCTRL_NONE>,
  394. <AT91_PIOB 29 AT91_PERIPH_A AT91_PINCTRL_NONE>;
  395. };
  396. };
  397. tcb0 {
  398. pinctrl_tcb0_tclk0: tcb0_tclk0-0 {
  399. atmel,pins = <AT91_PIOC 16 AT91_PERIPH_B AT91_PINCTRL_NONE>;
  400. };
  401. pinctrl_tcb0_tclk1: tcb0_tclk1-0 {
  402. atmel,pins = <AT91_PIOC 17 AT91_PERIPH_B AT91_PINCTRL_NONE>;
  403. };
  404. pinctrl_tcb0_tclk2: tcb0_tclk2-0 {
  405. atmel,pins = <AT91_PIOC 18 AT91_PERIPH_B AT91_PINCTRL_NONE>;
  406. };
  407. pinctrl_tcb0_tioa0: tcb0_tioa0-0 {
  408. atmel,pins = <AT91_PIOC 19 AT91_PERIPH_B AT91_PINCTRL_NONE>;
  409. };
  410. pinctrl_tcb0_tioa1: tcb0_tioa1-0 {
  411. atmel,pins = <AT91_PIOC 21 AT91_PERIPH_B AT91_PINCTRL_NONE>;
  412. };
  413. pinctrl_tcb0_tioa2: tcb0_tioa2-0 {
  414. atmel,pins = <AT91_PIOC 23 AT91_PERIPH_B AT91_PINCTRL_NONE>;
  415. };
  416. pinctrl_tcb0_tiob0: tcb0_tiob0-0 {
  417. atmel,pins = <AT91_PIOC 20 AT91_PERIPH_B AT91_PINCTRL_NONE>;
  418. };
  419. pinctrl_tcb0_tiob1: tcb0_tiob1-0 {
  420. atmel,pins = <AT91_PIOC 22 AT91_PERIPH_B AT91_PINCTRL_NONE>;
  421. };
  422. pinctrl_tcb0_tiob2: tcb0_tiob2-0 {
  423. atmel,pins = <AT91_PIOC 24 AT91_PERIPH_B AT91_PINCTRL_NONE>;
  424. };
  425. };
  426. i2c0 {
  427. pinctrl_i2c_bitbang: i2c-0-bitbang {
  428. atmel,pins =
  429. <AT91_PIOA 7 AT91_PERIPH_GPIO AT91_PINCTRL_NONE>,
  430. <AT91_PIOA 8 AT91_PERIPH_GPIO AT91_PINCTRL_NONE>;
  431. };
  432. pinctrl_i2c_twi: i2c-0-twi {
  433. atmel,pins =
  434. <AT91_PIOA 7 AT91_PERIPH_A AT91_PINCTRL_NONE>,
  435. <AT91_PIOA 8 AT91_PERIPH_A AT91_PINCTRL_NONE>;
  436. };
  437. };
  438. fb {
  439. pinctrl_fb: fb-0 {
  440. atmel,pins =
  441. <AT91_PIOB 1 AT91_PERIPH_A AT91_PINCTRL_NONE>,
  442. <AT91_PIOB 2 AT91_PERIPH_A AT91_PINCTRL_NONE>,
  443. <AT91_PIOB 3 AT91_PERIPH_A AT91_PINCTRL_NONE>,
  444. <AT91_PIOB 7 AT91_PERIPH_A AT91_PINCTRL_NONE>,
  445. <AT91_PIOB 8 AT91_PERIPH_A AT91_PINCTRL_NONE>,
  446. <AT91_PIOB 9 AT91_PERIPH_A AT91_PINCTRL_NONE>,
  447. <AT91_PIOB 10 AT91_PERIPH_A AT91_PINCTRL_NONE>,
  448. <AT91_PIOB 11 AT91_PERIPH_A AT91_PINCTRL_NONE>,
  449. <AT91_PIOB 12 AT91_PERIPH_A AT91_PINCTRL_NONE>,
  450. <AT91_PIOB 15 AT91_PERIPH_A AT91_PINCTRL_NONE>,
  451. <AT91_PIOB 16 AT91_PERIPH_A AT91_PINCTRL_NONE>,
  452. <AT91_PIOB 17 AT91_PERIPH_A AT91_PINCTRL_NONE>,
  453. <AT91_PIOB 18 AT91_PERIPH_A AT91_PINCTRL_NONE>,
  454. <AT91_PIOB 19 AT91_PERIPH_A AT91_PINCTRL_NONE>,
  455. <AT91_PIOB 20 AT91_PERIPH_A AT91_PINCTRL_NONE>,
  456. <AT91_PIOB 23 AT91_PERIPH_B AT91_PINCTRL_NONE>,
  457. <AT91_PIOB 24 AT91_PERIPH_B AT91_PINCTRL_NONE>,
  458. <AT91_PIOB 25 AT91_PERIPH_B AT91_PINCTRL_NONE>,
  459. <AT91_PIOB 26 AT91_PERIPH_B AT91_PINCTRL_NONE>,
  460. <AT91_PIOB 27 AT91_PERIPH_B AT91_PINCTRL_NONE>,
  461. <AT91_PIOB 28 AT91_PERIPH_B AT91_PINCTRL_NONE>;
  462. };
  463. };
  464. pioA: gpio@fffff400 {
  465. compatible = "atmel,at91rm9200-gpio";
  466. reg = <0xfffff400 0x200>;
  467. interrupts = <2 IRQ_TYPE_LEVEL_HIGH 1>;
  468. #gpio-cells = <2>;
  469. gpio-controller;
  470. interrupt-controller;
  471. #interrupt-cells = <2>;
  472. clocks = <&pioA_clk>;
  473. };
  474. pioB: gpio@fffff600 {
  475. compatible = "atmel,at91rm9200-gpio";
  476. reg = <0xfffff600 0x200>;
  477. interrupts = <3 IRQ_TYPE_LEVEL_HIGH 1>;
  478. #gpio-cells = <2>;
  479. gpio-controller;
  480. interrupt-controller;
  481. #interrupt-cells = <2>;
  482. clocks = <&pioB_clk>;
  483. };
  484. pioC: gpio@fffff800 {
  485. compatible = "atmel,at91rm9200-gpio";
  486. reg = <0xfffff800 0x200>;
  487. interrupts = <4 IRQ_TYPE_LEVEL_HIGH 1>;
  488. #gpio-cells = <2>;
  489. gpio-controller;
  490. interrupt-controller;
  491. #interrupt-cells = <2>;
  492. clocks = <&pioC_clk>;
  493. };
  494. };
  495. pmc: pmc@fffffc00 {
  496. compatible = "atmel,at91rm9200-pmc";
  497. reg = <0xfffffc00 0x100>;
  498. interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
  499. interrupt-controller;
  500. #address-cells = <1>;
  501. #size-cells = <0>;
  502. #interrupt-cells = <1>;
  503. main_osc: main_osc {
  504. compatible = "atmel,at91rm9200-clk-main-osc";
  505. #clock-cells = <0>;
  506. interrupts-extended = <&pmc AT91_PMC_MOSCS>;
  507. clocks = <&main_xtal>;
  508. };
  509. main: mainck {
  510. compatible = "atmel,at91rm9200-clk-main";
  511. #clock-cells = <0>;
  512. clocks = <&main_osc>;
  513. };
  514. plla: pllack {
  515. compatible = "atmel,at91rm9200-clk-pll";
  516. #clock-cells = <0>;
  517. interrupts-extended = <&pmc AT91_PMC_LOCKA>;
  518. clocks = <&main>;
  519. reg = <0>;
  520. atmel,clk-input-range = <1000000 32000000>;
  521. #atmel,pll-clk-output-range-cells = <4>;
  522. atmel,pll-clk-output-ranges = <80000000 200000000 0 1>,
  523. <190000000 240000000 2 1>;
  524. };
  525. pllb: pllbck {
  526. compatible = "atmel,at91rm9200-clk-pll";
  527. #clock-cells = <0>;
  528. interrupts-extended = <&pmc AT91_PMC_LOCKB>;
  529. clocks = <&main>;
  530. reg = <1>;
  531. atmel,clk-input-range = <1000000 5000000>;
  532. #atmel,pll-clk-output-range-cells = <4>;
  533. atmel,pll-clk-output-ranges = <70000000 130000000 1 1>;
  534. };
  535. mck: masterck {
  536. compatible = "atmel,at91rm9200-clk-master";
  537. #clock-cells = <0>;
  538. interrupts-extended = <&pmc AT91_PMC_MCKRDY>;
  539. clocks = <&slow_xtal>, <&main>, <&plla>, <&pllb>;
  540. atmel,clk-output-range = <0 94000000>;
  541. atmel,clk-divisors = <1 2 4 0>;
  542. };
  543. usb: usbck {
  544. compatible = "atmel,at91rm9200-clk-usb";
  545. #clock-cells = <0>;
  546. atmel,clk-divisors = <1 2 4 0>;
  547. clocks = <&pllb>;
  548. };
  549. prog: progck {
  550. compatible = "atmel,at91rm9200-clk-programmable";
  551. #address-cells = <1>;
  552. #size-cells = <0>;
  553. interrupt-parent = <&pmc>;
  554. clocks = <&slow_xtal>, <&main>, <&plla>, <&pllb>;
  555. prog0: prog0 {
  556. #clock-cells = <0>;
  557. reg = <0>;
  558. interrupts = <AT91_PMC_PCKRDY(0)>;
  559. };
  560. prog1: prog1 {
  561. #clock-cells = <0>;
  562. reg = <1>;
  563. interrupts = <AT91_PMC_PCKRDY(1)>;
  564. };
  565. prog2: prog2 {
  566. #clock-cells = <0>;
  567. reg = <2>;
  568. interrupts = <AT91_PMC_PCKRDY(2)>;
  569. };
  570. prog3: prog3 {
  571. #clock-cells = <0>;
  572. reg = <3>;
  573. interrupts = <AT91_PMC_PCKRDY(3)>;
  574. };
  575. };
  576. systemck {
  577. compatible = "atmel,at91rm9200-clk-system";
  578. #address-cells = <1>;
  579. #size-cells = <0>;
  580. uhpck: uhpck {
  581. #clock-cells = <0>;
  582. reg = <6>;
  583. clocks = <&usb>;
  584. };
  585. udpck: udpck {
  586. #clock-cells = <0>;
  587. reg = <7>;
  588. clocks = <&usb>;
  589. };
  590. pck0: pck0 {
  591. #clock-cells = <0>;
  592. reg = <8>;
  593. clocks = <&prog0>;
  594. };
  595. pck1: pck1 {
  596. #clock-cells = <0>;
  597. reg = <9>;
  598. clocks = <&prog1>;
  599. };
  600. pck2: pck2 {
  601. #clock-cells = <0>;
  602. reg = <10>;
  603. clocks = <&prog2>;
  604. };
  605. pck3: pck3 {
  606. #clock-cells = <0>;
  607. reg = <11>;
  608. clocks = <&prog3>;
  609. };
  610. hclk0: hclk0 {
  611. #clock-cells = <0>;
  612. reg = <16>;
  613. clocks = <&mck>;
  614. };
  615. hclk1: hclk1 {
  616. #clock-cells = <0>;
  617. reg = <17>;
  618. clocks = <&mck>;
  619. };
  620. };
  621. periphck {
  622. compatible = "atmel,at91rm9200-clk-peripheral";
  623. #address-cells = <1>;
  624. #size-cells = <0>;
  625. clocks = <&mck>;
  626. pioA_clk: pioA_clk {
  627. #clock-cells = <0>;
  628. reg = <2>;
  629. };
  630. pioB_clk: pioB_clk {
  631. #clock-cells = <0>;
  632. reg = <3>;
  633. };
  634. pioC_clk: pioC_clk {
  635. #clock-cells = <0>;
  636. reg = <4>;
  637. };
  638. usart0_clk: usart0_clk {
  639. #clock-cells = <0>;
  640. reg = <6>;
  641. };
  642. usart1_clk: usart1_clk {
  643. #clock-cells = <0>;
  644. reg = <7>;
  645. };
  646. usart2_clk: usart2_clk {
  647. #clock-cells = <0>;
  648. reg = <8>;
  649. };
  650. mci0_clk: mci0_clk {
  651. #clock-cells = <0>;
  652. reg = <9>;
  653. };
  654. udc_clk: udc_clk {
  655. #clock-cells = <0>;
  656. reg = <10>;
  657. };
  658. twi0_clk: twi0_clk {
  659. reg = <11>;
  660. #clock-cells = <0>;
  661. };
  662. spi0_clk: spi0_clk {
  663. #clock-cells = <0>;
  664. reg = <12>;
  665. };
  666. spi1_clk: spi1_clk {
  667. #clock-cells = <0>;
  668. reg = <13>;
  669. };
  670. ssc0_clk: ssc0_clk {
  671. #clock-cells = <0>;
  672. reg = <14>;
  673. };
  674. ssc1_clk: ssc1_clk {
  675. #clock-cells = <0>;
  676. reg = <15>;
  677. };
  678. ssc2_clk: ssc2_clk {
  679. #clock-cells = <0>;
  680. reg = <16>;
  681. };
  682. tc0_clk: tc0_clk {
  683. #clock-cells = <0>;
  684. reg = <17>;
  685. };
  686. tc1_clk: tc1_clk {
  687. #clock-cells = <0>;
  688. reg = <18>;
  689. };
  690. tc2_clk: tc2_clk {
  691. #clock-cells = <0>;
  692. reg = <19>;
  693. };
  694. ohci_clk: ohci_clk {
  695. #clock-cells = <0>;
  696. reg = <20>;
  697. };
  698. lcd_clk: lcd_clk {
  699. #clock-cells = <0>;
  700. reg = <21>;
  701. };
  702. };
  703. };
  704. rstc@fffffd00 {
  705. compatible = "atmel,at91sam9260-rstc";
  706. reg = <0xfffffd00 0x10>;
  707. };
  708. shdwc@fffffd10 {
  709. compatible = "atmel,at91sam9260-shdwc";
  710. reg = <0xfffffd10 0x10>;
  711. };
  712. pit: timer@fffffd30 {
  713. compatible = "atmel,at91sam9260-pit";
  714. reg = <0xfffffd30 0xf>;
  715. interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
  716. clocks = <&mck>;
  717. };
  718. watchdog@fffffd40 {
  719. compatible = "atmel,at91sam9260-wdt";
  720. reg = <0xfffffd40 0x10>;
  721. interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
  722. status = "disabled";
  723. };
  724. };
  725. };
  726. i2c@0 {
  727. compatible = "i2c-gpio";
  728. pinctrl-names = "default";
  729. pinctrl-0 = <&pinctrl_i2c_bitbang>;
  730. gpios = <&pioA 7 GPIO_ACTIVE_HIGH>, /* sda */
  731. <&pioA 8 GPIO_ACTIVE_HIGH>; /* scl */
  732. i2c-gpio,sda-open-drain;
  733. i2c-gpio,scl-open-drain;
  734. i2c-gpio,delay-us = <2>; /* ~100 kHz */
  735. #address-cells = <1>;
  736. #size-cells = <0>;
  737. status = "disabled";
  738. };
  739. };