at91sam9g20.dtsi 1.3 KB

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  1. /*
  2. * at91sam9g20.dtsi - Device Tree Include file for AT91SAM9G20 family SoC
  3. *
  4. * Copyright (C) 2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
  5. *
  6. * Licensed under GPLv2.
  7. */
  8. #include "at91sam9260.dtsi"
  9. / {
  10. model = "Atmel AT91SAM9G20 family SoC";
  11. compatible = "atmel,at91sam9g20";
  12. memory {
  13. reg = <0x20000000 0x08000000>;
  14. };
  15. ahb {
  16. apb {
  17. i2c0: i2c@fffac000 {
  18. compatible = "atmel,at91sam9g20-i2c";
  19. };
  20. ssc0: ssc@fffbc000 {
  21. compatible = "atmel,at91sam9rl-ssc";
  22. };
  23. adc0: adc@fffe0000 {
  24. atmel,adc-startup-time = <40>;
  25. };
  26. pmc: pmc@fffffc00 {
  27. plla: pllack {
  28. atmel,clk-input-range = <2000000 32000000>;
  29. atmel,pll-clk-output-ranges = <745000000 800000000 0 0>,
  30. <695000000 750000000 1 0>,
  31. <645000000 700000000 2 0>,
  32. <595000000 650000000 3 0>,
  33. <545000000 600000000 0 1>,
  34. <495000000 550000000 1 1>,
  35. <445000000 500000000 2 1>,
  36. <400000000 450000000 3 1>;
  37. };
  38. pllb: pllbck {
  39. compatible = "atmel,at91sam9g20-clk-pllb";
  40. atmel,clk-input-range = <2000000 32000000>;
  41. atmel,pll-clk-output-ranges = <30000000 100000000 0 0>;
  42. };
  43. mck: masterck {
  44. atmel,clk-output-range = <0 133000000>;
  45. atmel,clk-divisors = <1 2 4 6>;
  46. };
  47. };
  48. };
  49. };
  50. };