bcm11351.dtsi 9.6 KB

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  1. /*
  2. * Copyright (C) 2012-2013 Broadcom Corporation
  3. *
  4. * This program is free software; you can redistribute it and/or
  5. * modify it under the terms of the GNU General Public License as
  6. * published by the Free Software Foundation version 2.
  7. *
  8. * This program is distributed "as is" WITHOUT ANY WARRANTY of any
  9. * kind, whether express or implied; without even the implied warranty
  10. * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  11. * GNU General Public License for more details.
  12. */
  13. #include <dt-bindings/interrupt-controller/arm-gic.h>
  14. #include <dt-bindings/interrupt-controller/irq.h>
  15. #include "dt-bindings/clock/bcm281xx.h"
  16. #include "skeleton.dtsi"
  17. / {
  18. model = "BCM11351 SoC";
  19. compatible = "brcm,bcm11351";
  20. interrupt-parent = <&gic>;
  21. chosen {
  22. bootargs = "console=ttyS0,115200n8";
  23. };
  24. cpus {
  25. #address-cells = <1>;
  26. #size-cells = <0>;
  27. enable-method = "brcm,bcm11351-cpu-method";
  28. secondary-boot-reg = <0x3500417c>;
  29. cpu0: cpu@0 {
  30. device_type = "cpu";
  31. compatible = "arm,cortex-a9";
  32. reg = <0>;
  33. };
  34. cpu1: cpu@1 {
  35. device_type = "cpu";
  36. compatible = "arm,cortex-a9";
  37. reg = <1>;
  38. };
  39. };
  40. gic: interrupt-controller@3ff00100 {
  41. compatible = "arm,cortex-a9-gic";
  42. #interrupt-cells = <3>;
  43. #address-cells = <0>;
  44. interrupt-controller;
  45. reg = <0x3ff01000 0x1000>,
  46. <0x3ff00100 0x100>;
  47. };
  48. smc@0x3404c000 {
  49. compatible = "brcm,bcm11351-smc", "brcm,kona-smc";
  50. reg = <0x3404c000 0x400>; /* 1 KiB in SRAM */
  51. };
  52. uart@3e000000 {
  53. compatible = "brcm,bcm11351-dw-apb-uart", "snps,dw-apb-uart";
  54. status = "disabled";
  55. reg = <0x3e000000 0x1000>;
  56. clocks = <&slave_ccu BCM281XX_SLAVE_CCU_UARTB>;
  57. interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
  58. reg-shift = <2>;
  59. reg-io-width = <4>;
  60. };
  61. uart@3e001000 {
  62. compatible = "brcm,bcm11351-dw-apb-uart", "snps,dw-apb-uart";
  63. status = "disabled";
  64. reg = <0x3e001000 0x1000>;
  65. clocks = <&slave_ccu BCM281XX_SLAVE_CCU_UARTB2>;
  66. interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
  67. reg-shift = <2>;
  68. reg-io-width = <4>;
  69. };
  70. uart@3e002000 {
  71. compatible = "brcm,bcm11351-dw-apb-uart", "snps,dw-apb-uart";
  72. status = "disabled";
  73. reg = <0x3e002000 0x1000>;
  74. clocks = <&slave_ccu BCM281XX_SLAVE_CCU_UARTB3>;
  75. interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
  76. reg-shift = <2>;
  77. reg-io-width = <4>;
  78. };
  79. uart@3e003000 {
  80. compatible = "brcm,bcm11351-dw-apb-uart", "snps,dw-apb-uart";
  81. status = "disabled";
  82. reg = <0x3e003000 0x1000>;
  83. clocks = <&slave_ccu BCM281XX_SLAVE_CCU_UARTB4>;
  84. interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
  85. reg-shift = <2>;
  86. reg-io-width = <4>;
  87. };
  88. L2: l2-cache {
  89. compatible = "brcm,bcm11351-a2-pl310-cache";
  90. reg = <0x3ff20000 0x1000>;
  91. cache-unified;
  92. cache-level = <2>;
  93. };
  94. watchdog@35002f40 {
  95. compatible = "brcm,bcm11351-wdt", "brcm,kona-wdt";
  96. reg = <0x35002f40 0x6c>;
  97. };
  98. timer@35006000 {
  99. compatible = "brcm,kona-timer";
  100. reg = <0x35006000 0x1000>;
  101. interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
  102. clocks = <&aon_ccu BCM281XX_AON_CCU_HUB_TIMER>;
  103. };
  104. gpio: gpio@35003000 {
  105. compatible = "brcm,bcm11351-gpio", "brcm,kona-gpio";
  106. reg = <0x35003000 0x800>;
  107. interrupts =
  108. <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH
  109. GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH
  110. GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH
  111. GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH
  112. GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH
  113. GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
  114. #gpio-cells = <2>;
  115. #interrupt-cells = <2>;
  116. gpio-controller;
  117. interrupt-controller;
  118. };
  119. sdio1: sdio@3f180000 {
  120. compatible = "brcm,kona-sdhci";
  121. reg = <0x3f180000 0x10000>;
  122. interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
  123. clocks = <&master_ccu BCM281XX_MASTER_CCU_SDIO1>;
  124. status = "disabled";
  125. };
  126. sdio2: sdio@3f190000 {
  127. compatible = "brcm,kona-sdhci";
  128. reg = <0x3f190000 0x10000>;
  129. interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
  130. clocks = <&master_ccu BCM281XX_MASTER_CCU_SDIO2>;
  131. status = "disabled";
  132. };
  133. sdio3: sdio@3f1a0000 {
  134. compatible = "brcm,kona-sdhci";
  135. reg = <0x3f1a0000 0x10000>;
  136. interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
  137. clocks = <&master_ccu BCM281XX_MASTER_CCU_SDIO3>;
  138. status = "disabled";
  139. };
  140. sdio4: sdio@3f1b0000 {
  141. compatible = "brcm,kona-sdhci";
  142. reg = <0x3f1b0000 0x10000>;
  143. interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
  144. clocks = <&master_ccu BCM281XX_MASTER_CCU_SDIO4>;
  145. status = "disabled";
  146. };
  147. pinctrl@35004800 {
  148. compatible = "brcm,bcm11351-pinctrl";
  149. reg = <0x35004800 0x430>;
  150. };
  151. i2c@3e016000 {
  152. compatible = "brcm,bcm11351-i2c", "brcm,kona-i2c";
  153. reg = <0x3e016000 0x80>;
  154. interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
  155. #address-cells = <1>;
  156. #size-cells = <0>;
  157. clocks = <&slave_ccu BCM281XX_SLAVE_CCU_BSC1>;
  158. status = "disabled";
  159. };
  160. i2c@3e017000 {
  161. compatible = "brcm,bcm11351-i2c", "brcm,kona-i2c";
  162. reg = <0x3e017000 0x80>;
  163. interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
  164. #address-cells = <1>;
  165. #size-cells = <0>;
  166. clocks = <&slave_ccu BCM281XX_SLAVE_CCU_BSC2>;
  167. status = "disabled";
  168. };
  169. i2c@3e018000 {
  170. compatible = "brcm,bcm11351-i2c", "brcm,kona-i2c";
  171. reg = <0x3e018000 0x80>;
  172. interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
  173. #address-cells = <1>;
  174. #size-cells = <0>;
  175. clocks = <&slave_ccu BCM281XX_SLAVE_CCU_BSC3>;
  176. status = "disabled";
  177. };
  178. i2c@3500d000 {
  179. compatible = "brcm,bcm11351-i2c", "brcm,kona-i2c";
  180. reg = <0x3500d000 0x80>;
  181. interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
  182. #address-cells = <1>;
  183. #size-cells = <0>;
  184. clocks = <&aon_ccu BCM281XX_AON_CCU_PMU_BSC>;
  185. status = "disabled";
  186. };
  187. pwm: pwm@3e01a000 {
  188. compatible = "brcm,bcm11351-pwm", "brcm,kona-pwm";
  189. reg = <0x3e01a000 0xcc>;
  190. clocks = <&slave_ccu BCM281XX_SLAVE_CCU_PWM>;
  191. #pwm-cells = <3>;
  192. status = "disabled";
  193. };
  194. clocks {
  195. #address-cells = <1>;
  196. #size-cells = <1>;
  197. ranges;
  198. root_ccu: root_ccu {
  199. compatible = "brcm,bcm11351-root-ccu";
  200. reg = <0x35001000 0x0f00>;
  201. #clock-cells = <1>;
  202. clock-output-names = "frac_1m";
  203. };
  204. hub_ccu: hub_ccu {
  205. compatible = "brcm,bcm11351-hub-ccu";
  206. reg = <0x34000000 0x0f00>;
  207. #clock-cells = <1>;
  208. clock-output-names = "tmon_1m";
  209. };
  210. aon_ccu: aon_ccu {
  211. compatible = "brcm,bcm11351-aon-ccu";
  212. reg = <0x35002000 0x0f00>;
  213. #clock-cells = <1>;
  214. clock-output-names = "hub_timer",
  215. "pmu_bsc",
  216. "pmu_bsc_var";
  217. };
  218. master_ccu: master_ccu {
  219. compatible = "brcm,bcm11351-master-ccu";
  220. reg = <0x3f001000 0x0f00>;
  221. #clock-cells = <1>;
  222. clock-output-names = "sdio1",
  223. "sdio2",
  224. "sdio3",
  225. "sdio4",
  226. "usb_ic",
  227. "hsic2_48m",
  228. "hsic2_12m";
  229. };
  230. slave_ccu: slave_ccu {
  231. compatible = "brcm,bcm11351-slave-ccu";
  232. reg = <0x3e011000 0x0f00>;
  233. #clock-cells = <1>;
  234. clock-output-names = "uartb",
  235. "uartb2",
  236. "uartb3",
  237. "uartb4",
  238. "ssp0",
  239. "ssp2",
  240. "bsc1",
  241. "bsc2",
  242. "bsc3",
  243. "pwm";
  244. };
  245. ref_1m_clk: ref_1m {
  246. #clock-cells = <0>;
  247. compatible = "fixed-clock";
  248. clock-frequency = <1000000>;
  249. };
  250. ref_32k_clk: ref_32k {
  251. #clock-cells = <0>;
  252. compatible = "fixed-clock";
  253. clock-frequency = <32768>;
  254. };
  255. bbl_32k_clk: bbl_32k {
  256. #clock-cells = <0>;
  257. compatible = "fixed-clock";
  258. clock-frequency = <32768>;
  259. };
  260. ref_13m_clk: ref_13m {
  261. #clock-cells = <0>;
  262. compatible = "fixed-clock";
  263. clock-frequency = <13000000>;
  264. };
  265. var_13m_clk: var_13m {
  266. #clock-cells = <0>;
  267. compatible = "fixed-clock";
  268. clock-frequency = <13000000>;
  269. };
  270. dft_19_5m_clk: dft_19_5m {
  271. #clock-cells = <0>;
  272. compatible = "fixed-clock";
  273. clock-frequency = <19500000>;
  274. };
  275. ref_crystal_clk: ref_crystal {
  276. #clock-cells = <0>;
  277. compatible = "fixed-clock";
  278. clock-frequency = <26000000>;
  279. };
  280. ref_cx40_clk: ref_cx40 {
  281. #clock-cells = <0>;
  282. compatible = "fixed-clock";
  283. clock-frequency = <40000000>;
  284. };
  285. ref_52m_clk: ref_52m {
  286. #clock-cells = <0>;
  287. compatible = "fixed-clock";
  288. clock-frequency = <52000000>;
  289. };
  290. var_52m_clk: var_52m {
  291. #clock-cells = <0>;
  292. compatible = "fixed-clock";
  293. clock-frequency = <52000000>;
  294. };
  295. usb_otg_ahb_clk: usb_otg_ahb {
  296. compatible = "fixed-clock";
  297. clock-frequency = <52000000>;
  298. #clock-cells = <0>;
  299. };
  300. ref_96m_clk: ref_96m {
  301. #clock-cells = <0>;
  302. compatible = "fixed-clock";
  303. clock-frequency = <96000000>;
  304. };
  305. var_96m_clk: var_96m {
  306. #clock-cells = <0>;
  307. compatible = "fixed-clock";
  308. clock-frequency = <96000000>;
  309. };
  310. ref_104m_clk: ref_104m {
  311. #clock-cells = <0>;
  312. compatible = "fixed-clock";
  313. clock-frequency = <104000000>;
  314. };
  315. var_104m_clk: var_104m {
  316. #clock-cells = <0>;
  317. compatible = "fixed-clock";
  318. clock-frequency = <104000000>;
  319. };
  320. ref_156m_clk: ref_156m {
  321. #clock-cells = <0>;
  322. compatible = "fixed-clock";
  323. clock-frequency = <156000000>;
  324. };
  325. var_156m_clk: var_156m {
  326. #clock-cells = <0>;
  327. compatible = "fixed-clock";
  328. clock-frequency = <156000000>;
  329. };
  330. ref_208m_clk: ref_208m {
  331. #clock-cells = <0>;
  332. compatible = "fixed-clock";
  333. clock-frequency = <208000000>;
  334. };
  335. var_208m_clk: var_208m {
  336. #clock-cells = <0>;
  337. compatible = "fixed-clock";
  338. clock-frequency = <208000000>;
  339. };
  340. ref_312m_clk: ref_312m {
  341. #clock-cells = <0>;
  342. compatible = "fixed-clock";
  343. clock-frequency = <312000000>;
  344. };
  345. var_312m_clk: var_312m {
  346. #clock-cells = <0>;
  347. compatible = "fixed-clock";
  348. clock-frequency = <312000000>;
  349. };
  350. };
  351. usbotg: usb@3f120000 {
  352. compatible = "snps,dwc2";
  353. reg = <0x3f120000 0x10000>;
  354. interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
  355. clocks = <&usb_otg_ahb_clk>;
  356. clock-names = "otg";
  357. phys = <&usbphy>;
  358. phy-names = "usb2-phy";
  359. status = "disabled";
  360. };
  361. usbphy: usb-phy@3f130000 {
  362. compatible = "brcm,kona-usb2-phy";
  363. reg = <0x3f130000 0x28>;
  364. #phy-cells = <0>;
  365. status = "disabled";
  366. };
  367. };