bcm21664.dtsi 8.1 KB

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  1. /*
  2. * Copyright (C) 2014 Broadcom Corporation
  3. *
  4. * This program is free software; you can redistribute it and/or
  5. * modify it under the terms of the GNU General Public License as
  6. * published by the Free Software Foundation version 2.
  7. *
  8. * This program is distributed "as is" WITHOUT ANY WARRANTY of any
  9. * kind, whether express or implied; without even the implied warranty
  10. * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  11. * GNU General Public License for more details.
  12. */
  13. #include <dt-bindings/interrupt-controller/arm-gic.h>
  14. #include <dt-bindings/interrupt-controller/irq.h>
  15. #include "dt-bindings/clock/bcm21664.h"
  16. #include "skeleton.dtsi"
  17. / {
  18. model = "BCM21664 SoC";
  19. compatible = "brcm,bcm21664";
  20. interrupt-parent = <&gic>;
  21. chosen {
  22. bootargs = "console=ttyS0,115200n8";
  23. };
  24. cpus {
  25. #address-cells = <1>;
  26. #size-cells = <0>;
  27. enable-method = "brcm,bcm11351-cpu-method";
  28. secondary-boot-reg = <0x35004178>;
  29. cpu0: cpu@0 {
  30. device_type = "cpu";
  31. compatible = "arm,cortex-a9";
  32. reg = <0>;
  33. };
  34. cpu1: cpu@1 {
  35. device_type = "cpu";
  36. compatible = "arm,cortex-a9";
  37. reg = <1>;
  38. };
  39. };
  40. gic: interrupt-controller@3ff00100 {
  41. compatible = "arm,cortex-a9-gic";
  42. #interrupt-cells = <3>;
  43. #address-cells = <0>;
  44. interrupt-controller;
  45. reg = <0x3ff01000 0x1000>,
  46. <0x3ff00100 0x100>;
  47. };
  48. smc@0x3404e000 {
  49. compatible = "brcm,bcm21664-smc", "brcm,kona-smc";
  50. reg = <0x3404e000 0x400>; /* 1 KiB in SRAM */
  51. };
  52. uart@3e000000 {
  53. compatible = "brcm,bcm21664-dw-apb-uart", "snps,dw-apb-uart";
  54. status = "disabled";
  55. reg = <0x3e000000 0x118>;
  56. clocks = <&slave_ccu BCM21664_SLAVE_CCU_UARTB>;
  57. interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
  58. reg-shift = <2>;
  59. reg-io-width = <4>;
  60. };
  61. uart@3e001000 {
  62. compatible = "brcm,bcm21664-dw-apb-uart", "snps,dw-apb-uart";
  63. status = "disabled";
  64. reg = <0x3e001000 0x118>;
  65. clocks = <&slave_ccu BCM21664_SLAVE_CCU_UARTB2>;
  66. interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
  67. reg-shift = <2>;
  68. reg-io-width = <4>;
  69. };
  70. uart@3e002000 {
  71. compatible = "brcm,bcm21664-dw-apb-uart", "snps,dw-apb-uart";
  72. status = "disabled";
  73. reg = <0x3e002000 0x118>;
  74. clocks = <&slave_ccu BCM21664_SLAVE_CCU_UARTB3>;
  75. interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
  76. reg-shift = <2>;
  77. reg-io-width = <4>;
  78. };
  79. L2: l2-cache {
  80. compatible = "arm,pl310-cache";
  81. reg = <0x3ff20000 0x1000>;
  82. cache-unified;
  83. cache-level = <2>;
  84. };
  85. brcm,resetmgr@35001f00 {
  86. compatible = "brcm,bcm21664-resetmgr";
  87. reg = <0x35001f00 0x24>;
  88. };
  89. timer@35006000 {
  90. compatible = "brcm,kona-timer";
  91. reg = <0x35006000 0x1c>;
  92. interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
  93. clocks = <&aon_ccu BCM21664_AON_CCU_HUB_TIMER>;
  94. };
  95. gpio: gpio@35003000 {
  96. compatible = "brcm,bcm21664-gpio", "brcm,kona-gpio";
  97. reg = <0x35003000 0x524>;
  98. interrupts =
  99. <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH
  100. GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH
  101. GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH
  102. GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
  103. #gpio-cells = <2>;
  104. #interrupt-cells = <2>;
  105. gpio-controller;
  106. interrupt-controller;
  107. };
  108. sdio1: sdio@3f180000 {
  109. compatible = "brcm,kona-sdhci";
  110. reg = <0x3f180000 0x801c>;
  111. interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
  112. clocks = <&master_ccu BCM21664_MASTER_CCU_SDIO1>;
  113. status = "disabled";
  114. };
  115. sdio2: sdio@3f190000 {
  116. compatible = "brcm,kona-sdhci";
  117. reg = <0x3f190000 0x801c>;
  118. interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
  119. clocks = <&master_ccu BCM21664_MASTER_CCU_SDIO2>;
  120. status = "disabled";
  121. };
  122. sdio3: sdio@3f1a0000 {
  123. compatible = "brcm,kona-sdhci";
  124. reg = <0x3f1a0000 0x801c>;
  125. interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
  126. clocks = <&master_ccu BCM21664_MASTER_CCU_SDIO3>;
  127. status = "disabled";
  128. };
  129. sdio4: sdio@3f1b0000 {
  130. compatible = "brcm,kona-sdhci";
  131. reg = <0x3f1b0000 0x801c>;
  132. interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
  133. clocks = <&master_ccu BCM21664_MASTER_CCU_SDIO4>;
  134. status = "disabled";
  135. };
  136. i2c@3e016000 {
  137. compatible = "brcm,bcm21664-i2c", "brcm,kona-i2c";
  138. reg = <0x3e016000 0x70>;
  139. interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
  140. #address-cells = <1>;
  141. #size-cells = <0>;
  142. clocks = <&slave_ccu BCM21664_SLAVE_CCU_BSC1>;
  143. status = "disabled";
  144. };
  145. i2c@3e017000 {
  146. compatible = "brcm,bcm21664-i2c", "brcm,kona-i2c";
  147. reg = <0x3e017000 0x70>;
  148. interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
  149. #address-cells = <1>;
  150. #size-cells = <0>;
  151. clocks = <&slave_ccu BCM21664_SLAVE_CCU_BSC2>;
  152. status = "disabled";
  153. };
  154. i2c@3e018000 {
  155. compatible = "brcm,bcm21664-i2c", "brcm,kona-i2c";
  156. reg = <0x3e018000 0x70>;
  157. interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
  158. #address-cells = <1>;
  159. #size-cells = <0>;
  160. clocks = <&slave_ccu BCM21664_SLAVE_CCU_BSC3>;
  161. status = "disabled";
  162. };
  163. i2c@3e01c000 {
  164. compatible = "brcm,bcm21664-i2c", "brcm,kona-i2c";
  165. reg = <0x3e01c000 0x70>;
  166. interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>;
  167. #address-cells = <1>;
  168. #size-cells = <0>;
  169. clocks = <&slave_ccu BCM21664_SLAVE_CCU_BSC4>;
  170. status = "disabled";
  171. };
  172. clocks {
  173. #address-cells = <1>;
  174. #size-cells = <1>;
  175. ranges;
  176. /*
  177. * Fixed clocks are defined before CCUs whose
  178. * clocks may depend on them.
  179. */
  180. ref_32k_clk: ref_32k {
  181. #clock-cells = <0>;
  182. compatible = "fixed-clock";
  183. clock-frequency = <32768>;
  184. };
  185. bbl_32k_clk: bbl_32k {
  186. #clock-cells = <0>;
  187. compatible = "fixed-clock";
  188. clock-frequency = <32768>;
  189. };
  190. ref_13m_clk: ref_13m {
  191. #clock-cells = <0>;
  192. compatible = "fixed-clock";
  193. clock-frequency = <13000000>;
  194. };
  195. var_13m_clk: var_13m {
  196. #clock-cells = <0>;
  197. compatible = "fixed-clock";
  198. clock-frequency = <13000000>;
  199. };
  200. dft_19_5m_clk: dft_19_5m {
  201. #clock-cells = <0>;
  202. compatible = "fixed-clock";
  203. clock-frequency = <19500000>;
  204. };
  205. ref_crystal_clk: ref_crystal {
  206. #clock-cells = <0>;
  207. compatible = "fixed-clock";
  208. clock-frequency = <26000000>;
  209. };
  210. ref_52m_clk: ref_52m {
  211. #clock-cells = <0>;
  212. compatible = "fixed-clock";
  213. clock-frequency = <52000000>;
  214. };
  215. var_52m_clk: var_52m {
  216. #clock-cells = <0>;
  217. compatible = "fixed-clock";
  218. clock-frequency = <52000000>;
  219. };
  220. usb_otg_ahb_clk: usb_otg_ahb {
  221. #clock-cells = <0>;
  222. compatible = "fixed-clock";
  223. clock-frequency = <52000000>;
  224. };
  225. ref_96m_clk: ref_96m {
  226. #clock-cells = <0>;
  227. compatible = "fixed-clock";
  228. clock-frequency = <96000000>;
  229. };
  230. var_96m_clk: var_96m {
  231. #clock-cells = <0>;
  232. compatible = "fixed-clock";
  233. clock-frequency = <96000000>;
  234. };
  235. ref_104m_clk: ref_104m {
  236. #clock-cells = <0>;
  237. compatible = "fixed-clock";
  238. clock-frequency = <104000000>;
  239. };
  240. var_104m_clk: var_104m {
  241. #clock-cells = <0>;
  242. compatible = "fixed-clock";
  243. clock-frequency = <104000000>;
  244. };
  245. ref_156m_clk: ref_156m {
  246. #clock-cells = <0>;
  247. compatible = "fixed-clock";
  248. clock-frequency = <156000000>;
  249. };
  250. var_156m_clk: var_156m {
  251. #clock-cells = <0>;
  252. compatible = "fixed-clock";
  253. clock-frequency = <156000000>;
  254. };
  255. root_ccu: root_ccu {
  256. compatible = BCM21664_DT_ROOT_CCU_COMPAT;
  257. reg = <0x35001000 0x0f00>;
  258. #clock-cells = <1>;
  259. clock-output-names = "frac_1m";
  260. };
  261. aon_ccu: aon_ccu {
  262. compatible = BCM21664_DT_AON_CCU_COMPAT;
  263. reg = <0x35002000 0x0f00>;
  264. #clock-cells = <1>;
  265. clock-output-names = "hub_timer";
  266. };
  267. master_ccu: master_ccu {
  268. compatible = BCM21664_DT_MASTER_CCU_COMPAT;
  269. reg = <0x3f001000 0x0f00>;
  270. #clock-cells = <1>;
  271. clock-output-names = "sdio1",
  272. "sdio2",
  273. "sdio3",
  274. "sdio4",
  275. "sdio1_sleep",
  276. "sdio2_sleep",
  277. "sdio3_sleep",
  278. "sdio4_sleep";
  279. };
  280. slave_ccu: slave_ccu {
  281. compatible = BCM21664_DT_SLAVE_CCU_COMPAT;
  282. reg = <0x3e011000 0x0f00>;
  283. #clock-cells = <1>;
  284. clock-output-names = "uartb",
  285. "uartb2",
  286. "uartb3",
  287. "bsc1",
  288. "bsc2",
  289. "bsc3",
  290. "bsc4";
  291. };
  292. };
  293. usbotg: usb@3f120000 {
  294. compatible = "snps,dwc2";
  295. reg = <0x3f120000 0x10000>;
  296. interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
  297. clocks = <&usb_otg_ahb_clk>;
  298. clock-names = "otg";
  299. phys = <&usbphy>;
  300. phy-names = "usb2-phy";
  301. status = "disabled";
  302. };
  303. usbphy: usb-phy@3f130000 {
  304. compatible = "brcm,kona-usb2-phy";
  305. reg = <0x3f130000 0x28>;
  306. #phy-cells = <0>;
  307. status = "disabled";
  308. };
  309. };