imx51-apf51.dts 2.1 KB

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  1. /*
  2. * Copyright 2012 Armadeus Systems - <support@armadeus.com>
  3. * Copyright 2012 Laurent Cans <laurent.cans@gmail.com>
  4. *
  5. * Based on mx51-babbage.dts
  6. * Copyright 2011 Freescale Semiconductor, Inc.
  7. * Copyright 2011 Linaro Ltd.
  8. *
  9. * The code contained herein is licensed under the GNU General Public
  10. * License. You may obtain a copy of the GNU General Public License
  11. * Version 2 or later at the following locations:
  12. *
  13. * http://www.opensource.org/licenses/gpl-license.html
  14. * http://www.gnu.org/copyleft/gpl.html
  15. */
  16. /dts-v1/;
  17. #include "imx51.dtsi"
  18. / {
  19. model = "Armadeus Systems APF51 module";
  20. compatible = "armadeus,imx51-apf51", "fsl,imx51";
  21. memory {
  22. reg = <0x90000000 0x20000000>;
  23. };
  24. clocks {
  25. osc {
  26. clock-frequency = <33554432>;
  27. };
  28. };
  29. };
  30. &fec {
  31. pinctrl-names = "default";
  32. pinctrl-0 = <&pinctrl_fec>;
  33. phy-mode = "mii";
  34. phy-reset-gpios = <&gpio3 0 GPIO_ACTIVE_HIGH>;
  35. phy-reset-duration = <1>;
  36. status = "okay";
  37. };
  38. &iomuxc {
  39. imx51-apf51 {
  40. pinctrl_fec: fecgrp {
  41. fsl,pins = <
  42. MX51_PAD_DI_GP3__FEC_TX_ER 0x80000000
  43. MX51_PAD_DI2_PIN4__FEC_CRS 0x80000000
  44. MX51_PAD_DI2_PIN2__FEC_MDC 0x80000000
  45. MX51_PAD_DI2_PIN3__FEC_MDIO 0x80000000
  46. MX51_PAD_DI2_DISP_CLK__FEC_RDATA1 0x80000000
  47. MX51_PAD_DI_GP4__FEC_RDATA2 0x80000000
  48. MX51_PAD_DISP2_DAT0__FEC_RDATA3 0x80000000
  49. MX51_PAD_DISP2_DAT1__FEC_RX_ER 0x80000000
  50. MX51_PAD_DISP2_DAT6__FEC_TDATA1 0x80000000
  51. MX51_PAD_DISP2_DAT7__FEC_TDATA2 0x80000000
  52. MX51_PAD_DISP2_DAT8__FEC_TDATA3 0x80000000
  53. MX51_PAD_DISP2_DAT9__FEC_TX_EN 0x80000000
  54. MX51_PAD_DISP2_DAT10__FEC_COL 0x80000000
  55. MX51_PAD_DISP2_DAT11__FEC_RX_CLK 0x80000000
  56. MX51_PAD_DISP2_DAT12__FEC_RX_DV 0x80000000
  57. MX51_PAD_DISP2_DAT13__FEC_TX_CLK 0x80000000
  58. MX51_PAD_DISP2_DAT14__FEC_RDATA0 0x80000000
  59. MX51_PAD_DISP2_DAT15__FEC_TDATA0 0x80000000
  60. >;
  61. };
  62. pinctrl_uart3: uart3grp {
  63. fsl,pins = <
  64. MX51_PAD_UART3_RXD__UART3_RXD 0x1c5
  65. MX51_PAD_UART3_TXD__UART3_TXD 0x1c5
  66. >;
  67. };
  68. };
  69. };
  70. &nfc {
  71. nand-bus-width = <8>;
  72. nand-ecc-mode = "hw";
  73. nand-on-flash-bbt;
  74. status = "okay";
  75. };
  76. &uart3 {
  77. pinctrl-names = "default";
  78. pinctrl-0 = <&pinctrl_uart3>;
  79. status = "okay";
  80. };