imx6q-arm2.dts 5.6 KB

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  1. /*
  2. * Copyright 2011 Freescale Semiconductor, Inc.
  3. * Copyright 2011 Linaro Ltd.
  4. *
  5. * The code contained herein is licensed under the GNU General Public
  6. * License. You may obtain a copy of the GNU General Public License
  7. * Version 2 or later at the following locations:
  8. *
  9. * http://www.opensource.org/licenses/gpl-license.html
  10. * http://www.gnu.org/copyleft/gpl.html
  11. */
  12. /dts-v1/;
  13. #include "imx6q.dtsi"
  14. / {
  15. model = "Freescale i.MX6 Quad Armadillo2 Board";
  16. compatible = "fsl,imx6q-arm2", "fsl,imx6q";
  17. memory {
  18. reg = <0x10000000 0x80000000>;
  19. };
  20. regulators {
  21. compatible = "simple-bus";
  22. #address-cells = <1>;
  23. #size-cells = <0>;
  24. reg_3p3v: regulator@0 {
  25. compatible = "regulator-fixed";
  26. reg = <0>;
  27. regulator-name = "3P3V";
  28. regulator-min-microvolt = <3300000>;
  29. regulator-max-microvolt = <3300000>;
  30. regulator-always-on;
  31. };
  32. reg_usb_otg_vbus: regulator@1 {
  33. compatible = "regulator-fixed";
  34. reg = <1>;
  35. regulator-name = "usb_otg_vbus";
  36. regulator-min-microvolt = <5000000>;
  37. regulator-max-microvolt = <5000000>;
  38. gpio = <&gpio3 22 0>;
  39. enable-active-high;
  40. };
  41. };
  42. leds {
  43. compatible = "gpio-leds";
  44. debug-led {
  45. label = "Heartbeat";
  46. gpios = <&gpio3 25 0>;
  47. linux,default-trigger = "heartbeat";
  48. };
  49. };
  50. };
  51. &gpmi {
  52. pinctrl-names = "default";
  53. pinctrl-0 = <&pinctrl_gpmi_nand>;
  54. status = "disabled"; /* gpmi nand conflicts with SD */
  55. };
  56. &iomuxc {
  57. pinctrl-names = "default";
  58. pinctrl-0 = <&pinctrl_hog>;
  59. imx6q-arm2 {
  60. pinctrl_hog: hoggrp {
  61. fsl,pins = <
  62. MX6QDL_PAD_EIM_D25__GPIO3_IO25 0x80000000
  63. >;
  64. };
  65. pinctrl_enet: enetgrp {
  66. fsl,pins = <
  67. MX6QDL_PAD_KEY_COL1__ENET_MDIO 0x1b0b0
  68. MX6QDL_PAD_KEY_COL2__ENET_MDC 0x1b0b0
  69. MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0
  70. MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0
  71. MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0
  72. MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0
  73. MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0
  74. MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0
  75. MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
  76. MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0
  77. MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0
  78. MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0
  79. MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0
  80. MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0
  81. MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0
  82. MX6QDL_PAD_GPIO_6__ENET_IRQ 0x000b1
  83. >;
  84. };
  85. pinctrl_gpmi_nand: gpminandgrp {
  86. fsl,pins = <
  87. MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1
  88. MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1
  89. MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1
  90. MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000
  91. MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1
  92. MX6QDL_PAD_NANDF_CS1__NAND_CE1_B 0xb0b1
  93. MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1
  94. MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1
  95. MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1
  96. MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1
  97. MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1
  98. MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1
  99. MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1
  100. MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1
  101. MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1
  102. MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1
  103. MX6QDL_PAD_SD4_DAT0__NAND_DQS 0x00b1
  104. >;
  105. };
  106. pinctrl_uart2: uart2grp {
  107. fsl,pins = <
  108. MX6QDL_PAD_EIM_D26__UART2_RX_DATA 0x1b0b1
  109. MX6QDL_PAD_EIM_D27__UART2_TX_DATA 0x1b0b1
  110. MX6QDL_PAD_EIM_D28__UART2_DTE_CTS_B 0x1b0b1
  111. MX6QDL_PAD_EIM_D29__UART2_DTE_RTS_B 0x1b0b1
  112. >;
  113. };
  114. pinctrl_uart4: uart4grp {
  115. fsl,pins = <
  116. MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1
  117. MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1
  118. >;
  119. };
  120. pinctrl_usbotg: usbotggrp {
  121. fsl,pins = <
  122. MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059
  123. >;
  124. };
  125. pinctrl_usdhc3: usdhc3grp {
  126. fsl,pins = <
  127. MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059
  128. MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059
  129. MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
  130. MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
  131. MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
  132. MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
  133. MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17059
  134. MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17059
  135. MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17059
  136. MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17059
  137. >;
  138. };
  139. pinctrl_usdhc3_cdwp: usdhc3cdwp {
  140. fsl,pins = <
  141. MX6QDL_PAD_NANDF_CS0__GPIO6_IO11 0x80000000
  142. MX6QDL_PAD_NANDF_CS1__GPIO6_IO14 0x80000000
  143. >;
  144. };
  145. pinctrl_usdhc4: usdhc4grp {
  146. fsl,pins = <
  147. MX6QDL_PAD_SD4_CMD__SD4_CMD 0x17059
  148. MX6QDL_PAD_SD4_CLK__SD4_CLK 0x10059
  149. MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17059
  150. MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17059
  151. MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17059
  152. MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17059
  153. MX6QDL_PAD_SD4_DAT4__SD4_DATA4 0x17059
  154. MX6QDL_PAD_SD4_DAT5__SD4_DATA5 0x17059
  155. MX6QDL_PAD_SD4_DAT6__SD4_DATA6 0x17059
  156. MX6QDL_PAD_SD4_DAT7__SD4_DATA7 0x17059
  157. >;
  158. };
  159. };
  160. };
  161. &fec {
  162. pinctrl-names = "default";
  163. pinctrl-0 = <&pinctrl_enet>;
  164. phy-mode = "rgmii";
  165. interrupts-extended = <&gpio1 6 IRQ_TYPE_LEVEL_HIGH>,
  166. <&intc 0 119 IRQ_TYPE_LEVEL_HIGH>;
  167. status = "okay";
  168. };
  169. &usbotg {
  170. vbus-supply = <&reg_usb_otg_vbus>;
  171. pinctrl-names = "default";
  172. pinctrl-0 = <&pinctrl_usbotg>;
  173. disable-over-current;
  174. status = "okay";
  175. };
  176. &usdhc3 {
  177. cd-gpios = <&gpio6 11 0>;
  178. wp-gpios = <&gpio6 14 0>;
  179. vmmc-supply = <&reg_3p3v>;
  180. pinctrl-names = "default";
  181. pinctrl-0 = <&pinctrl_usdhc3
  182. &pinctrl_usdhc3_cdwp>;
  183. status = "okay";
  184. };
  185. &usdhc4 {
  186. non-removable;
  187. vmmc-supply = <&reg_3p3v>;
  188. pinctrl-names = "default";
  189. pinctrl-0 = <&pinctrl_usdhc4>;
  190. status = "okay";
  191. };
  192. &uart2 {
  193. pinctrl-names = "default";
  194. pinctrl-0 = <&pinctrl_uart2>;
  195. fsl,dte-mode;
  196. fsl,uart-has-rtscts;
  197. status = "okay";
  198. };
  199. &uart4 {
  200. pinctrl-names = "default";
  201. pinctrl-0 = <&pinctrl_uart4>;
  202. status = "okay";
  203. };