imx6qdl-rex.dtsi 7.7 KB

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  1. /*
  2. * Copyright 2014 FEDEVEL, Inc.
  3. *
  4. * Author: Robert Nelson <robertcnelson@gmail.com>
  5. *
  6. * This program is free software; you can redistribute it and/or modify
  7. * it under the terms of the GNU General Public License version 2 as
  8. * published by the Free Software Foundation.
  9. *
  10. */
  11. #include <dt-bindings/gpio/gpio.h>
  12. #include <dt-bindings/input/input.h>
  13. / {
  14. chosen {
  15. stdout-path = &uart1;
  16. };
  17. regulators {
  18. compatible = "simple-bus";
  19. #address-cells = <1>;
  20. #size-cells = <0>;
  21. reg_3p3v: regulator@0 {
  22. compatible = "regulator-fixed";
  23. reg = <0>;
  24. regulator-name = "3P3V";
  25. regulator-min-microvolt = <3300000>;
  26. regulator-max-microvolt = <3300000>;
  27. regulator-always-on;
  28. };
  29. reg_usbh1_vbus: regulator@1 {
  30. compatible = "regulator-fixed";
  31. reg = <1>;
  32. pinctrl-names = "default";
  33. pinctrl-0 = <&pinctrl_usbh1>;
  34. regulator-name = "usbh1_vbus";
  35. regulator-min-microvolt = <5000000>;
  36. regulator-max-microvolt = <5000000>;
  37. gpio = <&gpio3 31 GPIO_ACTIVE_HIGH>;
  38. enable-active-high;
  39. };
  40. reg_usb_otg_vbus: regulator@2 {
  41. compatible = "regulator-fixed";
  42. reg = <2>;
  43. pinctrl-names = "default";
  44. pinctrl-0 = <&pinctrl_usbotg>;
  45. regulator-name = "usb_otg_vbus";
  46. regulator-min-microvolt = <5000000>;
  47. regulator-max-microvolt = <5000000>;
  48. gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>;
  49. enable-active-high;
  50. };
  51. };
  52. leds {
  53. compatible = "gpio-leds";
  54. pinctrl-names = "default";
  55. pinctrl-0 = <&pinctrl_led>;
  56. led0: usr {
  57. label = "usr";
  58. gpios = <&gpio1 2 GPIO_ACTIVE_LOW>;
  59. default-state = "off";
  60. linux,default-trigger = "heartbeat";
  61. };
  62. };
  63. sound {
  64. compatible = "fsl,imx6-rex-sgtl5000",
  65. "fsl,imx-audio-sgtl5000";
  66. model = "imx6-rex-sgtl5000";
  67. ssi-controller = <&ssi1>;
  68. audio-codec = <&codec>;
  69. audio-routing =
  70. "MIC_IN", "Mic Jack",
  71. "Mic Jack", "Mic Bias",
  72. "Headphone Jack", "HP_OUT";
  73. mux-int-port = <1>;
  74. mux-ext-port = <3>;
  75. };
  76. };
  77. &audmux {
  78. pinctrl-names = "default";
  79. pinctrl-0 = <&pinctrl_audmux>;
  80. status = "okay";
  81. };
  82. &ecspi2 {
  83. fsl,spi-num-chipselects = <1>;
  84. cs-gpios = <&gpio5 12 GPIO_ACTIVE_LOW>;
  85. pinctrl-names = "default";
  86. pinctrl-0 = <&pinctrl_ecspi2>;
  87. status = "okay";
  88. };
  89. &ecspi3 {
  90. fsl,spi-num-chipselects = <1>;
  91. cs-gpios = <&gpio4 26 GPIO_ACTIVE_LOW>;
  92. pinctrl-names = "default";
  93. pinctrl-0 = <&pinctrl_ecspi3>;
  94. status = "okay";
  95. };
  96. &fec {
  97. pinctrl-names = "default";
  98. pinctrl-0 = <&pinctrl_enet>;
  99. phy-mode = "rgmii";
  100. phy-reset-gpios = <&gpio1 25 GPIO_ACTIVE_LOW>;
  101. status = "okay";
  102. };
  103. &hdmi {
  104. ddc-i2c-bus = <&i2c2>;
  105. status = "okay";
  106. };
  107. &i2c1 {
  108. clock-frequency = <100000>;
  109. pinctrl-names = "default";
  110. pinctrl-0 = <&pinctrl_i2c1>;
  111. status = "okay";
  112. codec: sgtl5000@0a {
  113. compatible = "fsl,sgtl5000";
  114. reg = <0x0a>;
  115. clocks = <&clks 201>;
  116. VDDA-supply = <&reg_3p3v>;
  117. VDDIO-supply = <&reg_3p3v>;
  118. };
  119. };
  120. &i2c2 {
  121. clock-frequency = <100000>;
  122. pinctrl-names = "default";
  123. pinctrl-0 = <&pinctrl_i2c2>;
  124. status = "okay";
  125. eeprom@57 {
  126. compatible = "at,24c02";
  127. reg = <0x57>;
  128. };
  129. };
  130. &i2c3 {
  131. clock-frequency = <100000>;
  132. pinctrl-names = "default";
  133. pinctrl-0 = <&pinctrl_i2c3>;
  134. status = "okay";
  135. };
  136. &iomuxc {
  137. pinctrl-names = "default";
  138. pinctrl-0 = <&pinctrl_hog>;
  139. imx6qdl-rex {
  140. pinctrl_hog: hoggrp {
  141. fsl,pins = <
  142. /* SGTL5000 sys_mclk */
  143. MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x030b0
  144. >;
  145. };
  146. pinctrl_audmux: audmuxgrp {
  147. fsl,pins = <
  148. MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x130b0
  149. MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x130b0
  150. MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x110b0
  151. MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x130b0
  152. >;
  153. };
  154. pinctrl_ecspi2: ecspi2grp {
  155. fsl,pins = <
  156. MX6QDL_PAD_DISP0_DAT2__ECSPI3_MISO 0x100b1
  157. MX6QDL_PAD_DISP0_DAT1__ECSPI3_MOSI 0x100b1
  158. MX6QDL_PAD_DISP0_DAT0__ECSPI3_SCLK 0x100b1
  159. /* CS */
  160. MX6QDL_PAD_DISP0_DAT5__GPIO4_IO26 0x000b1
  161. >;
  162. };
  163. pinctrl_ecspi3: ecspi3grp {
  164. fsl,pins = <
  165. MX6QDL_PAD_DISP0_DAT17__ECSPI2_MISO 0x100b1
  166. MX6QDL_PAD_DISP0_DAT16__ECSPI2_MOSI 0x100b1
  167. MX6QDL_PAD_DISP0_DAT19__ECSPI2_SCLK 0x100b1
  168. /* CS */
  169. MX6QDL_PAD_DISP0_DAT18__GPIO5_IO12 0x000b1
  170. >;
  171. };
  172. pinctrl_enet: enetgrp {
  173. fsl,pins = <
  174. MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
  175. MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
  176. MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0
  177. MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0
  178. MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0
  179. MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0
  180. MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0
  181. MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0
  182. MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
  183. MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0
  184. MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0
  185. MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0
  186. MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0
  187. MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0
  188. MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0
  189. MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8
  190. /* Phy reset */
  191. MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0x000b0
  192. >;
  193. };
  194. pinctrl_i2c1: i2c1grp {
  195. fsl,pins = <
  196. MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x4001b8b1
  197. MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x4001b8b1
  198. >;
  199. };
  200. pinctrl_i2c2: i2c2grp {
  201. fsl,pins = <
  202. MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1
  203. MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
  204. >;
  205. };
  206. pinctrl_i2c3: i2c3grp {
  207. fsl,pins = <
  208. MX6QDL_PAD_EIM_D17__I2C3_SCL 0x4001b8b1
  209. MX6QDL_PAD_EIM_D18__I2C3_SDA 0x4001b8b1
  210. >;
  211. };
  212. pinctrl_led: ledgrp {
  213. fsl,pins = <
  214. /* user led */
  215. MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x80000000
  216. >;
  217. };
  218. pinctrl_uart1: uart1grp {
  219. fsl,pins = <
  220. MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1
  221. MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1
  222. >;
  223. };
  224. pinctrl_uart2: uart2grp {
  225. fsl,pins = <
  226. MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1
  227. MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1
  228. >;
  229. };
  230. pinctrl_usbh1: usbh1grp {
  231. fsl,pins = <
  232. /* power enable, high active */
  233. MX6QDL_PAD_EIM_D31__GPIO3_IO31 0x10b0
  234. >;
  235. };
  236. pinctrl_usbotg: usbotggrp {
  237. fsl,pins = <
  238. MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059
  239. MX6QDL_PAD_EIM_D21__USB_OTG_OC 0x1b0b0
  240. /* power enable, high active */
  241. MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x10b0
  242. >;
  243. };
  244. pinctrl_usdhc2: usdhc2grp {
  245. fsl,pins = <
  246. MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059
  247. MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059
  248. MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059
  249. MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059
  250. MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059
  251. MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059
  252. /* CD */
  253. MX6QDL_PAD_NANDF_D2__GPIO2_IO02 0x1b0b0
  254. /* WP */
  255. MX6QDL_PAD_NANDF_D3__GPIO2_IO03 0x1f0b0
  256. >;
  257. };
  258. pinctrl_usdhc3: usdhc3grp {
  259. fsl,pins = <
  260. MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059
  261. MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059
  262. MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
  263. MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
  264. MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
  265. MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
  266. /* CD */
  267. MX6QDL_PAD_NANDF_D0__GPIO2_IO00 0x1b0b0
  268. /* WP */
  269. MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x1f0b0
  270. >;
  271. };
  272. };
  273. };
  274. &ssi1 {
  275. fsl,mode = "i2s-slave";
  276. status = "okay";
  277. };
  278. &uart1 {
  279. pinctrl-names = "default";
  280. pinctrl-0 = <&pinctrl_uart1>;
  281. status = "okay";
  282. };
  283. &uart2 {
  284. pinctrl-names = "default";
  285. pinctrl-0 = <&pinctrl_uart2>;
  286. status = "okay";
  287. };
  288. &usbh1 {
  289. vbus-supply = <&reg_usbh1_vbus>;
  290. pinctrl-names = "default";
  291. pinctrl-0 = <&pinctrl_usbh1>;
  292. status = "okay";
  293. };
  294. &usbotg {
  295. vbus-supply = <&reg_usb_otg_vbus>;
  296. pinctrl-names = "default";
  297. pinctrl-0 = <&pinctrl_usbotg>;
  298. status = "okay";
  299. };
  300. &usdhc2 {
  301. pinctrl-names = "default";
  302. pinctrl-0 = <&pinctrl_usdhc2>;
  303. bus-width = <4>;
  304. cd-gpios = <&gpio2 2 GPIO_ACTIVE_LOW>;
  305. wp-gpios = <&gpio2 3 GPIO_ACTIVE_LOW>;
  306. status = "okay";
  307. };
  308. &usdhc3 {
  309. pinctrl-names = "default";
  310. pinctrl-0 = <&pinctrl_usdhc3>;
  311. bus-width = <4>;
  312. cd-gpios = <&gpio2 0 GPIO_ACTIVE_LOW>;
  313. wp-gpios = <&gpio2 1 GPIO_ACTIVE_LOW>;
  314. status = "okay";
  315. };