imx6qdl-sabresd.dtsi 12 KB

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  1. /*
  2. * Copyright 2012 Freescale Semiconductor, Inc.
  3. * Copyright 2011 Linaro Ltd.
  4. *
  5. * The code contained herein is licensed under the GNU General Public
  6. * License. You may obtain a copy of the GNU General Public License
  7. * Version 2 or later at the following locations:
  8. *
  9. * http://www.opensource.org/licenses/gpl-license.html
  10. * http://www.gnu.org/copyleft/gpl.html
  11. */
  12. #include <dt-bindings/gpio/gpio.h>
  13. #include <dt-bindings/input/input.h>
  14. / {
  15. chosen {
  16. stdout-path = &uart1;
  17. };
  18. memory {
  19. reg = <0x10000000 0x40000000>;
  20. };
  21. regulators {
  22. compatible = "simple-bus";
  23. #address-cells = <1>;
  24. #size-cells = <0>;
  25. reg_usb_otg_vbus: regulator@0 {
  26. compatible = "regulator-fixed";
  27. reg = <0>;
  28. regulator-name = "usb_otg_vbus";
  29. regulator-min-microvolt = <5000000>;
  30. regulator-max-microvolt = <5000000>;
  31. gpio = <&gpio3 22 0>;
  32. enable-active-high;
  33. vin-supply = <&swbst_reg>;
  34. };
  35. reg_usb_h1_vbus: regulator@1 {
  36. compatible = "regulator-fixed";
  37. reg = <1>;
  38. regulator-name = "usb_h1_vbus";
  39. regulator-min-microvolt = <5000000>;
  40. regulator-max-microvolt = <5000000>;
  41. gpio = <&gpio1 29 0>;
  42. enable-active-high;
  43. vin-supply = <&swbst_reg>;
  44. };
  45. reg_audio: regulator@2 {
  46. compatible = "regulator-fixed";
  47. reg = <2>;
  48. regulator-name = "wm8962-supply";
  49. gpio = <&gpio4 10 0>;
  50. enable-active-high;
  51. };
  52. reg_pcie: regulator@3 {
  53. compatible = "regulator-fixed";
  54. reg = <3>;
  55. pinctrl-names = "default";
  56. pinctrl-0 = <&pinctrl_pcie_reg>;
  57. regulator-name = "MPCIE_3V3";
  58. regulator-min-microvolt = <3300000>;
  59. regulator-max-microvolt = <3300000>;
  60. gpio = <&gpio3 19 0>;
  61. regulator-always-on;
  62. enable-active-high;
  63. };
  64. };
  65. gpio-keys {
  66. compatible = "gpio-keys";
  67. pinctrl-names = "default";
  68. pinctrl-0 = <&pinctrl_gpio_keys>;
  69. power {
  70. label = "Power Button";
  71. gpios = <&gpio3 29 GPIO_ACTIVE_LOW>;
  72. gpio-key,wakeup;
  73. linux,code = <KEY_POWER>;
  74. };
  75. volume-up {
  76. label = "Volume Up";
  77. gpios = <&gpio1 4 GPIO_ACTIVE_LOW>;
  78. gpio-key,wakeup;
  79. linux,code = <KEY_VOLUMEUP>;
  80. };
  81. volume-down {
  82. label = "Volume Down";
  83. gpios = <&gpio1 5 GPIO_ACTIVE_LOW>;
  84. gpio-key,wakeup;
  85. linux,code = <KEY_VOLUMEDOWN>;
  86. };
  87. };
  88. sound {
  89. compatible = "fsl,imx6q-sabresd-wm8962",
  90. "fsl,imx-audio-wm8962";
  91. model = "wm8962-audio";
  92. ssi-controller = <&ssi2>;
  93. audio-codec = <&codec>;
  94. audio-routing =
  95. "Headphone Jack", "HPOUTL",
  96. "Headphone Jack", "HPOUTR",
  97. "Ext Spk", "SPKOUTL",
  98. "Ext Spk", "SPKOUTR",
  99. "MICBIAS", "AMIC",
  100. "IN3R", "MICBIAS",
  101. "DMIC", "MICBIAS",
  102. "DMICDAT", "DMIC";
  103. mux-int-port = <2>;
  104. mux-ext-port = <3>;
  105. };
  106. backlight {
  107. compatible = "pwm-backlight";
  108. pwms = <&pwm1 0 5000000>;
  109. brightness-levels = <0 4 8 16 32 64 128 255>;
  110. default-brightness-level = <7>;
  111. status = "okay";
  112. };
  113. leds {
  114. compatible = "gpio-leds";
  115. pinctrl-names = "default";
  116. pinctrl-0 = <&pinctrl_gpio_leds>;
  117. red {
  118. gpios = <&gpio1 2 0>;
  119. default-state = "on";
  120. };
  121. };
  122. };
  123. &audmux {
  124. pinctrl-names = "default";
  125. pinctrl-0 = <&pinctrl_audmux>;
  126. status = "okay";
  127. };
  128. &ecspi1 {
  129. fsl,spi-num-chipselects = <1>;
  130. cs-gpios = <&gpio4 9 0>;
  131. pinctrl-names = "default";
  132. pinctrl-0 = <&pinctrl_ecspi1>;
  133. status = "okay";
  134. flash: m25p80@0 {
  135. #address-cells = <1>;
  136. #size-cells = <1>;
  137. compatible = "st,m25p32";
  138. spi-max-frequency = <20000000>;
  139. reg = <0>;
  140. };
  141. };
  142. &fec {
  143. pinctrl-names = "default";
  144. pinctrl-0 = <&pinctrl_enet>;
  145. phy-mode = "rgmii";
  146. phy-reset-gpios = <&gpio1 25 0>;
  147. status = "okay";
  148. };
  149. &hdmi {
  150. ddc-i2c-bus = <&i2c2>;
  151. status = "okay";
  152. };
  153. &i2c1 {
  154. clock-frequency = <100000>;
  155. pinctrl-names = "default";
  156. pinctrl-0 = <&pinctrl_i2c1>;
  157. status = "okay";
  158. codec: wm8962@1a {
  159. compatible = "wlf,wm8962";
  160. reg = <0x1a>;
  161. clocks = <&clks 201>;
  162. DCVDD-supply = <&reg_audio>;
  163. DBVDD-supply = <&reg_audio>;
  164. AVDD-supply = <&reg_audio>;
  165. CPVDD-supply = <&reg_audio>;
  166. MICVDD-supply = <&reg_audio>;
  167. PLLVDD-supply = <&reg_audio>;
  168. SPKVDD1-supply = <&reg_audio>;
  169. SPKVDD2-supply = <&reg_audio>;
  170. gpio-cfg = <
  171. 0x0000 /* 0:Default */
  172. 0x0000 /* 1:Default */
  173. 0x0013 /* 2:FN_DMICCLK */
  174. 0x0000 /* 3:Default */
  175. 0x8014 /* 4:FN_DMICCDAT */
  176. 0x0000 /* 5:Default */
  177. >;
  178. };
  179. };
  180. &i2c2 {
  181. clock-frequency = <100000>;
  182. pinctrl-names = "default";
  183. pinctrl-0 = <&pinctrl_i2c2>;
  184. status = "okay";
  185. pmic: pfuze100@08 {
  186. compatible = "fsl,pfuze100";
  187. reg = <0x08>;
  188. regulators {
  189. sw1a_reg: sw1ab {
  190. regulator-min-microvolt = <300000>;
  191. regulator-max-microvolt = <1875000>;
  192. regulator-boot-on;
  193. regulator-always-on;
  194. regulator-ramp-delay = <6250>;
  195. };
  196. sw1c_reg: sw1c {
  197. regulator-min-microvolt = <300000>;
  198. regulator-max-microvolt = <1875000>;
  199. regulator-boot-on;
  200. regulator-always-on;
  201. regulator-ramp-delay = <6250>;
  202. };
  203. sw2_reg: sw2 {
  204. regulator-min-microvolt = <800000>;
  205. regulator-max-microvolt = <3300000>;
  206. regulator-boot-on;
  207. regulator-always-on;
  208. };
  209. sw3a_reg: sw3a {
  210. regulator-min-microvolt = <400000>;
  211. regulator-max-microvolt = <1975000>;
  212. regulator-boot-on;
  213. regulator-always-on;
  214. };
  215. sw3b_reg: sw3b {
  216. regulator-min-microvolt = <400000>;
  217. regulator-max-microvolt = <1975000>;
  218. regulator-boot-on;
  219. regulator-always-on;
  220. };
  221. sw4_reg: sw4 {
  222. regulator-min-microvolt = <800000>;
  223. regulator-max-microvolt = <3300000>;
  224. };
  225. swbst_reg: swbst {
  226. regulator-min-microvolt = <5000000>;
  227. regulator-max-microvolt = <5150000>;
  228. };
  229. snvs_reg: vsnvs {
  230. regulator-min-microvolt = <1000000>;
  231. regulator-max-microvolt = <3000000>;
  232. regulator-boot-on;
  233. regulator-always-on;
  234. };
  235. vref_reg: vrefddr {
  236. regulator-boot-on;
  237. regulator-always-on;
  238. };
  239. vgen1_reg: vgen1 {
  240. regulator-min-microvolt = <800000>;
  241. regulator-max-microvolt = <1550000>;
  242. };
  243. vgen2_reg: vgen2 {
  244. regulator-min-microvolt = <800000>;
  245. regulator-max-microvolt = <1550000>;
  246. };
  247. vgen3_reg: vgen3 {
  248. regulator-min-microvolt = <1800000>;
  249. regulator-max-microvolt = <3300000>;
  250. };
  251. vgen4_reg: vgen4 {
  252. regulator-min-microvolt = <1800000>;
  253. regulator-max-microvolt = <3300000>;
  254. regulator-always-on;
  255. };
  256. vgen5_reg: vgen5 {
  257. regulator-min-microvolt = <1800000>;
  258. regulator-max-microvolt = <3300000>;
  259. regulator-always-on;
  260. };
  261. vgen6_reg: vgen6 {
  262. regulator-min-microvolt = <1800000>;
  263. regulator-max-microvolt = <3300000>;
  264. regulator-always-on;
  265. };
  266. };
  267. };
  268. };
  269. &i2c3 {
  270. clock-frequency = <100000>;
  271. pinctrl-names = "default";
  272. pinctrl-0 = <&pinctrl_i2c3>;
  273. status = "okay";
  274. egalax_ts@04 {
  275. compatible = "eeti,egalax_ts";
  276. reg = <0x04>;
  277. interrupt-parent = <&gpio6>;
  278. interrupts = <7 2>;
  279. wakeup-gpios = <&gpio6 7 0>;
  280. };
  281. };
  282. &iomuxc {
  283. pinctrl-names = "default";
  284. pinctrl-0 = <&pinctrl_hog>;
  285. imx6qdl-sabresd {
  286. pinctrl_hog: hoggrp {
  287. fsl,pins = <
  288. MX6QDL_PAD_NANDF_D0__GPIO2_IO00 0x1b0b0
  289. MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x1b0b0
  290. MX6QDL_PAD_NANDF_D2__GPIO2_IO02 0x1b0b0
  291. MX6QDL_PAD_NANDF_D3__GPIO2_IO03 0x1b0b0
  292. MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x130b0
  293. MX6QDL_PAD_NANDF_CLE__GPIO6_IO07 0x1b0b0
  294. MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x1b0b0
  295. MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x1b0b0
  296. MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0x1b0b0
  297. >;
  298. };
  299. pinctrl_audmux: audmuxgrp {
  300. fsl,pins = <
  301. MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x130b0
  302. MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x130b0
  303. MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x110b0
  304. MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x130b0
  305. >;
  306. };
  307. pinctrl_ecspi1: ecspi1grp {
  308. fsl,pins = <
  309. MX6QDL_PAD_KEY_COL1__ECSPI1_MISO 0x100b1
  310. MX6QDL_PAD_KEY_ROW0__ECSPI1_MOSI 0x100b1
  311. MX6QDL_PAD_KEY_COL0__ECSPI1_SCLK 0x100b1
  312. MX6QDL_PAD_KEY_ROW1__GPIO4_IO09 0x1b0b0
  313. >;
  314. };
  315. pinctrl_enet: enetgrp {
  316. fsl,pins = <
  317. MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
  318. MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
  319. MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0
  320. MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0
  321. MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0
  322. MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0
  323. MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0
  324. MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0
  325. MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
  326. MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0
  327. MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0
  328. MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0
  329. MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0
  330. MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0
  331. MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0
  332. MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8
  333. >;
  334. };
  335. pinctrl_gpio_keys: gpio_keysgrp {
  336. fsl,pins = <
  337. MX6QDL_PAD_EIM_D29__GPIO3_IO29 0x1b0b0
  338. MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x1b0b0
  339. MX6QDL_PAD_GPIO_5__GPIO1_IO05 0x1b0b0
  340. >;
  341. };
  342. pinctrl_i2c1: i2c1grp {
  343. fsl,pins = <
  344. MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x4001b8b1
  345. MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x4001b8b1
  346. >;
  347. };
  348. pinctrl_i2c2: i2c2grp {
  349. fsl,pins = <
  350. MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1
  351. MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
  352. >;
  353. };
  354. pinctrl_i2c3: i2c3grp {
  355. fsl,pins = <
  356. MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1
  357. MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1
  358. >;
  359. };
  360. pinctrl_pcie: pciegrp {
  361. fsl,pins = <
  362. MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x1b0b0
  363. >;
  364. };
  365. pinctrl_pcie_reg: pciereggrp {
  366. fsl,pins = <
  367. MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x1b0b0
  368. >;
  369. };
  370. pinctrl_pwm1: pwm1grp {
  371. fsl,pins = <
  372. MX6QDL_PAD_SD1_DAT3__PWM1_OUT 0x1b0b1
  373. >;
  374. };
  375. pinctrl_uart1: uart1grp {
  376. fsl,pins = <
  377. MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1
  378. MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1
  379. >;
  380. };
  381. pinctrl_usbotg: usbotggrp {
  382. fsl,pins = <
  383. MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x17059
  384. >;
  385. };
  386. pinctrl_usdhc2: usdhc2grp {
  387. fsl,pins = <
  388. MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059
  389. MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059
  390. MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059
  391. MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059
  392. MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059
  393. MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059
  394. MX6QDL_PAD_NANDF_D4__SD2_DATA4 0x17059
  395. MX6QDL_PAD_NANDF_D5__SD2_DATA5 0x17059
  396. MX6QDL_PAD_NANDF_D6__SD2_DATA6 0x17059
  397. MX6QDL_PAD_NANDF_D7__SD2_DATA7 0x17059
  398. >;
  399. };
  400. pinctrl_usdhc3: usdhc3grp {
  401. fsl,pins = <
  402. MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059
  403. MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059
  404. MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
  405. MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
  406. MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
  407. MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
  408. MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17059
  409. MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17059
  410. MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17059
  411. MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17059
  412. >;
  413. };
  414. pinctrl_usdhc4: usdhc4grp {
  415. fsl,pins = <
  416. MX6QDL_PAD_SD4_CMD__SD4_CMD 0x17059
  417. MX6QDL_PAD_SD4_CLK__SD4_CLK 0x10059
  418. MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17059
  419. MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17059
  420. MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17059
  421. MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17059
  422. MX6QDL_PAD_SD4_DAT4__SD4_DATA4 0x17059
  423. MX6QDL_PAD_SD4_DAT5__SD4_DATA5 0x17059
  424. MX6QDL_PAD_SD4_DAT6__SD4_DATA6 0x17059
  425. MX6QDL_PAD_SD4_DAT7__SD4_DATA7 0x17059
  426. >;
  427. };
  428. };
  429. gpio_leds {
  430. pinctrl_gpio_leds: gpioledsgrp {
  431. fsl,pins = <
  432. MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x1b0b0
  433. >;
  434. };
  435. };
  436. };
  437. &ldb {
  438. status = "okay";
  439. lvds-channel@1 {
  440. fsl,data-mapping = "spwg";
  441. fsl,data-width = <18>;
  442. status = "okay";
  443. display-timings {
  444. native-mode = <&timing0>;
  445. timing0: hsd100pxn1 {
  446. clock-frequency = <65000000>;
  447. hactive = <1024>;
  448. vactive = <768>;
  449. hback-porch = <220>;
  450. hfront-porch = <40>;
  451. vback-porch = <21>;
  452. vfront-porch = <7>;
  453. hsync-len = <60>;
  454. vsync-len = <10>;
  455. };
  456. };
  457. };
  458. };
  459. &pcie {
  460. pinctrl-names = "default";
  461. pinctrl-0 = <&pinctrl_pcie>;
  462. reset-gpio = <&gpio7 12 0>;
  463. status = "okay";
  464. };
  465. &pwm1 {
  466. pinctrl-names = "default";
  467. pinctrl-0 = <&pinctrl_pwm1>;
  468. status = "okay";
  469. };
  470. &ssi2 {
  471. status = "okay";
  472. };
  473. &uart1 {
  474. pinctrl-names = "default";
  475. pinctrl-0 = <&pinctrl_uart1>;
  476. status = "okay";
  477. };
  478. &usbh1 {
  479. vbus-supply = <&reg_usb_h1_vbus>;
  480. status = "okay";
  481. };
  482. &usbotg {
  483. vbus-supply = <&reg_usb_otg_vbus>;
  484. pinctrl-names = "default";
  485. pinctrl-0 = <&pinctrl_usbotg>;
  486. disable-over-current;
  487. status = "okay";
  488. };
  489. &usdhc2 {
  490. pinctrl-names = "default";
  491. pinctrl-0 = <&pinctrl_usdhc2>;
  492. bus-width = <8>;
  493. cd-gpios = <&gpio2 2 0>;
  494. wp-gpios = <&gpio2 3 0>;
  495. status = "okay";
  496. };
  497. &usdhc3 {
  498. pinctrl-names = "default";
  499. pinctrl-0 = <&pinctrl_usdhc3>;
  500. bus-width = <8>;
  501. cd-gpios = <&gpio2 0 0>;
  502. wp-gpios = <&gpio2 1 0>;
  503. status = "okay";
  504. };
  505. &usdhc4 {
  506. pinctrl-names = "default";
  507. pinctrl-0 = <&pinctrl_usdhc4>;
  508. bus-width = <8>;
  509. non-removable;
  510. no-1-8-v;
  511. status = "okay";
  512. };