imx6sl-evk.dts 15 KB

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  1. /*
  2. * Copyright (C) 2013 Freescale Semiconductor, Inc.
  3. *
  4. * This program is free software; you can redistribute it and/or modify
  5. * it under the terms of the GNU General Public License version 2 as
  6. * published by the Free Software Foundation.
  7. */
  8. /dts-v1/;
  9. #include <dt-bindings/gpio/gpio.h>
  10. #include <dt-bindings/input/input.h>
  11. #include "imx6sl.dtsi"
  12. / {
  13. model = "Freescale i.MX6 SoloLite EVK Board";
  14. compatible = "fsl,imx6sl-evk", "fsl,imx6sl";
  15. memory {
  16. reg = <0x80000000 0x40000000>;
  17. };
  18. backlight {
  19. compatible = "pwm-backlight";
  20. pwms = <&pwm1 0 5000000>;
  21. brightness-levels = <0 4 8 16 32 64 128 255>;
  22. default-brightness-level = <6>;
  23. };
  24. leds {
  25. compatible = "gpio-leds";
  26. pinctrl-names = "default";
  27. pinctrl-0 = <&pinctrl_led>;
  28. user {
  29. label = "debug";
  30. gpios = <&gpio3 20 GPIO_ACTIVE_HIGH>;
  31. linux,default-trigger = "heartbeat";
  32. };
  33. };
  34. regulators {
  35. compatible = "simple-bus";
  36. #address-cells = <1>;
  37. #size-cells = <0>;
  38. reg_usb_otg1_vbus: regulator@0 {
  39. compatible = "regulator-fixed";
  40. reg = <0>;
  41. regulator-name = "usb_otg1_vbus";
  42. regulator-min-microvolt = <5000000>;
  43. regulator-max-microvolt = <5000000>;
  44. gpio = <&gpio4 0 0>;
  45. enable-active-high;
  46. };
  47. reg_usb_otg2_vbus: regulator@1 {
  48. compatible = "regulator-fixed";
  49. reg = <1>;
  50. regulator-name = "usb_otg2_vbus";
  51. regulator-min-microvolt = <5000000>;
  52. regulator-max-microvolt = <5000000>;
  53. gpio = <&gpio4 2 0>;
  54. enable-active-high;
  55. };
  56. reg_aud3v: regulator@2 {
  57. compatible = "regulator-fixed";
  58. reg = <2>;
  59. regulator-name = "wm8962-supply-3v15";
  60. regulator-min-microvolt = <3150000>;
  61. regulator-max-microvolt = <3150000>;
  62. regulator-boot-on;
  63. };
  64. reg_aud4v: regulator@3 {
  65. compatible = "regulator-fixed";
  66. reg = <3>;
  67. regulator-name = "wm8962-supply-4v2";
  68. regulator-min-microvolt = <4325000>;
  69. regulator-max-microvolt = <4325000>;
  70. regulator-boot-on;
  71. };
  72. reg_lcd_3v3: regulator@4 {
  73. compatible = "regulator-fixed";
  74. reg = <4>;
  75. regulator-name = "lcd-3v3";
  76. gpio = <&gpio4 3 0>;
  77. enable-active-high;
  78. };
  79. };
  80. sound {
  81. compatible = "fsl,imx6sl-evk-wm8962", "fsl,imx-audio-wm8962";
  82. model = "wm8962-audio";
  83. ssi-controller = <&ssi2>;
  84. audio-codec = <&codec>;
  85. audio-routing =
  86. "Headphone Jack", "HPOUTL",
  87. "Headphone Jack", "HPOUTR",
  88. "Ext Spk", "SPKOUTL",
  89. "Ext Spk", "SPKOUTR",
  90. "AMIC", "MICBIAS",
  91. "IN3R", "AMIC";
  92. mux-int-port = <2>;
  93. mux-ext-port = <3>;
  94. };
  95. };
  96. &audmux {
  97. pinctrl-names = "default";
  98. pinctrl-0 = <&pinctrl_audmux3>;
  99. status = "okay";
  100. };
  101. &ecspi1 {
  102. fsl,spi-num-chipselects = <1>;
  103. cs-gpios = <&gpio4 11 0>;
  104. pinctrl-names = "default";
  105. pinctrl-0 = <&pinctrl_ecspi1>;
  106. status = "okay";
  107. flash: m25p80@0 {
  108. #address-cells = <1>;
  109. #size-cells = <1>;
  110. compatible = "st,m25p32";
  111. spi-max-frequency = <20000000>;
  112. reg = <0>;
  113. };
  114. };
  115. &fec {
  116. pinctrl-names = "default", "sleep";
  117. pinctrl-0 = <&pinctrl_fec>;
  118. pinctrl-1 = <&pinctrl_fec_sleep>;
  119. phy-mode = "rmii";
  120. status = "okay";
  121. };
  122. &i2c1 {
  123. clock-frequency = <100000>;
  124. pinctrl-names = "default";
  125. pinctrl-0 = <&pinctrl_i2c1>;
  126. status = "okay";
  127. pmic: pfuze100@08 {
  128. compatible = "fsl,pfuze100";
  129. reg = <0x08>;
  130. regulators {
  131. sw1a_reg: sw1ab {
  132. regulator-min-microvolt = <300000>;
  133. regulator-max-microvolt = <1875000>;
  134. regulator-boot-on;
  135. regulator-always-on;
  136. regulator-ramp-delay = <6250>;
  137. };
  138. sw1c_reg: sw1c {
  139. regulator-min-microvolt = <300000>;
  140. regulator-max-microvolt = <1875000>;
  141. regulator-boot-on;
  142. regulator-always-on;
  143. regulator-ramp-delay = <6250>;
  144. };
  145. sw2_reg: sw2 {
  146. regulator-min-microvolt = <800000>;
  147. regulator-max-microvolt = <3300000>;
  148. regulator-boot-on;
  149. regulator-always-on;
  150. };
  151. sw3a_reg: sw3a {
  152. regulator-min-microvolt = <400000>;
  153. regulator-max-microvolt = <1975000>;
  154. regulator-boot-on;
  155. regulator-always-on;
  156. };
  157. sw3b_reg: sw3b {
  158. regulator-min-microvolt = <400000>;
  159. regulator-max-microvolt = <1975000>;
  160. regulator-boot-on;
  161. regulator-always-on;
  162. };
  163. sw4_reg: sw4 {
  164. regulator-min-microvolt = <800000>;
  165. regulator-max-microvolt = <3300000>;
  166. };
  167. swbst_reg: swbst {
  168. regulator-min-microvolt = <5000000>;
  169. regulator-max-microvolt = <5150000>;
  170. };
  171. snvs_reg: vsnvs {
  172. regulator-min-microvolt = <1000000>;
  173. regulator-max-microvolt = <3000000>;
  174. regulator-boot-on;
  175. regulator-always-on;
  176. };
  177. vref_reg: vrefddr {
  178. regulator-boot-on;
  179. regulator-always-on;
  180. };
  181. vgen1_reg: vgen1 {
  182. regulator-min-microvolt = <800000>;
  183. regulator-max-microvolt = <1550000>;
  184. regulator-always-on;
  185. };
  186. vgen2_reg: vgen2 {
  187. regulator-min-microvolt = <800000>;
  188. regulator-max-microvolt = <1550000>;
  189. };
  190. vgen3_reg: vgen3 {
  191. regulator-min-microvolt = <1800000>;
  192. regulator-max-microvolt = <3300000>;
  193. };
  194. vgen4_reg: vgen4 {
  195. regulator-min-microvolt = <1800000>;
  196. regulator-max-microvolt = <3300000>;
  197. regulator-always-on;
  198. };
  199. vgen5_reg: vgen5 {
  200. regulator-min-microvolt = <1800000>;
  201. regulator-max-microvolt = <3300000>;
  202. regulator-always-on;
  203. };
  204. vgen6_reg: vgen6 {
  205. regulator-min-microvolt = <1800000>;
  206. regulator-max-microvolt = <3300000>;
  207. regulator-always-on;
  208. };
  209. };
  210. };
  211. };
  212. &i2c2 {
  213. clock-frequency = <100000>;
  214. pinctrl-names = "default";
  215. pinctrl-0 = <&pinctrl_i2c2>;
  216. status = "okay";
  217. codec: wm8962@1a {
  218. compatible = "wlf,wm8962";
  219. reg = <0x1a>;
  220. clocks = <&clks IMX6SL_CLK_EXTERN_AUDIO>;
  221. DCVDD-supply = <&vgen3_reg>;
  222. DBVDD-supply = <&reg_aud3v>;
  223. AVDD-supply = <&vgen3_reg>;
  224. CPVDD-supply = <&vgen3_reg>;
  225. MICVDD-supply = <&reg_aud3v>;
  226. PLLVDD-supply = <&vgen3_reg>;
  227. SPKVDD1-supply = <&reg_aud4v>;
  228. SPKVDD2-supply = <&reg_aud4v>;
  229. };
  230. };
  231. &iomuxc {
  232. pinctrl-names = "default";
  233. pinctrl-0 = <&pinctrl_hog>;
  234. imx6sl-evk {
  235. pinctrl_hog: hoggrp {
  236. fsl,pins = <
  237. MX6SL_PAD_KEY_ROW7__GPIO4_IO07 0x17059
  238. MX6SL_PAD_KEY_COL7__GPIO4_IO06 0x17059
  239. MX6SL_PAD_SD2_DAT7__GPIO5_IO00 0x17059
  240. MX6SL_PAD_SD2_DAT6__GPIO4_IO29 0x17059
  241. MX6SL_PAD_REF_CLK_32K__GPIO3_IO22 0x17059
  242. MX6SL_PAD_KEY_COL4__GPIO4_IO00 0x80000000
  243. MX6SL_PAD_KEY_COL5__GPIO4_IO02 0x80000000
  244. MX6SL_PAD_AUD_MCLK__AUDIO_CLK_OUT 0x4130b0
  245. >;
  246. };
  247. pinctrl_audmux3: audmux3grp {
  248. fsl,pins = <
  249. MX6SL_PAD_AUD_RXD__AUD3_RXD 0x4130b0
  250. MX6SL_PAD_AUD_TXC__AUD3_TXC 0x4130b0
  251. MX6SL_PAD_AUD_TXD__AUD3_TXD 0x4110b0
  252. MX6SL_PAD_AUD_TXFS__AUD3_TXFS 0x4130b0
  253. >;
  254. };
  255. pinctrl_ecspi1: ecspi1grp {
  256. fsl,pins = <
  257. MX6SL_PAD_ECSPI1_MISO__ECSPI1_MISO 0x100b1
  258. MX6SL_PAD_ECSPI1_MOSI__ECSPI1_MOSI 0x100b1
  259. MX6SL_PAD_ECSPI1_SCLK__ECSPI1_SCLK 0x100b1
  260. MX6SL_PAD_ECSPI1_SS0__GPIO4_IO11 0x80000000
  261. >;
  262. };
  263. pinctrl_fec: fecgrp {
  264. fsl,pins = <
  265. MX6SL_PAD_FEC_MDC__FEC_MDC 0x1b0b0
  266. MX6SL_PAD_FEC_MDIO__FEC_MDIO 0x1b0b0
  267. MX6SL_PAD_FEC_CRS_DV__FEC_RX_DV 0x1b0b0
  268. MX6SL_PAD_FEC_RXD0__FEC_RX_DATA0 0x1b0b0
  269. MX6SL_PAD_FEC_RXD1__FEC_RX_DATA1 0x1b0b0
  270. MX6SL_PAD_FEC_TX_EN__FEC_TX_EN 0x1b0b0
  271. MX6SL_PAD_FEC_TXD0__FEC_TX_DATA0 0x1b0b0
  272. MX6SL_PAD_FEC_TXD1__FEC_TX_DATA1 0x1b0b0
  273. MX6SL_PAD_FEC_REF_CLK__FEC_REF_OUT 0x4001b0a8
  274. >;
  275. };
  276. pinctrl_fec_sleep: fecgrp-sleep {
  277. fsl,pins = <
  278. MX6SL_PAD_FEC_MDC__GPIO4_IO23 0x3080
  279. MX6SL_PAD_FEC_CRS_DV__GPIO4_IO25 0x3080
  280. MX6SL_PAD_FEC_RXD0__GPIO4_IO17 0x3080
  281. MX6SL_PAD_FEC_RXD1__GPIO4_IO18 0x3080
  282. MX6SL_PAD_FEC_TX_EN__GPIO4_IO22 0x3080
  283. MX6SL_PAD_FEC_TXD0__GPIO4_IO24 0x3080
  284. MX6SL_PAD_FEC_TXD1__GPIO4_IO16 0x3080
  285. MX6SL_PAD_FEC_REF_CLK__GPIO4_IO26 0x3080
  286. >;
  287. };
  288. pinctrl_i2c1: i2c1grp {
  289. fsl,pins = <
  290. MX6SL_PAD_I2C1_SCL__I2C1_SCL 0x4001b8b1
  291. MX6SL_PAD_I2C1_SDA__I2C1_SDA 0x4001b8b1
  292. >;
  293. };
  294. pinctrl_i2c2: i2c2grp {
  295. fsl,pins = <
  296. MX6SL_PAD_I2C2_SCL__I2C2_SCL 0x4001b8b1
  297. MX6SL_PAD_I2C2_SDA__I2C2_SDA 0x4001b8b1
  298. >;
  299. };
  300. pinctrl_kpp: kppgrp {
  301. fsl,pins = <
  302. MX6SL_PAD_KEY_ROW0__KEY_ROW0 0x1b010
  303. MX6SL_PAD_KEY_ROW1__KEY_ROW1 0x1b010
  304. MX6SL_PAD_KEY_ROW2__KEY_ROW2 0x1b0b0
  305. MX6SL_PAD_KEY_COL0__KEY_COL0 0x110b0
  306. MX6SL_PAD_KEY_COL1__KEY_COL1 0x110b0
  307. MX6SL_PAD_KEY_COL2__KEY_COL2 0x110b0
  308. >;
  309. };
  310. pinctrl_lcd: lcdgrp {
  311. fsl,pins = <
  312. MX6SL_PAD_LCD_DAT0__LCD_DATA00 0x1b0b0
  313. MX6SL_PAD_LCD_DAT1__LCD_DATA01 0x1b0b0
  314. MX6SL_PAD_LCD_DAT2__LCD_DATA02 0x1b0b0
  315. MX6SL_PAD_LCD_DAT3__LCD_DATA03 0x1b0b0
  316. MX6SL_PAD_LCD_DAT4__LCD_DATA04 0x1b0b0
  317. MX6SL_PAD_LCD_DAT5__LCD_DATA05 0x1b0b0
  318. MX6SL_PAD_LCD_DAT6__LCD_DATA06 0x1b0b0
  319. MX6SL_PAD_LCD_DAT7__LCD_DATA07 0x1b0b0
  320. MX6SL_PAD_LCD_DAT8__LCD_DATA08 0x1b0b0
  321. MX6SL_PAD_LCD_DAT9__LCD_DATA09 0x1b0b0
  322. MX6SL_PAD_LCD_DAT10__LCD_DATA10 0x1b0b0
  323. MX6SL_PAD_LCD_DAT11__LCD_DATA11 0x1b0b0
  324. MX6SL_PAD_LCD_DAT12__LCD_DATA12 0x1b0b0
  325. MX6SL_PAD_LCD_DAT13__LCD_DATA13 0x1b0b0
  326. MX6SL_PAD_LCD_DAT14__LCD_DATA14 0x1b0b0
  327. MX6SL_PAD_LCD_DAT15__LCD_DATA15 0x1b0b0
  328. MX6SL_PAD_LCD_DAT16__LCD_DATA16 0x1b0b0
  329. MX6SL_PAD_LCD_DAT17__LCD_DATA17 0x1b0b0
  330. MX6SL_PAD_LCD_DAT18__LCD_DATA18 0x1b0b0
  331. MX6SL_PAD_LCD_DAT19__LCD_DATA19 0x1b0b0
  332. MX6SL_PAD_LCD_DAT20__LCD_DATA20 0x1b0b0
  333. MX6SL_PAD_LCD_DAT21__LCD_DATA21 0x1b0b0
  334. MX6SL_PAD_LCD_DAT22__LCD_DATA22 0x1b0b0
  335. MX6SL_PAD_LCD_DAT23__LCD_DATA23 0x1b0b0
  336. MX6SL_PAD_LCD_CLK__LCD_CLK 0x1b0b0
  337. MX6SL_PAD_LCD_ENABLE__LCD_ENABLE 0x1b0b0
  338. MX6SL_PAD_LCD_HSYNC__LCD_HSYNC 0x1b0b0
  339. MX6SL_PAD_LCD_VSYNC__LCD_VSYNC 0x1b0b0
  340. >;
  341. };
  342. pinctrl_led: ledgrp {
  343. fsl,pins = <
  344. MX6SL_PAD_HSIC_STROBE__GPIO3_IO20 0x17059
  345. >;
  346. };
  347. pinctrl_pwm1: pwmgrp {
  348. fsl,pins = <
  349. MX6SL_PAD_PWM1__PWM1_OUT 0x110b0
  350. >;
  351. };
  352. pinctrl_uart1: uart1grp {
  353. fsl,pins = <
  354. MX6SL_PAD_UART1_RXD__UART1_RX_DATA 0x1b0b1
  355. MX6SL_PAD_UART1_TXD__UART1_TX_DATA 0x1b0b1
  356. >;
  357. };
  358. pinctrl_usbotg1: usbotg1grp {
  359. fsl,pins = <
  360. MX6SL_PAD_EPDC_PWRCOM__USB_OTG1_ID 0x17059
  361. >;
  362. };
  363. pinctrl_usdhc1: usdhc1grp {
  364. fsl,pins = <
  365. MX6SL_PAD_SD1_CMD__SD1_CMD 0x17059
  366. MX6SL_PAD_SD1_CLK__SD1_CLK 0x10059
  367. MX6SL_PAD_SD1_DAT0__SD1_DATA0 0x17059
  368. MX6SL_PAD_SD1_DAT1__SD1_DATA1 0x17059
  369. MX6SL_PAD_SD1_DAT2__SD1_DATA2 0x17059
  370. MX6SL_PAD_SD1_DAT3__SD1_DATA3 0x17059
  371. MX6SL_PAD_SD1_DAT4__SD1_DATA4 0x17059
  372. MX6SL_PAD_SD1_DAT5__SD1_DATA5 0x17059
  373. MX6SL_PAD_SD1_DAT6__SD1_DATA6 0x17059
  374. MX6SL_PAD_SD1_DAT7__SD1_DATA7 0x17059
  375. >;
  376. };
  377. pinctrl_usdhc1_100mhz: usdhc1grp100mhz {
  378. fsl,pins = <
  379. MX6SL_PAD_SD1_CMD__SD1_CMD 0x170b9
  380. MX6SL_PAD_SD1_CLK__SD1_CLK 0x100b9
  381. MX6SL_PAD_SD1_DAT0__SD1_DATA0 0x170b9
  382. MX6SL_PAD_SD1_DAT1__SD1_DATA1 0x170b9
  383. MX6SL_PAD_SD1_DAT2__SD1_DATA2 0x170b9
  384. MX6SL_PAD_SD1_DAT3__SD1_DATA3 0x170b9
  385. MX6SL_PAD_SD1_DAT4__SD1_DATA4 0x170b9
  386. MX6SL_PAD_SD1_DAT5__SD1_DATA5 0x170b9
  387. MX6SL_PAD_SD1_DAT6__SD1_DATA6 0x170b9
  388. MX6SL_PAD_SD1_DAT7__SD1_DATA7 0x170b9
  389. >;
  390. };
  391. pinctrl_usdhc1_200mhz: usdhc1grp200mhz {
  392. fsl,pins = <
  393. MX6SL_PAD_SD1_CMD__SD1_CMD 0x170f9
  394. MX6SL_PAD_SD1_CLK__SD1_CLK 0x100f9
  395. MX6SL_PAD_SD1_DAT0__SD1_DATA0 0x170f9
  396. MX6SL_PAD_SD1_DAT1__SD1_DATA1 0x170f9
  397. MX6SL_PAD_SD1_DAT2__SD1_DATA2 0x170f9
  398. MX6SL_PAD_SD1_DAT3__SD1_DATA3 0x170f9
  399. MX6SL_PAD_SD1_DAT4__SD1_DATA4 0x170f9
  400. MX6SL_PAD_SD1_DAT5__SD1_DATA5 0x170f9
  401. MX6SL_PAD_SD1_DAT6__SD1_DATA6 0x170f9
  402. MX6SL_PAD_SD1_DAT7__SD1_DATA7 0x170f9
  403. >;
  404. };
  405. pinctrl_usdhc2: usdhc2grp {
  406. fsl,pins = <
  407. MX6SL_PAD_SD2_CMD__SD2_CMD 0x17059
  408. MX6SL_PAD_SD2_CLK__SD2_CLK 0x10059
  409. MX6SL_PAD_SD2_DAT0__SD2_DATA0 0x17059
  410. MX6SL_PAD_SD2_DAT1__SD2_DATA1 0x17059
  411. MX6SL_PAD_SD2_DAT2__SD2_DATA2 0x17059
  412. MX6SL_PAD_SD2_DAT3__SD2_DATA3 0x17059
  413. >;
  414. };
  415. pinctrl_usdhc2_100mhz: usdhc2grp100mhz {
  416. fsl,pins = <
  417. MX6SL_PAD_SD2_CMD__SD2_CMD 0x170b9
  418. MX6SL_PAD_SD2_CLK__SD2_CLK 0x100b9
  419. MX6SL_PAD_SD2_DAT0__SD2_DATA0 0x170b9
  420. MX6SL_PAD_SD2_DAT1__SD2_DATA1 0x170b9
  421. MX6SL_PAD_SD2_DAT2__SD2_DATA2 0x170b9
  422. MX6SL_PAD_SD2_DAT3__SD2_DATA3 0x170b9
  423. >;
  424. };
  425. pinctrl_usdhc2_200mhz: usdhc2grp200mhz {
  426. fsl,pins = <
  427. MX6SL_PAD_SD2_CMD__SD2_CMD 0x170f9
  428. MX6SL_PAD_SD2_CLK__SD2_CLK 0x100f9
  429. MX6SL_PAD_SD2_DAT0__SD2_DATA0 0x170f9
  430. MX6SL_PAD_SD2_DAT1__SD2_DATA1 0x170f9
  431. MX6SL_PAD_SD2_DAT2__SD2_DATA2 0x170f9
  432. MX6SL_PAD_SD2_DAT3__SD2_DATA3 0x170f9
  433. >;
  434. };
  435. pinctrl_usdhc3: usdhc3grp {
  436. fsl,pins = <
  437. MX6SL_PAD_SD3_CMD__SD3_CMD 0x17059
  438. MX6SL_PAD_SD3_CLK__SD3_CLK 0x10059
  439. MX6SL_PAD_SD3_DAT0__SD3_DATA0 0x17059
  440. MX6SL_PAD_SD3_DAT1__SD3_DATA1 0x17059
  441. MX6SL_PAD_SD3_DAT2__SD3_DATA2 0x17059
  442. MX6SL_PAD_SD3_DAT3__SD3_DATA3 0x17059
  443. >;
  444. };
  445. pinctrl_usdhc3_100mhz: usdhc3grp100mhz {
  446. fsl,pins = <
  447. MX6SL_PAD_SD3_CMD__SD3_CMD 0x170b9
  448. MX6SL_PAD_SD3_CLK__SD3_CLK 0x100b9
  449. MX6SL_PAD_SD3_DAT0__SD3_DATA0 0x170b9
  450. MX6SL_PAD_SD3_DAT1__SD3_DATA1 0x170b9
  451. MX6SL_PAD_SD3_DAT2__SD3_DATA2 0x170b9
  452. MX6SL_PAD_SD3_DAT3__SD3_DATA3 0x170b9
  453. >;
  454. };
  455. pinctrl_usdhc3_200mhz: usdhc3grp200mhz {
  456. fsl,pins = <
  457. MX6SL_PAD_SD3_CMD__SD3_CMD 0x170f9
  458. MX6SL_PAD_SD3_CLK__SD3_CLK 0x100f9
  459. MX6SL_PAD_SD3_DAT0__SD3_DATA0 0x170f9
  460. MX6SL_PAD_SD3_DAT1__SD3_DATA1 0x170f9
  461. MX6SL_PAD_SD3_DAT2__SD3_DATA2 0x170f9
  462. MX6SL_PAD_SD3_DAT3__SD3_DATA3 0x170f9
  463. >;
  464. };
  465. };
  466. };
  467. &kpp {
  468. pinctrl-names = "default";
  469. pinctrl-0 = <&pinctrl_kpp>;
  470. linux,keymap = <
  471. MATRIX_KEY(0x0, 0x0, KEY_UP) /* ROW0, COL0 */
  472. MATRIX_KEY(0x0, 0x1, KEY_DOWN) /* ROW0, COL1 */
  473. MATRIX_KEY(0x0, 0x2, KEY_ENTER) /* ROW0, COL2 */
  474. MATRIX_KEY(0x1, 0x0, KEY_HOME) /* ROW1, COL0 */
  475. MATRIX_KEY(0x1, 0x1, KEY_RIGHT) /* ROW1, COL1 */
  476. MATRIX_KEY(0x1, 0x2, KEY_LEFT) /* ROW1, COL2 */
  477. MATRIX_KEY(0x2, 0x0, KEY_VOLUMEDOWN) /* ROW2, COL0 */
  478. MATRIX_KEY(0x2, 0x1, KEY_VOLUMEUP) /* ROW2, COL1 */
  479. >;
  480. status = "okay";
  481. };
  482. &lcdif {
  483. pinctrl-names = "default";
  484. pinctrl-0 = <&pinctrl_lcd>;
  485. lcd-supply = <&reg_lcd_3v3>;
  486. display = <&display0>;
  487. status = "okay";
  488. display0: display0 {
  489. bits-per-pixel = <32>;
  490. bus-width = <24>;
  491. display-timings {
  492. native-mode = <&timing0>;
  493. timing0: timing0 {
  494. clock-frequency = <33500000>;
  495. hactive = <800>;
  496. vactive = <480>;
  497. hback-porch = <89>;
  498. hfront-porch = <164>;
  499. vback-porch = <23>;
  500. vfront-porch = <10>;
  501. hsync-len = <10>;
  502. vsync-len = <10>;
  503. hsync-active = <0>;
  504. vsync-active = <0>;
  505. de-active = <1>;
  506. pixelclk-active = <0>;
  507. };
  508. };
  509. };
  510. };
  511. &pwm1 {
  512. pinctrl-names = "default";
  513. pinctrl-0 = <&pinctrl_pwm1>;
  514. status = "okay";
  515. };
  516. &ssi2 {
  517. status = "okay";
  518. };
  519. &uart1 {
  520. pinctrl-names = "default";
  521. pinctrl-0 = <&pinctrl_uart1>;
  522. status = "okay";
  523. };
  524. &usbotg1 {
  525. vbus-supply = <&reg_usb_otg1_vbus>;
  526. pinctrl-names = "default";
  527. pinctrl-0 = <&pinctrl_usbotg1>;
  528. disable-over-current;
  529. status = "okay";
  530. };
  531. &usbotg2 {
  532. vbus-supply = <&reg_usb_otg2_vbus>;
  533. dr_mode = "host";
  534. disable-over-current;
  535. status = "okay";
  536. };
  537. &usdhc1 {
  538. pinctrl-names = "default", "state_100mhz", "state_200mhz";
  539. pinctrl-0 = <&pinctrl_usdhc1>;
  540. pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
  541. pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
  542. bus-width = <8>;
  543. cd-gpios = <&gpio4 7 0>;
  544. wp-gpios = <&gpio4 6 0>;
  545. status = "okay";
  546. };
  547. &usdhc2 {
  548. pinctrl-names = "default", "state_100mhz", "state_200mhz";
  549. pinctrl-0 = <&pinctrl_usdhc2>;
  550. pinctrl-1 = <&pinctrl_usdhc2_100mhz>;
  551. pinctrl-2 = <&pinctrl_usdhc2_200mhz>;
  552. cd-gpios = <&gpio5 0 0>;
  553. wp-gpios = <&gpio4 29 0>;
  554. status = "okay";
  555. };
  556. &usdhc3 {
  557. pinctrl-names = "default", "state_100mhz", "state_200mhz";
  558. pinctrl-0 = <&pinctrl_usdhc3>;
  559. pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
  560. pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
  561. cd-gpios = <&gpio3 22 0>;
  562. status = "okay";
  563. };