kirkwood-6282.dtsi 3.5 KB

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  1. / {
  2. mbus {
  3. pciec: pcie-controller {
  4. compatible = "marvell,kirkwood-pcie";
  5. status = "disabled";
  6. device_type = "pci";
  7. #address-cells = <3>;
  8. #size-cells = <2>;
  9. bus-range = <0x00 0xff>;
  10. ranges =
  11. <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000
  12. 0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000
  13. 0x82000000 0 0x80000 MBUS_ID(0xf0, 0x01) 0x80000 0 0x00002000
  14. 0x82000000 0x1 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0.0 MEM */
  15. 0x81000000 0x1 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0.0 IO */
  16. 0x82000000 0x2 0 MBUS_ID(0x04, 0xd8) 0 1 0 /* Port 1.0 MEM */
  17. 0x81000000 0x2 0 MBUS_ID(0x04, 0xd0) 0 1 0 /* Port 1.0 IO */>;
  18. pcie0: pcie@1,0 {
  19. device_type = "pci";
  20. assigned-addresses = <0x82000800 0 0x00040000 0 0x2000>;
  21. reg = <0x0800 0 0 0 0>;
  22. #address-cells = <3>;
  23. #size-cells = <2>;
  24. #interrupt-cells = <1>;
  25. ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0
  26. 0x81000000 0 0 0x81000000 0x1 0 1 0>;
  27. interrupt-map-mask = <0 0 0 0>;
  28. interrupt-map = <0 0 0 0 &intc 9>;
  29. marvell,pcie-port = <0>;
  30. marvell,pcie-lane = <0>;
  31. clocks = <&gate_clk 2>;
  32. status = "disabled";
  33. };
  34. pcie1: pcie@2,0 {
  35. device_type = "pci";
  36. assigned-addresses = <0x82001000 0 0x00044000 0 0x2000>;
  37. reg = <0x1000 0 0 0 0>;
  38. #address-cells = <3>;
  39. #size-cells = <2>;
  40. #interrupt-cells = <1>;
  41. ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0
  42. 0x81000000 0 0 0x81000000 0x2 0 1 0>;
  43. interrupt-map-mask = <0 0 0 0>;
  44. interrupt-map = <0 0 0 0 &intc 10>;
  45. marvell,pcie-port = <1>;
  46. marvell,pcie-lane = <0>;
  47. clocks = <&gate_clk 18>;
  48. status = "disabled";
  49. };
  50. };
  51. };
  52. ocp@f1000000 {
  53. pinctrl: pin-controller@10000 {
  54. compatible = "marvell,88f6282-pinctrl";
  55. pmx_sata0: pmx-sata0 {
  56. marvell,pins = "mpp5", "mpp21", "mpp23";
  57. marvell,function = "sata0";
  58. };
  59. pmx_sata1: pmx-sata1 {
  60. marvell,pins = "mpp4", "mpp20", "mpp22";
  61. marvell,function = "sata1";
  62. };
  63. /*
  64. * Default I2C1 pinctrl setting on mpp36/mpp37,
  65. * overwrite marvell,pins on board level if required.
  66. */
  67. pmx_twsi1: pmx-twsi1 {
  68. marvell,pins = "mpp36", "mpp37";
  69. marvell,function = "twsi1";
  70. };
  71. pmx_sdio: pmx-sdio {
  72. marvell,pins = "mpp12", "mpp13", "mpp14",
  73. "mpp15", "mpp16", "mpp17";
  74. marvell,function = "sdio";
  75. };
  76. };
  77. thermal: thermal@10078 {
  78. compatible = "marvell,kirkwood-thermal";
  79. reg = <0x10078 0x4>;
  80. status = "okay";
  81. };
  82. rtc: rtc@10300 {
  83. compatible = "marvell,kirkwood-rtc", "marvell,orion-rtc";
  84. reg = <0x10300 0x20>;
  85. interrupts = <53>;
  86. clocks = <&gate_clk 7>;
  87. };
  88. i2c1: i2c@11100 {
  89. compatible = "marvell,mv64xxx-i2c";
  90. reg = <0x11100 0x20>;
  91. #address-cells = <1>;
  92. #size-cells = <0>;
  93. interrupts = <32>;
  94. clock-frequency = <100000>;
  95. clocks = <&gate_clk 7>;
  96. pinctrl-0 = <&pmx_twsi1>;
  97. pinctrl-names = "default";
  98. status = "disabled";
  99. };
  100. sata: sata@80000 {
  101. compatible = "marvell,orion-sata";
  102. reg = <0x80000 0x5000>;
  103. interrupts = <21>;
  104. clocks = <&gate_clk 14>, <&gate_clk 15>;
  105. clock-names = "0", "1";
  106. phys = <&sata_phy0>, <&sata_phy1>;
  107. phy-names = "port0", "port1";
  108. status = "disabled";
  109. };
  110. sdio: mvsdio@90000 {
  111. compatible = "marvell,orion-sdio";
  112. reg = <0x90000 0x200>;
  113. interrupts = <28>;
  114. clocks = <&gate_clk 4>;
  115. pinctrl-0 = <&pmx_sdio>;
  116. pinctrl-names = "default";
  117. bus-width = <4>;
  118. cap-sdio-irq;
  119. cap-sd-highspeed;
  120. cap-mmc-highspeed;
  121. status = "disabled";
  122. };
  123. };
  124. };