moxart.dtsi 2.9 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148
  1. /* moxart.dtsi - Device Tree Include file for MOXA ART family SoC
  2. *
  3. * Copyright (C) 2013 Jonas Jensen <jonas.jensen@gmail.com>
  4. *
  5. * Licensed under GPLv2 or later.
  6. */
  7. /include/ "skeleton.dtsi"
  8. / {
  9. compatible = "moxa,moxart";
  10. model = "MOXART";
  11. interrupt-parent = <&intc>;
  12. cpus {
  13. #address-cells = <1>;
  14. #size-cells = <0>;
  15. cpu@0 {
  16. device_type = "cpu";
  17. compatible = "faraday,fa526";
  18. reg = <0>;
  19. };
  20. };
  21. clocks {
  22. #address-cells = <1>;
  23. #size-cells = <0>;
  24. };
  25. soc {
  26. compatible = "simple-bus";
  27. #address-cells = <1>;
  28. #size-cells = <1>;
  29. reg = <0x90000000 0x10000000>;
  30. ranges;
  31. intc: interrupt-controller@98800000 {
  32. compatible = "moxa,moxart-ic";
  33. reg = <0x98800000 0x38>;
  34. interrupt-controller;
  35. #interrupt-cells = <2>;
  36. interrupt-mask = <0x00080000>;
  37. };
  38. clk_pll: clk_pll@98100000 {
  39. compatible = "moxa,moxart-pll-clock";
  40. #clock-cells = <0>;
  41. reg = <0x98100000 0x34>;
  42. };
  43. clk_apb: clk_apb@98100000 {
  44. compatible = "moxa,moxart-apb-clock";
  45. #clock-cells = <0>;
  46. reg = <0x98100000 0x34>;
  47. clocks = <&clk_pll>;
  48. };
  49. timer: timer@98400000 {
  50. compatible = "moxa,moxart-timer";
  51. reg = <0x98400000 0x42>;
  52. interrupts = <19 1>;
  53. clocks = <&clk_apb>;
  54. };
  55. gpio: gpio@98700000 {
  56. gpio-controller;
  57. #gpio-cells = <2>;
  58. compatible = "moxa,moxart-gpio";
  59. reg = <0x98700000 0xC>;
  60. };
  61. rtc: rtc {
  62. compatible = "moxa,moxart-rtc";
  63. gpio-rtc-sclk = <&gpio 5 0>;
  64. gpio-rtc-data = <&gpio 6 0>;
  65. gpio-rtc-reset = <&gpio 7 0>;
  66. };
  67. dma: dma@90500000 {
  68. compatible = "moxa,moxart-dma";
  69. reg = <0x90500080 0x40>;
  70. interrupts = <24 0>;
  71. #dma-cells = <1>;
  72. };
  73. watchdog: watchdog@98500000 {
  74. compatible = "moxa,moxart-watchdog";
  75. reg = <0x98500000 0x10>;
  76. clocks = <&clk_apb>;
  77. };
  78. sdhci: sdhci@98e00000 {
  79. compatible = "moxa,moxart-sdhci";
  80. reg = <0x98e00000 0x5C>;
  81. interrupts = <5 0>;
  82. clocks = <&clk_apb>;
  83. dmas = <&dma 5>,
  84. <&dma 5>;
  85. dma-names = "tx", "rx";
  86. status = "disabled";
  87. };
  88. mdio0: mdio@90900090 {
  89. compatible = "moxa,moxart-mdio";
  90. reg = <0x90900090 0x8>;
  91. #address-cells = <1>;
  92. #size-cells = <0>;
  93. status = "disabled";
  94. };
  95. mdio1: mdio@92000090 {
  96. compatible = "moxa,moxart-mdio";
  97. reg = <0x92000090 0x8>;
  98. #address-cells = <1>;
  99. #size-cells = <0>;
  100. status = "disabled";
  101. };
  102. mac0: mac@90900000 {
  103. compatible = "moxa,moxart-mac";
  104. reg = <0x90900000 0x90>;
  105. interrupts = <25 0>;
  106. phy-handle = <&ethphy0>;
  107. phy-mode = "mii";
  108. status = "disabled";
  109. };
  110. mac1: mac@92000000 {
  111. compatible = "moxa,moxart-mac";
  112. reg = <0x92000000 0x90>;
  113. interrupts = <27 0>;
  114. phy-handle = <&ethphy1>;
  115. phy-mode = "mii";
  116. status = "disabled";
  117. };
  118. uart0: uart@98200000 {
  119. compatible = "ns16550a";
  120. reg = <0x98200000 0x20>;
  121. interrupts = <31 8>;
  122. reg-shift = <2>;
  123. reg-io-width = <4>;
  124. clock-frequency = <14745600>;
  125. status = "disabled";
  126. };
  127. };
  128. };