omap3-evm-37xx.dts 6.4 KB

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  1. /*
  2. * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
  3. *
  4. * This program is free software; you can redistribute it and/or modify
  5. * it under the terms of the GNU General Public License version 2 as
  6. * published by the Free Software Foundation.
  7. */
  8. /dts-v1/;
  9. #include "omap36xx.dtsi"
  10. #include "omap3-evm-common.dtsi"
  11. / {
  12. model = "TI OMAP37XX EVM (TMDSEVM3730)";
  13. compatible = "ti,omap3-evm-37xx", "ti,omap36xx";
  14. memory {
  15. device_type = "memory";
  16. reg = <0x80000000 0x10000000>; /* 256 MB */
  17. };
  18. wl12xx_vmmc: wl12xx_vmmc {
  19. pinctrl-names = "default";
  20. pinctrl-0 = <&wl12xx_gpio>;
  21. };
  22. };
  23. &dss {
  24. pinctrl-names = "default";
  25. pinctrl-0 = <
  26. &dss_dpi_pins1
  27. &dss_dpi_pins2
  28. >;
  29. };
  30. &omap3_pmx_core {
  31. dss_dpi_pins1: pinmux_dss_dpi_pins2 {
  32. pinctrl-single,pins = <
  33. OMAP3_CORE1_IOPAD(0x20d4, PIN_OUTPUT | MUX_MODE0) /* dss_pclk.dss_pclk */
  34. OMAP3_CORE1_IOPAD(0x20d6, PIN_OUTPUT | MUX_MODE0) /* dss_hsync.dss_hsync */
  35. OMAP3_CORE1_IOPAD(0x20d8, PIN_OUTPUT | MUX_MODE0) /* dss_vsync.dss_vsync */
  36. OMAP3_CORE1_IOPAD(0x20da, PIN_OUTPUT | MUX_MODE0) /* dss_acbias.dss_acbias */
  37. OMAP3_CORE1_IOPAD(0x20e8, PIN_OUTPUT | MUX_MODE0) /* dss_data6.dss_data6 */
  38. OMAP3_CORE1_IOPAD(0x20ea, PIN_OUTPUT | MUX_MODE0) /* dss_data7.dss_data7 */
  39. OMAP3_CORE1_IOPAD(0x20ec, PIN_OUTPUT | MUX_MODE0) /* dss_data8.dss_data8 */
  40. OMAP3_CORE1_IOPAD(0x20ee, PIN_OUTPUT | MUX_MODE0) /* dss_data9.dss_data9 */
  41. OMAP3_CORE1_IOPAD(0x20f0, PIN_OUTPUT | MUX_MODE0) /* dss_data10.dss_data10 */
  42. OMAP3_CORE1_IOPAD(0x20f2, PIN_OUTPUT | MUX_MODE0) /* dss_data11.dss_data11 */
  43. OMAP3_CORE1_IOPAD(0x20f4, PIN_OUTPUT | MUX_MODE0) /* dss_data12.dss_data12 */
  44. OMAP3_CORE1_IOPAD(0x20f6, PIN_OUTPUT | MUX_MODE0) /* dss_data13.dss_data13 */
  45. OMAP3_CORE1_IOPAD(0x20f8, PIN_OUTPUT | MUX_MODE0) /* dss_data14.dss_data14 */
  46. OMAP3_CORE1_IOPAD(0x20fa, PIN_OUTPUT | MUX_MODE0) /* dss_data15.dss_data15 */
  47. OMAP3_CORE1_IOPAD(0x20fc, PIN_OUTPUT | MUX_MODE0) /* dss_data16.dss_data16 */
  48. OMAP3_CORE1_IOPAD(0x20fe, PIN_OUTPUT | MUX_MODE0) /* dss_data17.dss_data17 */
  49. OMAP3_CORE1_IOPAD(0x2100, PIN_OUTPUT | MUX_MODE3) /* dss_data18.dss_data0 */
  50. OMAP3_CORE1_IOPAD(0x2102, PIN_OUTPUT | MUX_MODE3) /* dss_data19.dss_data1 */
  51. OMAP3_CORE1_IOPAD(0x2104, PIN_OUTPUT | MUX_MODE3) /* dss_data20.dss_data2 */
  52. OMAP3_CORE1_IOPAD(0x2106, PIN_OUTPUT | MUX_MODE3) /* dss_data21.dss_data3 */
  53. OMAP3_CORE1_IOPAD(0x2108, PIN_OUTPUT | MUX_MODE3) /* dss_data22.dss_data4 */
  54. OMAP3_CORE1_IOPAD(0x210a, PIN_OUTPUT | MUX_MODE3) /* dss_data23.dss_data5 */
  55. >;
  56. };
  57. mmc1_pins: pinmux_mmc1_pins {
  58. pinctrl-single,pins = <
  59. 0x114 (PIN_OUTPUT_PULLUP | MUX_MODE0) /* sdmmc1_clk.sdmmc1_clk */
  60. 0x116 (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_cmd.sdmmc1_cmd */
  61. 0x118 (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat0.sdmmc1_dat0 */
  62. 0x11a (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat1.sdmmc1_dat1 */
  63. 0x11c (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat2.sdmmc1_dat2 */
  64. 0x11e (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat3.sdmmc1_dat3 */
  65. 0x120 (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat4.sdmmc1_dat4 */
  66. 0x122 (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat5.sdmmc1_dat5 */
  67. 0x124 (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat6.sdmmc1_dat6 */
  68. 0x126 (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat7.sdmmc1_dat7 */
  69. >;
  70. };
  71. /* NOTE: Clocked externally, needs INPUT also for sdmmc2_clk.sdmmc2_clk */
  72. mmc2_pins: pinmux_mmc2_pins {
  73. pinctrl-single,pins = <
  74. 0x128 (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_clk.sdmmc2_clk */
  75. 0x12a (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_cmd.sdmmc2_cmd */
  76. 0x12c (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat0.sdmmc2_dat0 */
  77. 0x12e (WAKEUP_EN | PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat1.sdmmc2_dat1 */
  78. 0x130 (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat2.sdmmc2_dat2 */
  79. 0x132 (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat3.sdmmc2_dat3 */
  80. >;
  81. };
  82. uart3_pins: pinmux_uart3_pins {
  83. pinctrl-single,pins = <
  84. 0x16e (WAKEUP_EN | PIN_INPUT | MUX_MODE0) /* uart3_rx_irrx.uart3_rx_irrx */
  85. 0x170 (PIN_OUTPUT | MUX_MODE0) /* uart3_tx_irtx.uart3_tx_irtx */
  86. >;
  87. };
  88. wl12xx_gpio: pinmux_wl12xx_gpio {
  89. pinctrl-single,pins = <
  90. 0x150 (PIN_OUTPUT | MUX_MODE4) /* uart1_cts.gpio_150 */
  91. 0x14e (PIN_INPUT | MUX_MODE4) /* uart1_rts.gpio_149 */
  92. >;
  93. };
  94. smsc911x_pins: pinmux_smsc911x_pins {
  95. pinctrl-single,pins = <
  96. 0x1a2 (PIN_INPUT | MUX_MODE4) /* mcspi1_cs2.gpio_176 */
  97. >;
  98. };
  99. };
  100. &omap3_pmx_wkup {
  101. dss_dpi_pins2: pinmux_dss_dpi_pins1 {
  102. pinctrl-single,pins = <
  103. 0x0a (PIN_OUTPUT | MUX_MODE3) /* sys_boot0.dss_data18 */
  104. 0x0c (PIN_OUTPUT | MUX_MODE3) /* sys_boot1.dss_data19 */
  105. 0x10 (PIN_OUTPUT | MUX_MODE3) /* sys_boot3.dss_data20 */
  106. 0x12 (PIN_OUTPUT | MUX_MODE3) /* sys_boot4.dss_data21 */
  107. 0x14 (PIN_OUTPUT | MUX_MODE3) /* sys_boot5.dss_data22 */
  108. 0x16 (PIN_OUTPUT | MUX_MODE3) /* sys_boot6.dss_data23 */
  109. >;
  110. };
  111. };
  112. &mmc1 {
  113. pinctrl-names = "default";
  114. pinctrl-0 = <&mmc1_pins>;
  115. };
  116. &mmc2 {
  117. pinctrl-names = "default";
  118. pinctrl-0 = <&mmc2_pins>;
  119. };
  120. &mmc3 {
  121. status = "disabled";
  122. };
  123. &uart1 {
  124. interrupts-extended = <&intc 72 &omap3_pmx_core OMAP3_UART1_RX>;
  125. };
  126. &uart2 {
  127. interrupts-extended = <&intc 73 &omap3_pmx_core OMAP3_UART2_RX>;
  128. };
  129. &uart3 {
  130. interrupts-extended = <&intc 74 &omap3_pmx_core OMAP3_UART3_RX>;
  131. pinctrl-names = "default";
  132. pinctrl-0 = <&uart3_pins>;
  133. };
  134. &gpmc {
  135. ranges = <0 0 0x00000000 0x20000000>,
  136. <5 0 0x2c000000 0x01000000>;
  137. nand@0,0 {
  138. linux,mtd-name= "hynix,h8kds0un0mer-4em";
  139. reg = <0 0 0>;
  140. nand-bus-width = <16>;
  141. ti,nand-ecc-opt = "bch8";
  142. gpmc,sync-clk-ps = <0>;
  143. gpmc,cs-on-ns = <0>;
  144. gpmc,cs-rd-off-ns = <44>;
  145. gpmc,cs-wr-off-ns = <44>;
  146. gpmc,adv-on-ns = <6>;
  147. gpmc,adv-rd-off-ns = <34>;
  148. gpmc,adv-wr-off-ns = <44>;
  149. gpmc,we-off-ns = <40>;
  150. gpmc,oe-off-ns = <54>;
  151. gpmc,access-ns = <64>;
  152. gpmc,rd-cycle-ns = <82>;
  153. gpmc,wr-cycle-ns = <82>;
  154. gpmc,wr-access-ns = <40>;
  155. gpmc,wr-data-mux-bus-ns = <0>;
  156. #address-cells = <1>;
  157. #size-cells = <1>;
  158. partition@0 {
  159. label = "X-Loader";
  160. reg = <0 0x80000>;
  161. };
  162. partition@0x80000 {
  163. label = "U-Boot";
  164. reg = <0x80000 0x1c0000>;
  165. };
  166. partition@0x1c0000 {
  167. label = "Environment";
  168. reg = <0x240000 0x40000>;
  169. };
  170. partition@0x280000 {
  171. label = "Kernel";
  172. reg = <0x280000 0x500000>;
  173. };
  174. partition@0x780000 {
  175. label = "Filesystem";
  176. reg = <0x780000 0x1f880000>;
  177. };
  178. };
  179. ethernet@gpmc {
  180. pinctrl-names = "default";
  181. pinctrl-0 = <&smsc911x_pins>;
  182. };
  183. };