omap3-lilly-a83x.dtsi 12 KB

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  1. /*
  2. * Copyright (C) 2014 Christoph Fritz <chf.fritzc@googlemail.com>
  3. *
  4. * This program is free software; you can redistribute it and/or modify
  5. * it under the terms of the GNU General Public License as published by
  6. * the Free Software Foundation; either version 2 of the License, or
  7. * (at your option) any later version.
  8. */
  9. #include "omap36xx.dtsi"
  10. / {
  11. model = "INCOstartec LILLY-A83X module (DM3730)";
  12. compatible = "incostartec,omap3-lilly-a83x", "ti,omap36xx", "ti,omap3";
  13. chosen {
  14. bootargs = "console=ttyO0,115200n8 vt.global_cursor_default=0 consoleblank=0";
  15. };
  16. memory {
  17. device_type = "memory";
  18. reg = <0x80000000 0x8000000>; /* 128 MB */
  19. };
  20. leds {
  21. compatible = "gpio-leds";
  22. led1 {
  23. label = "lilly-a83x::led1";
  24. gpios = <&gpio1 29 GPIO_ACTIVE_LOW>;
  25. linux,default-trigger = "default-on";
  26. };
  27. };
  28. sound {
  29. compatible = "ti,omap-twl4030";
  30. ti,model = "lilly-a83x";
  31. ti,mcbsp = <&mcbsp2>;
  32. ti,codec = <&twl_audio>;
  33. };
  34. reg_vcc3: vcc3 {
  35. compatible = "regulator-fixed";
  36. regulator-name = "VCC3";
  37. regulator-min-microvolt = <3300000>;
  38. regulator-max-microvolt = <3300000>;
  39. regulator-always-on;
  40. };
  41. hsusb1_phy: hsusb1_phy {
  42. compatible = "usb-nop-xceiv";
  43. vcc-supply = <&reg_vcc3>;
  44. };
  45. };
  46. &omap3_pmx_wkup {
  47. pinctrl-names = "default";
  48. lan9221_pins: pinmux_lan9221_pins {
  49. pinctrl-single,pins = <
  50. OMAP3_WKUP_IOPAD(0x2a5a, PIN_INPUT | MUX_MODE4) /* reserved.gpio_129 */
  51. >;
  52. };
  53. tsc2048_pins: pinmux_tsc2048_pins {
  54. pinctrl-single,pins = <
  55. OMAP3_WKUP_IOPAD(0x2a16, PIN_INPUT_PULLUP | MUX_MODE4) /* sys_boot6.gpio_8 */
  56. >;
  57. };
  58. mmc1cd_pins: pinmux_mmc1cd_pins {
  59. pinctrl-single,pins = <
  60. OMAP3_WKUP_IOPAD(0x2a56, PIN_INPUT | MUX_MODE4) /* reserved.gpio_126 */
  61. >;
  62. };
  63. };
  64. &omap3_pmx_core {
  65. pinctrl-names = "default";
  66. uart1_pins: pinmux_uart1_pins {
  67. pinctrl-single,pins = <
  68. OMAP3_CORE1_IOPAD(0x217c, PIN_OUTPUT | MUX_MODE0) /* uart1_tx.uart1_tx */
  69. OMAP3_CORE1_IOPAD(0x217e, PIN_OUTPUT | MUX_MODE0) /* uart1_rts.uart1_rts */
  70. OMAP3_CORE1_IOPAD(0x2180, PIN_INPUT | MUX_MODE0) /* uart1_cts.uart1_cts */
  71. OMAP3_CORE1_IOPAD(0x2182, PIN_INPUT | MUX_MODE0) /* uart1_rx.uart1_rx */
  72. >;
  73. };
  74. uart2_pins: pinmux_uart2_pins {
  75. pinctrl-single,pins = <
  76. OMAP3_CORE1_IOPAD(0x2170, PIN_OUTPUT | MUX_MODE1) /* mcbsp3_clkx.uart2_tx */
  77. OMAP3_CORE1_IOPAD(0x2172, PIN_INPUT | MUX_MODE1) /* mcbsp3_fsx.uart2_rx */
  78. >;
  79. };
  80. uart3_pins: pinmux_uart3_pins {
  81. pinctrl-single,pins = <
  82. OMAP3_CORE1_IOPAD(0x219e, PIN_INPUT | MUX_MODE0) /* uart3_rx_irrx.uart3_rx_irrx */
  83. OMAP3_CORE1_IOPAD(0x21a0, PIN_OUTPUT | MUX_MODE0) /* uart3_tx_irtx.uart3_tx_irtx */
  84. >;
  85. };
  86. i2c1_pins: pinmux_i2c1_pins {
  87. pinctrl-single,pins = <
  88. OMAP3_CORE1_IOPAD(0x21ba ,PIN_INPUT_PULLUP | MUX_MODE0) /* i2c1_scl.i2c1_scl */
  89. OMAP3_CORE1_IOPAD(0x21bc ,PIN_INPUT_PULLUP | MUX_MODE0) /* i2c1_sda.i2c1_sda */
  90. >;
  91. };
  92. i2c2_pins: pinmux_i2c2_pins {
  93. pinctrl-single,pins = <
  94. OMAP3_CORE1_IOPAD(0x21be, PIN_INPUT | MUX_MODE0) /* i2c2_scl.i2c2_scl */
  95. OMAP3_CORE1_IOPAD(0x21c0, PIN_INPUT | MUX_MODE0) /* i2c2_sda.i2c2_sda */
  96. >;
  97. };
  98. i2c3_pins: pinmux_i2c3_pins {
  99. pinctrl-single,pins = <
  100. OMAP3_CORE1_IOPAD(0x21c2, PIN_INPUT | MUX_MODE0) /* i2c3_scl.i2c3_scl */
  101. OMAP3_CORE1_IOPAD(0x21c4, PIN_INPUT | MUX_MODE0) /* i2c3_sda.i2c3_sda */
  102. >;
  103. };
  104. hsusb1_pins: pinmux_hsusb1_pins {
  105. pinctrl-single,pins = <
  106. /* GPIO 182 controls USB-Hub reset. But USB-Phy its
  107. * reset can't be controlled. So we clamp this GPIO to
  108. * high (PIN_OFF_OUTPUT_HIGH) to always enable USB-Hub.
  109. */
  110. OMAP3_CORE1_IOPAD(0x21de, PIN_OUTPUT_PULLUP | PIN_OFF_OUTPUT_HIGH | MUX_MODE4) /* mcspi2_cs1.gpio_182 */
  111. >;
  112. };
  113. hsusb_otg_pins: pinmux_hsusb_otg_pins {
  114. pinctrl-single,pins = <
  115. OMAP3_CORE1_IOPAD(0x21a2, PIN_INPUT | MUX_MODE0) /* hsusb0_clk.hsusb0_clk */
  116. OMAP3_CORE1_IOPAD(0x21a4, PIN_OUTPUT | MUX_MODE0) /* hsusb0_stp.hsusb0_stp */
  117. OMAP3_CORE1_IOPAD(0x21a6, PIN_INPUT | MUX_MODE0) /* hsusb0_dir.hsusb0_dir */
  118. OMAP3_CORE1_IOPAD(0x21a8, PIN_INPUT | MUX_MODE0) /* hsusb0_nxt.hsusb0_nxt */
  119. OMAP3_CORE1_IOPAD(0x21aa, PIN_INPUT | MUX_MODE0) /* hsusb0_data0.hsusb0_data0 */
  120. OMAP3_CORE1_IOPAD(0x21ac, PIN_INPUT | MUX_MODE0) /* hsusb0_data1.hsusb0_data1 */
  121. OMAP3_CORE1_IOPAD(0x21ae, PIN_INPUT | MUX_MODE0) /* hsusb0_data2.hsusb0_data2 */
  122. OMAP3_CORE1_IOPAD(0x21b0, PIN_INPUT | MUX_MODE0) /* hsusb0_data3.hsusb0_data3 */
  123. OMAP3_CORE1_IOPAD(0x21b2, PIN_INPUT | MUX_MODE0) /* hsusb0_data4.hsusb0_data4 */
  124. OMAP3_CORE1_IOPAD(0x21b4, PIN_INPUT | MUX_MODE0) /* hsusb0_data5.hsusb0_data5 */
  125. OMAP3_CORE1_IOPAD(0x21b6, PIN_INPUT | MUX_MODE0) /* hsusb0_data6.hsusb0_data6 */
  126. OMAP3_CORE1_IOPAD(0x21b8, PIN_INPUT | MUX_MODE0) /* hsusb0_data7.hsusb0_data7 */
  127. >;
  128. };
  129. mmc1_pins: pinmux_mmc1_pins {
  130. pinctrl-single,pins = <
  131. OMAP3_CORE1_IOPAD(0x2144, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_clk.sdmmc1_clk */
  132. OMAP3_CORE1_IOPAD(0x2146, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_cmd.sdmmc1_cmd */
  133. OMAP3_CORE1_IOPAD(0x2148, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat0.sdmmc1_dat0 */
  134. OMAP3_CORE1_IOPAD(0x214a, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat1.sdmmc1_dat1 */
  135. OMAP3_CORE1_IOPAD(0x214c, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat2.sdmmc1_dat2 */
  136. OMAP3_CORE1_IOPAD(0x214e, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat3.sdmmc1_dat3 */
  137. >;
  138. };
  139. spi2_pins: pinmux_spi2_pins {
  140. pinctrl-single,pins = <
  141. OMAP3_CORE1_IOPAD(0x21d6, PIN_INPUT_PULLDOWN | MUX_MODE0) /* mcspi2_clk.mcspi2_clk */
  142. OMAP3_CORE1_IOPAD(0x21d8, PIN_INPUT_PULLDOWN | MUX_MODE0) /* mcspi2_simo.mcspi2_simo */
  143. OMAP3_CORE1_IOPAD(0x21da, PIN_INPUT_PULLDOWN | MUX_MODE0) /* mcspi2_somi.mcspi2_somi */
  144. OMAP3_CORE1_IOPAD(0x21dc, PIN_OUTPUT | MUX_MODE0) /* mcspi2_cs0.mcspi2_cs0 */
  145. >;
  146. };
  147. };
  148. &omap3_pmx_core2 {
  149. pinctrl-names = "default";
  150. hsusb1_2_pins: pinmux_hsusb1_2_pins {
  151. pinctrl-single,pins = <
  152. OMAP3630_CORE2_IOPAD(0x25d8, PIN_OUTPUT | MUX_MODE3) /* etk_clk.hsusb1_stp */
  153. OMAP3630_CORE2_IOPAD(0x25da, PIN_INPUT | MUX_MODE3) /* etk_ctl.hsusb1_clk */
  154. OMAP3630_CORE2_IOPAD(0x25dc, PIN_INPUT | MUX_MODE3) /* etk_d0.hsusb1_data0 */
  155. OMAP3630_CORE2_IOPAD(0x25de, PIN_INPUT | MUX_MODE3) /* etk_d1.hsusb1_data1 */
  156. OMAP3630_CORE2_IOPAD(0x25e0, PIN_INPUT | MUX_MODE3) /* etk_d2.hsusb1_data2 */
  157. OMAP3630_CORE2_IOPAD(0x25e2, PIN_INPUT | MUX_MODE3) /* etk_d3.hsusb1_data7 */
  158. OMAP3630_CORE2_IOPAD(0x25e4, PIN_INPUT | MUX_MODE3) /* etk_d4.hsusb1_data4 */
  159. OMAP3630_CORE2_IOPAD(0x25e6, PIN_INPUT | MUX_MODE3) /* etk_d5.hsusb1_data5 */
  160. OMAP3630_CORE2_IOPAD(0x25e8, PIN_INPUT | MUX_MODE3) /* etk_d6.hsusb1_data6 */
  161. OMAP3630_CORE2_IOPAD(0x25ea, PIN_INPUT | MUX_MODE3) /* etk_d7.hsusb1_data3 */
  162. OMAP3630_CORE2_IOPAD(0x25ec, PIN_INPUT | MUX_MODE3) /* etk_d8.hsusb1_dir */
  163. OMAP3630_CORE2_IOPAD(0x25ee, PIN_INPUT | MUX_MODE3) /* etk_d9.hsusb1_nxt */
  164. >;
  165. };
  166. gpio1_pins: pinmux_gpio1_pins {
  167. pinctrl-single,pins = <
  168. OMAP3630_CORE2_IOPAD(0x25fa, PIN_OUTPUT_PULLDOWN | MUX_MODE4) /* etk_d15.gpio_29 */
  169. >;
  170. };
  171. };
  172. &gpio1 {
  173. pinctrl-names = "default";
  174. pinctrl-0 = <&gpio1_pins>;
  175. };
  176. &gpio6 {
  177. pinctrl-names = "default";
  178. pinctrl-0 = <&hsusb1_pins>;
  179. };
  180. &i2c1 {
  181. clock-frequency = <2600000>;
  182. pinctrl-names = "default";
  183. pinctrl-0 = <&i2c1_pins>;
  184. twl: twl@48 {
  185. reg = <0x48>;
  186. interrupts = <7>; /* SYS_NIRQ cascaded to intc */
  187. interrupt-parent = <&intc>;
  188. twl_audio: audio {
  189. compatible = "ti,twl4030-audio";
  190. codec {
  191. };
  192. };
  193. };
  194. };
  195. #include "twl4030.dtsi"
  196. #include "twl4030_omap3.dtsi"
  197. &twl {
  198. vmmc1: regulator-vmmc1 {
  199. regulator-always-on;
  200. };
  201. vdd1: regulator-vdd1 {
  202. regulator-always-on;
  203. };
  204. vdd2: regulator-vdd2 {
  205. regulator-always-on;
  206. };
  207. };
  208. &i2c2 {
  209. clock-frequency = <2600000>;
  210. pinctrl-names = "default";
  211. pinctrl-0 = <&i2c2_pins>;
  212. };
  213. &i2c3 {
  214. clock-frequency = <2600000>;
  215. pinctrl-names = "default";
  216. pinctrl-0 = <&i2c3_pins>;
  217. gpiom1: gpio@20 {
  218. compatible = "mcp,mcp23017";
  219. gpio-controller;
  220. #gpio-cells = <2>;
  221. reg = <0x20>;
  222. };
  223. };
  224. &uart1 {
  225. pinctrl-names = "default";
  226. pinctrl-0 = <&uart1_pins>;
  227. };
  228. &uart2 {
  229. pinctrl-names = "default";
  230. pinctrl-0 = <&uart2_pins>;
  231. };
  232. &uart3 {
  233. pinctrl-names = "default";
  234. pinctrl-0 = <&uart3_pins>;
  235. };
  236. &uart4 {
  237. status = "disabled";
  238. };
  239. &mmc1 {
  240. cd-gpios = <&gpio4 30 IRQ_TYPE_LEVEL_LOW>;
  241. cd-inverted;
  242. vmmc-supply = <&vmmc1>;
  243. bus-width = <4>;
  244. pinctrl-names = "default";
  245. pinctrl-0 = <&mmc1_pins &mmc1cd_pins>;
  246. cap-sdio-irq;
  247. cap-sd-highspeed;
  248. cap-mmc-highspeed;
  249. };
  250. &mmc2 {
  251. status = "disabled";
  252. };
  253. &mmc3 {
  254. status = "disabled";
  255. };
  256. &mcspi2 {
  257. status = "okay";
  258. pinctrl-names = "default";
  259. pinctrl-0 = <&spi2_pins>;
  260. tsc2046@0 {
  261. reg = <0>; /* CS0 */
  262. compatible = "ti,tsc2046";
  263. interrupt-parent = <&gpio1>;
  264. interrupts = <8 0>; /* boot6 / gpio_8 */
  265. spi-max-frequency = <1000000>;
  266. pendown-gpio = <&gpio1 8 0>;
  267. vcc-supply = <&reg_vcc3>;
  268. pinctrl-names = "default";
  269. pinctrl-0 = <&tsc2048_pins>;
  270. ti,x-min = <300>;
  271. ti,x-max = <3000>;
  272. ti,y-min = <600>;
  273. ti,y-max = <3600>;
  274. ti,x-plate-ohms = <80>;
  275. ti,pressure-max = <255>;
  276. ti,swap-xy;
  277. linux,wakeup;
  278. };
  279. };
  280. &usbhsehci {
  281. phys = <&hsusb1_phy>;
  282. };
  283. &usbhshost {
  284. pinctrl-names = "default";
  285. pinctrl-0 = <&hsusb1_2_pins>;
  286. num-ports = <2>;
  287. port1-mode = "ehci-phy";
  288. };
  289. &usb_otg_hs {
  290. pinctrl-names = "default";
  291. pinctrl-0 = <&hsusb_otg_pins>;
  292. interface-type = <0>;
  293. usb-phy = <&usb2_phy>;
  294. phys = <&usb2_phy>;
  295. phy-names = "usb2-phy";
  296. mode = <3>;
  297. power = <50>;
  298. };
  299. &mcbsp2 {
  300. status = "okay";
  301. };
  302. &gpmc {
  303. ranges = <0 0 0x30000000 0x1000000>,
  304. <7 0 0x15000000 0x01000000>;
  305. nand@0,0 {
  306. reg = <0 0 0x1000000>;
  307. nand-bus-width = <16>;
  308. ti,nand-ecc-opt = "bch8";
  309. /* no elm on omap3 */
  310. gpmc,mux-add-data = <0>;
  311. gpmc,device-width = <2>;
  312. gpmc,wait-pin = <0>;
  313. gpmc,wait-monitoring-ns = <0>;
  314. gpmc,burst-length= <4>;
  315. gpmc,cs-on-ns = <0>;
  316. gpmc,cs-rd-off-ns = <100>;
  317. gpmc,cs-wr-off-ns = <100>;
  318. gpmc,adv-on-ns = <0>;
  319. gpmc,adv-rd-off-ns = <100>;
  320. gpmc,adv-wr-off-ns = <100>;
  321. gpmc,oe-on-ns = <5>;
  322. gpmc,oe-off-ns = <75>;
  323. gpmc,we-on-ns = <5>;
  324. gpmc,we-off-ns = <75>;
  325. gpmc,rd-cycle-ns = <100>;
  326. gpmc,wr-cycle-ns = <100>;
  327. gpmc,access-ns = <60>;
  328. gpmc,page-burst-access-ns = <5>;
  329. gpmc,bus-turnaround-ns = <0>;
  330. gpmc,cycle2cycle-samecsen;
  331. gpmc,cycle2cycle-delay-ns = <50>;
  332. gpmc,wr-data-mux-bus-ns = <75>;
  333. gpmc,wr-access-ns = <155>;
  334. #address-cells = <1>;
  335. #size-cells = <1>;
  336. partition@0 {
  337. label = "MLO";
  338. reg = <0 0x80000>;
  339. };
  340. partition@0x80000 {
  341. label = "u-boot";
  342. reg = <0x80000 0x1e0000>;
  343. };
  344. partition@0x260000 {
  345. label = "u-boot-environment";
  346. reg = <0x260000 0x20000>;
  347. };
  348. partition@0x280000 {
  349. label = "kernel";
  350. reg = <0x280000 0x500000>;
  351. };
  352. partition@0x780000 {
  353. label = "filesystem";
  354. reg = <0x780000 0xf880000>;
  355. };
  356. };
  357. ethernet@7,0 {
  358. compatible = "smsc,lan9221", "smsc,lan9115";
  359. bank-width = <2>;
  360. gpmc,mux-add-data = <2>;
  361. gpmc,cs-on-ns = <10>;
  362. gpmc,cs-rd-off-ns = <60>;
  363. gpmc,cs-wr-off-ns = <60>;
  364. gpmc,adv-on-ns = <0>;
  365. gpmc,adv-rd-off-ns = <10>;
  366. gpmc,adv-wr-off-ns = <10>;
  367. gpmc,oe-on-ns = <10>;
  368. gpmc,oe-off-ns = <60>;
  369. gpmc,we-on-ns = <10>;
  370. gpmc,we-off-ns = <60>;
  371. gpmc,rd-cycle-ns = <100>;
  372. gpmc,wr-cycle-ns = <100>;
  373. gpmc,access-ns = <50>;
  374. gpmc,page-burst-access-ns = <5>;
  375. gpmc,bus-turnaround-ns = <0>;
  376. gpmc,cycle2cycle-delay-ns = <75>;
  377. gpmc,wr-data-mux-bus-ns = <15>;
  378. gpmc,wr-access-ns = <75>;
  379. gpmc,cycle2cycle-samecsen;
  380. gpmc,cycle2cycle-diffcsen;
  381. vddvario-supply = <&reg_vcc3>;
  382. vdd33a-supply = <&reg_vcc3>;
  383. reg-io-width = <4>;
  384. interrupt-parent = <&gpio5>;
  385. interrupts = <1 0x2>;
  386. reg = <7 0 0xff>;
  387. pinctrl-names = "default";
  388. pinctrl-0 = <&lan9221_pins>;
  389. phy-mode = "mii";
  390. };
  391. };