omap3-tao3530.dtsi 9.0 KB

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  1. /*
  2. * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
  3. * Copyright (C) 2014 Stefan Roese <sr@denx.de>
  4. *
  5. * This program is free software; you can redistribute it and/or modify
  6. * it under the terms of the GNU General Public License version 2 as
  7. * published by the Free Software Foundation.
  8. */
  9. /dts-v1/;
  10. #include "omap34xx-hs.dtsi"
  11. / {
  12. cpus {
  13. cpu@0 {
  14. cpu0-supply = <&vcc>;
  15. };
  16. };
  17. memory {
  18. device_type = "memory";
  19. reg = <0x80000000 0x10000000>; /* 256 MB */
  20. };
  21. /* HS USB Port 2 Power */
  22. hsusb2_power: hsusb2_power_reg {
  23. compatible = "regulator-fixed";
  24. regulator-name = "hsusb2_vbus";
  25. regulator-min-microvolt = <3300000>;
  26. regulator-max-microvolt = <3300000>;
  27. gpio = <&twl_gpio 18 0>; /* GPIO LEDA */
  28. startup-delay-us = <70000>;
  29. };
  30. /* HS USB Host PHY on PORT 2 */
  31. hsusb2_phy: hsusb2_phy {
  32. compatible = "usb-nop-xceiv";
  33. reset-gpios = <&gpio6 2 GPIO_ACTIVE_LOW>; /* gpio_162 */
  34. vcc-supply = <&hsusb2_power>;
  35. };
  36. sound {
  37. compatible = "ti,omap-twl4030";
  38. ti,model = "omap3beagle";
  39. /* McBSP2 is used for onboard sound, same as on beagle */
  40. ti,mcbsp = <&mcbsp2>;
  41. ti,codec = <&twl_audio>;
  42. };
  43. /* Regulator to enable/switch the vcc of the Wifi module */
  44. mmc2_sdio_poweron: regulator-mmc2-sdio-poweron {
  45. compatible = "regulator-fixed";
  46. regulator-name = "regulator-mmc2-sdio-poweron";
  47. regulator-min-microvolt = <3150000>;
  48. regulator-max-microvolt = <3150000>;
  49. gpio = <&gpio5 29 GPIO_ACTIVE_LOW>; /* gpio_157 */
  50. enable-active-low;
  51. startup-delay-us = <10000>;
  52. };
  53. };
  54. &omap3_pmx_core {
  55. hsusbb2_pins: pinmux_hsusbb2_pins {
  56. pinctrl-single,pins = <
  57. OMAP3_CORE1_IOPAD(0x25f0, PIN_OUTPUT | MUX_MODE3) /* etk_d10.hsusb2_clk */
  58. OMAP3_CORE1_IOPAD(0x25f2, PIN_OUTPUT | MUX_MODE3) /* etk_d11.hsusb2_stp */
  59. OMAP3_CORE1_IOPAD(0x25f4, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d12.hsusb2_dir */
  60. OMAP3_CORE1_IOPAD(0x25f6, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d13.hsusb2_nxt */
  61. OMAP3_CORE1_IOPAD(0x25f8, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d14.hsusb2_data0 */
  62. OMAP3_CORE1_IOPAD(0x25fa, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d15.hsusb2_data1 */
  63. OMAP3_CORE1_IOPAD(0x21d4, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi1_cs3.hsusb2_data2 */
  64. OMAP3_CORE1_IOPAD(0x21d6, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_clk.hsusb2_data7 */
  65. OMAP3_CORE1_IOPAD(0x21d8, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_simo.hsusb2_data4 */
  66. OMAP3_CORE1_IOPAD(0x21da, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_somi.hsusb2_data5 */
  67. OMAP3_CORE1_IOPAD(0x21dc, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_cs0.hsusb2_data6 */
  68. OMAP3_CORE1_IOPAD(0x21de, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_cs1.hsusb2_data3 */
  69. >;
  70. };
  71. mmc1_pins: pinmux_mmc1_pins {
  72. pinctrl-single,pins = <
  73. OMAP3_CORE1_IOPAD(0x2144, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_clk.sdmmc1_clk */
  74. OMAP3_CORE1_IOPAD(0x2146, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_cmd.sdmmc1_cmd */
  75. OMAP3_CORE1_IOPAD(0x2148, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat0.sdmmc1_dat0 */
  76. OMAP3_CORE1_IOPAD(0x214a, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat1.sdmmc1_dat1 */
  77. OMAP3_CORE1_IOPAD(0x214c, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat2.sdmmc1_dat2 */
  78. OMAP3_CORE1_IOPAD(0x214e, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat3.sdmmc1_dat3 */
  79. OMAP3_CORE1_IOPAD(0x2150, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat4.sdmmc1_dat4 */
  80. OMAP3_CORE1_IOPAD(0x2152, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat5.sdmmc1_dat5 */
  81. OMAP3_CORE1_IOPAD(0x2154, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat6.sdmmc1_dat6 */
  82. OMAP3_CORE1_IOPAD(0x2156, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat7.sdmmc1_dat7 */
  83. >;
  84. };
  85. mmc2_pins: pinmux_mmc2_pins {
  86. pinctrl-single,pins = <
  87. OMAP3_CORE1_IOPAD(0x2158, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_clk.sdmmc2_clk */
  88. OMAP3_CORE1_IOPAD(0x215a, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_cmd.sdmmc2_cmd */
  89. OMAP3_CORE1_IOPAD(0x215c, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat0.sdmmc2_dat0 */
  90. OMAP3_CORE1_IOPAD(0x215e, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat1.sdmmc2_dat1 */
  91. OMAP3_CORE1_IOPAD(0x2160, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat2.sdmmc2_dat2 */
  92. OMAP3_CORE1_IOPAD(0x2162, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat3.sdmmc2_dat3 */
  93. >;
  94. };
  95. /* wlan GPIO output for WLAN_EN */
  96. wlan_gpio: pinmux_wlan_gpio {
  97. pinctrl-single,pins = <
  98. OMAP3_CORE1_IOPAD(0x218e, PIN_OUTPUT | MUX_MODE4) /* mcbsp1_fsr gpio_157 */
  99. >;
  100. };
  101. uart3_pins: pinmux_uart3_pins {
  102. pinctrl-single,pins = <
  103. OMAP3_CORE1_IOPAD(0x219e, PIN_INPUT | PIN_OFF_WAKEUPENABLE | MUX_MODE0) /* uart3_rx_irrx.uart3_rx_irrx */
  104. OMAP3_CORE1_IOPAD(0x21a0, PIN_OUTPUT | MUX_MODE0) /* uart3_tx_irtx.uart3_tx_irtx */
  105. >;
  106. };
  107. i2c3_pins: pinmux_i2c3_pins {
  108. pinctrl-single,pins = <
  109. OMAP3_CORE1_IOPAD(0x21c2, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c3_scl.i2c3_scl */
  110. OMAP3_CORE1_IOPAD(0x21c4, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c3_sda.i2c3_sda */
  111. >;
  112. };
  113. mcspi1_pins: pinmux_mcspi1_pins {
  114. pinctrl-single,pins = <
  115. OMAP3_CORE1_IOPAD(0x21c8, PIN_INPUT | MUX_MODE0) /* mcspi1_clk.mcspi1_clk */
  116. OMAP3_CORE1_IOPAD(0x21ca, PIN_OUTPUT | MUX_MODE0) /* mcspi1_simo.mcspi1_simo */
  117. OMAP3_CORE1_IOPAD(0x21cc, PIN_INPUT_PULLUP | MUX_MODE0) /* mcspi1_somi.mcspi1_somi */
  118. OMAP3_CORE1_IOPAD(0x21ce, PIN_OUTPUT | MUX_MODE0) /* mcspi1_cs0.mcspi1_cs0 */
  119. >;
  120. };
  121. mcspi3_pins: pinmux_mcspi3_pins {
  122. pinctrl-single,pins = <
  123. OMAP3_CORE1_IOPAD(0x25dc, PIN_OUTPUT | MUX_MODE1) /* etk_d0.mcspi3_simo gpio14 INPUT | MODE1 */
  124. OMAP3_CORE1_IOPAD(0x25de, PIN_INPUT_PULLUP | MUX_MODE1) /* etk_d1.mcspi3_somi gpio15 INPUT | MODE1 */
  125. OMAP3_CORE1_IOPAD(0x25e0, PIN_OUTPUT | MUX_MODE1) /* etk_d2.mcspi3_cs0 gpio16 INPUT | MODE1 */
  126. OMAP3_CORE1_IOPAD(0x25e2, PIN_INPUT | MUX_MODE1) /* etk_d3.mcspi3_clk gpio17 INPUT | MODE1 */
  127. >;
  128. };
  129. mcbsp3_pins: pinmux_mcbsp3_pins {
  130. pinctrl-single,pins = <
  131. OMAP3_CORE1_IOPAD(0x216c, PIN_OUTPUT | MUX_MODE0) /* mcbsp3_dx.uart2_cts */
  132. OMAP3_CORE1_IOPAD(0x216e, PIN_INPUT | MUX_MODE0) /* mcbsp3_dr.uart2_rts */
  133. OMAP3_CORE1_IOPAD(0x2170, PIN_INPUT | MUX_MODE0) /* mcbsp3_clk.uart2_tx */
  134. OMAP3_CORE1_IOPAD(0x2172, PIN_INPUT | MUX_MODE0) /* mcbsp3_fsx.uart2_rx */
  135. >;
  136. };
  137. };
  138. /* McBSP1: mux'ed with GPIO158 as clock for HA-DSP */
  139. &mcbsp1 {
  140. status = "disabled";
  141. };
  142. &mcbsp2 {
  143. status = "okay";
  144. };
  145. &i2c1 {
  146. clock-frequency = <2600000>;
  147. twl: twl@48 {
  148. reg = <0x48>;
  149. interrupts = <7>; /* SYS_NIRQ cascaded to intc */
  150. interrupt-parent = <&intc>;
  151. twl_audio: audio {
  152. compatible = "ti,twl4030-audio";
  153. codec {
  154. };
  155. };
  156. };
  157. };
  158. &i2c3 {
  159. clock-frequency = <100000>;
  160. pinctrl-names = "default";
  161. pinctrl-0 = <&i2c3_pins>;
  162. };
  163. &mcspi1 {
  164. pinctrl-names = "default";
  165. pinctrl-0 = <&mcspi1_pins>;
  166. spidev@0 {
  167. compatible = "spidev";
  168. spi-max-frequency = <48000000>;
  169. reg = <0>;
  170. spi-cpha;
  171. };
  172. };
  173. &mcspi3 {
  174. pinctrl-names = "default";
  175. pinctrl-0 = <&mcspi3_pins>;
  176. spidev@0 {
  177. compatible = "spidev";
  178. spi-max-frequency = <48000000>;
  179. reg = <0>;
  180. spi-cpha;
  181. };
  182. };
  183. #include "twl4030.dtsi"
  184. #include "twl4030_omap3.dtsi"
  185. &mmc1 {
  186. pinctrl-names = "default";
  187. pinctrl-0 = <&mmc1_pins>;
  188. vmmc-supply = <&vmmc1>;
  189. vmmc_aux-supply = <&vsim>;
  190. cd-gpios = <&twl_gpio 0 0>;
  191. bus-width = <8>;
  192. };
  193. // WiFi (Marvell 88W8686) on MMC2/SDIO
  194. &mmc2 {
  195. pinctrl-names = "default";
  196. pinctrl-0 = <&mmc2_pins>;
  197. vmmc-supply = <&mmc2_sdio_poweron>;
  198. non-removable;
  199. bus-width = <4>;
  200. cap-power-off-card;
  201. };
  202. &mmc3 {
  203. status = "disabled";
  204. };
  205. &usbhshost {
  206. port2-mode = "ehci-phy";
  207. };
  208. &usbhsehci {
  209. phys = <0 &hsusb2_phy>;
  210. };
  211. &twl_gpio {
  212. ti,use-leds;
  213. /* pullups: BIT(1) */
  214. ti,pullups = <0x000002>;
  215. /*
  216. * pulldowns:
  217. * BIT(2), BIT(6), BIT(7), BIT(8), BIT(13)
  218. * BIT(15), BIT(16), BIT(17)
  219. */
  220. ti,pulldowns = <0x03a1c4>;
  221. };
  222. &uart3 {
  223. pinctrl-names = "default";
  224. pinctrl-0 = <&uart3_pins>;
  225. };
  226. &mcbsp3 {
  227. status = "okay";
  228. pinctrl-names = "default";
  229. pinctrl-0 = <&mcbsp3_pins>;
  230. };
  231. &gpmc {
  232. ranges = <0 0 0x00000000 0x01000000>;
  233. nand@0,0 {
  234. reg = <0 0 0>; /* CS0, offset 0 */
  235. nand-bus-width = <16>;
  236. gpmc,device-width = <2>; /* GPMC_DEVWIDTH_16BIT */
  237. ti,nand-ecc-opt = "sw";
  238. gpmc,cs-on-ns = <0>;
  239. gpmc,cs-rd-off-ns = <36>;
  240. gpmc,cs-wr-off-ns = <36>;
  241. gpmc,adv-on-ns = <6>;
  242. gpmc,adv-rd-off-ns = <24>;
  243. gpmc,adv-wr-off-ns = <36>;
  244. gpmc,oe-on-ns = <6>;
  245. gpmc,oe-off-ns = <48>;
  246. gpmc,we-on-ns = <6>;
  247. gpmc,we-off-ns = <30>;
  248. gpmc,rd-cycle-ns = <72>;
  249. gpmc,wr-cycle-ns = <72>;
  250. gpmc,access-ns = <54>;
  251. gpmc,wr-access-ns = <30>;
  252. #address-cells = <1>;
  253. #size-cells = <1>;
  254. x-loader@0 {
  255. label = "X-Loader";
  256. reg = <0 0x80000>;
  257. };
  258. bootloaders@80000 {
  259. label = "U-Boot";
  260. reg = <0x80000 0x1e0000>;
  261. };
  262. bootloaders_env@260000 {
  263. label = "U-Boot Env";
  264. reg = <0x260000 0x20000>;
  265. };
  266. kernel@280000 {
  267. label = "Kernel";
  268. reg = <0x280000 0x400000>;
  269. };
  270. filesystem@680000 {
  271. label = "File System";
  272. reg = <0x680000 0xf980000>;
  273. };
  274. };
  275. };
  276. &usb_otg_hs {
  277. interface-type = <0>;
  278. usb-phy = <&usb2_phy>;
  279. phys = <&usb2_phy>;
  280. phy-names = "usb2-phy";
  281. mode = <3>;
  282. power = <50>;
  283. };
  284. &vaux2 {
  285. regulator-name = "vdd_ehci";
  286. regulator-min-microvolt = <1800000>;
  287. regulator-max-microvolt = <1800000>;
  288. regulator-always-on;
  289. };