omap36xx-clocks.dtsi 2.4 KB

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  1. /*
  2. * Device Tree Source for OMAP36xx clock data
  3. *
  4. * Copyright (C) 2013 Texas Instruments, Inc.
  5. *
  6. * This program is free software; you can redistribute it and/or modify
  7. * it under the terms of the GNU General Public License version 2 as
  8. * published by the Free Software Foundation.
  9. */
  10. &cm_clocks {
  11. dpll4_ck: dpll4_ck {
  12. #clock-cells = <0>;
  13. compatible = "ti,omap3-dpll-per-j-type-clock";
  14. clocks = <&sys_ck>, <&sys_ck>;
  15. reg = <0x0d00>, <0x0d20>, <0x0d44>, <0x0d30>;
  16. };
  17. dpll4_m5x2_ck: dpll4_m5x2_ck {
  18. #clock-cells = <0>;
  19. compatible = "ti,hsdiv-gate-clock";
  20. clocks = <&dpll4_m5x2_mul_ck>;
  21. ti,bit-shift = <0x1e>;
  22. reg = <0x0d00>;
  23. ti,set-rate-parent;
  24. ti,set-bit-to-disable;
  25. };
  26. dpll4_m2x2_ck: dpll4_m2x2_ck {
  27. #clock-cells = <0>;
  28. compatible = "ti,hsdiv-gate-clock";
  29. clocks = <&dpll4_m2x2_mul_ck>;
  30. ti,bit-shift = <0x1b>;
  31. reg = <0x0d00>;
  32. ti,set-bit-to-disable;
  33. };
  34. dpll3_m3x2_ck: dpll3_m3x2_ck {
  35. #clock-cells = <0>;
  36. compatible = "ti,hsdiv-gate-clock";
  37. clocks = <&dpll3_m3x2_mul_ck>;
  38. ti,bit-shift = <0xc>;
  39. reg = <0x0d00>;
  40. ti,set-bit-to-disable;
  41. };
  42. dpll4_m3x2_ck: dpll4_m3x2_ck {
  43. #clock-cells = <0>;
  44. compatible = "ti,hsdiv-gate-clock";
  45. clocks = <&dpll4_m3x2_mul_ck>;
  46. ti,bit-shift = <0x1c>;
  47. reg = <0x0d00>;
  48. ti,set-bit-to-disable;
  49. };
  50. dpll4_m6x2_ck: dpll4_m6x2_ck {
  51. #clock-cells = <0>;
  52. compatible = "ti,hsdiv-gate-clock";
  53. clocks = <&dpll4_m6x2_mul_ck>;
  54. ti,bit-shift = <0x1f>;
  55. reg = <0x0d00>;
  56. ti,set-bit-to-disable;
  57. };
  58. uart4_fck: uart4_fck {
  59. #clock-cells = <0>;
  60. compatible = "ti,wait-gate-clock";
  61. clocks = <&per_48m_fck>;
  62. reg = <0x1000>;
  63. ti,bit-shift = <18>;
  64. };
  65. };
  66. &dpll4_m2x2_mul_ck {
  67. clock-mult = <1>;
  68. };
  69. &dpll4_m3x2_mul_ck {
  70. clock-mult = <1>;
  71. };
  72. &dpll4_m4x2_mul_ck {
  73. ti,clock-mult = <1>;
  74. };
  75. &dpll4_m5x2_mul_ck {
  76. ti,clock-mult = <1>;
  77. };
  78. &dpll4_m6x2_mul_ck {
  79. clock-mult = <1>;
  80. };
  81. &cm_clockdomains {
  82. dpll4_clkdm: dpll4_clkdm {
  83. compatible = "ti,clockdomain";
  84. clocks = <&dpll4_ck>;
  85. };
  86. per_clkdm: per_clkdm {
  87. compatible = "ti,clockdomain";
  88. clocks = <&uart3_fck>, <&gpio6_dbck>, <&gpio5_dbck>,
  89. <&gpio4_dbck>, <&gpio3_dbck>, <&gpio2_dbck>,
  90. <&wdt3_fck>, <&gpio6_ick>, <&gpio5_ick>, <&gpio4_ick>,
  91. <&gpio3_ick>, <&gpio2_ick>, <&wdt3_ick>, <&uart3_ick>,
  92. <&uart4_ick>, <&gpt9_ick>, <&gpt8_ick>, <&gpt7_ick>,
  93. <&gpt6_ick>, <&gpt5_ick>, <&gpt4_ick>, <&gpt3_ick>,
  94. <&gpt2_ick>, <&mcbsp2_ick>, <&mcbsp3_ick>,
  95. <&mcbsp4_ick>, <&uart4_fck>;
  96. };
  97. };