qcom-ipq8064-ap148.dts 1.5 KB

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  1. #include "qcom-ipq8064-v1.0.dtsi"
  2. / {
  3. model = "Qualcomm IPQ8064/AP148";
  4. compatible = "qcom,ipq8064-ap148", "qcom,ipq8064";
  5. reserved-memory {
  6. #address-cells = <1>;
  7. #size-cells = <1>;
  8. ranges;
  9. rsvd@41200000 {
  10. reg = <0x41200000 0x300000>;
  11. no-map;
  12. };
  13. };
  14. soc {
  15. pinmux@800000 {
  16. i2c4_pins: i2c4_pinmux {
  17. pins = "gpio12", "gpio13";
  18. function = "gsbi4";
  19. bias-disable;
  20. };
  21. spi_pins: spi_pins {
  22. mux {
  23. pins = "gpio18", "gpio19", "gpio21";
  24. function = "gsbi5";
  25. drive-strength = <10>;
  26. bias-none;
  27. };
  28. };
  29. };
  30. gsbi@16300000 {
  31. qcom,mode = <GSBI_PROT_I2C_UART>;
  32. status = "ok";
  33. serial@16340000 {
  34. status = "ok";
  35. };
  36. i2c4: i2c@16380000 {
  37. status = "ok";
  38. clock-frequency = <200000>;
  39. pinctrl-0 = <&i2c4_pins>;
  40. pinctrl-names = "default";
  41. };
  42. };
  43. gsbi5: gsbi@1a200000 {
  44. qcom,mode = <GSBI_PROT_SPI>;
  45. status = "ok";
  46. spi4: spi@1a280000 {
  47. status = "ok";
  48. spi-max-frequency = <50000000>;
  49. pinctrl-0 = <&spi_pins>;
  50. pinctrl-names = "default";
  51. cs-gpios = <&qcom_pinmux 20 0>;
  52. flash: m25p80@0 {
  53. compatible = "s25fl256s1";
  54. #address-cells = <1>;
  55. #size-cells = <1>;
  56. spi-max-frequency = <50000000>;
  57. reg = <0>;
  58. partition@0 {
  59. label = "rootfs";
  60. reg = <0x0 0x1000000>;
  61. };
  62. partition@1 {
  63. label = "scratch";
  64. reg = <0x1000000 0x1000000>;
  65. };
  66. };
  67. };
  68. };
  69. sata-phy@1b400000 {
  70. status = "ok";
  71. };
  72. sata@29000000 {
  73. status = "ok";
  74. };
  75. };
  76. };