r8a73a4.dtsi 10 KB

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  1. /*
  2. * Device Tree Source for the r8a73a4 SoC
  3. *
  4. * Copyright (C) 2013 Renesas Solutions Corp.
  5. * Copyright (C) 2013 Magnus Damm
  6. *
  7. * This file is licensed under the terms of the GNU General Public License
  8. * version 2. This program is licensed "as is" without any warranty of any
  9. * kind, whether express or implied.
  10. */
  11. #include <dt-bindings/interrupt-controller/arm-gic.h>
  12. #include <dt-bindings/interrupt-controller/irq.h>
  13. / {
  14. compatible = "renesas,r8a73a4";
  15. interrupt-parent = <&gic>;
  16. #address-cells = <2>;
  17. #size-cells = <2>;
  18. cpus {
  19. #address-cells = <1>;
  20. #size-cells = <0>;
  21. cpu0: cpu@0 {
  22. device_type = "cpu";
  23. compatible = "arm,cortex-a15";
  24. reg = <0>;
  25. clock-frequency = <1500000000>;
  26. };
  27. };
  28. gic: interrupt-controller@f1001000 {
  29. compatible = "arm,cortex-a15-gic";
  30. #interrupt-cells = <3>;
  31. #address-cells = <0>;
  32. interrupt-controller;
  33. reg = <0 0xf1001000 0 0x1000>,
  34. <0 0xf1002000 0 0x1000>,
  35. <0 0xf1004000 0 0x2000>,
  36. <0 0xf1006000 0 0x2000>;
  37. interrupts = <1 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
  38. };
  39. timer {
  40. compatible = "arm,armv7-timer";
  41. interrupts = <1 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
  42. <1 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
  43. <1 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
  44. <1 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
  45. };
  46. irqc0: interrupt-controller@e61c0000 {
  47. compatible = "renesas,irqc-r8a73a4", "renesas,irqc";
  48. #interrupt-cells = <2>;
  49. interrupt-controller;
  50. reg = <0 0xe61c0000 0 0x200>;
  51. interrupts = <0 0 IRQ_TYPE_LEVEL_HIGH>,
  52. <0 1 IRQ_TYPE_LEVEL_HIGH>,
  53. <0 2 IRQ_TYPE_LEVEL_HIGH>,
  54. <0 3 IRQ_TYPE_LEVEL_HIGH>,
  55. <0 4 IRQ_TYPE_LEVEL_HIGH>,
  56. <0 5 IRQ_TYPE_LEVEL_HIGH>,
  57. <0 6 IRQ_TYPE_LEVEL_HIGH>,
  58. <0 7 IRQ_TYPE_LEVEL_HIGH>,
  59. <0 8 IRQ_TYPE_LEVEL_HIGH>,
  60. <0 9 IRQ_TYPE_LEVEL_HIGH>,
  61. <0 10 IRQ_TYPE_LEVEL_HIGH>,
  62. <0 11 IRQ_TYPE_LEVEL_HIGH>,
  63. <0 12 IRQ_TYPE_LEVEL_HIGH>,
  64. <0 13 IRQ_TYPE_LEVEL_HIGH>,
  65. <0 14 IRQ_TYPE_LEVEL_HIGH>,
  66. <0 15 IRQ_TYPE_LEVEL_HIGH>,
  67. <0 16 IRQ_TYPE_LEVEL_HIGH>,
  68. <0 17 IRQ_TYPE_LEVEL_HIGH>,
  69. <0 18 IRQ_TYPE_LEVEL_HIGH>,
  70. <0 19 IRQ_TYPE_LEVEL_HIGH>,
  71. <0 20 IRQ_TYPE_LEVEL_HIGH>,
  72. <0 21 IRQ_TYPE_LEVEL_HIGH>,
  73. <0 22 IRQ_TYPE_LEVEL_HIGH>,
  74. <0 23 IRQ_TYPE_LEVEL_HIGH>,
  75. <0 24 IRQ_TYPE_LEVEL_HIGH>,
  76. <0 25 IRQ_TYPE_LEVEL_HIGH>,
  77. <0 26 IRQ_TYPE_LEVEL_HIGH>,
  78. <0 27 IRQ_TYPE_LEVEL_HIGH>,
  79. <0 28 IRQ_TYPE_LEVEL_HIGH>,
  80. <0 29 IRQ_TYPE_LEVEL_HIGH>,
  81. <0 30 IRQ_TYPE_LEVEL_HIGH>,
  82. <0 31 IRQ_TYPE_LEVEL_HIGH>;
  83. };
  84. irqc1: interrupt-controller@e61c0200 {
  85. compatible = "renesas,irqc-r8a73a4", "renesas,irqc";
  86. #interrupt-cells = <2>;
  87. interrupt-controller;
  88. reg = <0 0xe61c0200 0 0x200>;
  89. interrupts = <0 32 IRQ_TYPE_LEVEL_HIGH>,
  90. <0 33 IRQ_TYPE_LEVEL_HIGH>,
  91. <0 34 IRQ_TYPE_LEVEL_HIGH>,
  92. <0 35 IRQ_TYPE_LEVEL_HIGH>,
  93. <0 36 IRQ_TYPE_LEVEL_HIGH>,
  94. <0 37 IRQ_TYPE_LEVEL_HIGH>,
  95. <0 38 IRQ_TYPE_LEVEL_HIGH>,
  96. <0 39 IRQ_TYPE_LEVEL_HIGH>,
  97. <0 40 IRQ_TYPE_LEVEL_HIGH>,
  98. <0 41 IRQ_TYPE_LEVEL_HIGH>,
  99. <0 42 IRQ_TYPE_LEVEL_HIGH>,
  100. <0 43 IRQ_TYPE_LEVEL_HIGH>,
  101. <0 44 IRQ_TYPE_LEVEL_HIGH>,
  102. <0 45 IRQ_TYPE_LEVEL_HIGH>,
  103. <0 46 IRQ_TYPE_LEVEL_HIGH>,
  104. <0 47 IRQ_TYPE_LEVEL_HIGH>,
  105. <0 48 IRQ_TYPE_LEVEL_HIGH>,
  106. <0 49 IRQ_TYPE_LEVEL_HIGH>,
  107. <0 50 IRQ_TYPE_LEVEL_HIGH>,
  108. <0 51 IRQ_TYPE_LEVEL_HIGH>,
  109. <0 52 IRQ_TYPE_LEVEL_HIGH>,
  110. <0 53 IRQ_TYPE_LEVEL_HIGH>,
  111. <0 54 IRQ_TYPE_LEVEL_HIGH>,
  112. <0 55 IRQ_TYPE_LEVEL_HIGH>,
  113. <0 56 IRQ_TYPE_LEVEL_HIGH>,
  114. <0 57 IRQ_TYPE_LEVEL_HIGH>;
  115. };
  116. dmac: dma-multiplexer@0 {
  117. compatible = "renesas,shdma-mux";
  118. #dma-cells = <1>;
  119. dma-channels = <20>;
  120. dma-requests = <256>;
  121. #address-cells = <2>;
  122. #size-cells = <2>;
  123. ranges;
  124. dma0: dma-controller@e6700020 {
  125. compatible = "renesas,shdma-r8a73a4";
  126. reg = <0 0xe6700020 0 0x89e0>;
  127. interrupts = <0 220 IRQ_TYPE_LEVEL_HIGH
  128. 0 200 IRQ_TYPE_LEVEL_HIGH
  129. 0 201 IRQ_TYPE_LEVEL_HIGH
  130. 0 202 IRQ_TYPE_LEVEL_HIGH
  131. 0 203 IRQ_TYPE_LEVEL_HIGH
  132. 0 204 IRQ_TYPE_LEVEL_HIGH
  133. 0 205 IRQ_TYPE_LEVEL_HIGH
  134. 0 206 IRQ_TYPE_LEVEL_HIGH
  135. 0 207 IRQ_TYPE_LEVEL_HIGH
  136. 0 208 IRQ_TYPE_LEVEL_HIGH
  137. 0 209 IRQ_TYPE_LEVEL_HIGH
  138. 0 210 IRQ_TYPE_LEVEL_HIGH
  139. 0 211 IRQ_TYPE_LEVEL_HIGH
  140. 0 212 IRQ_TYPE_LEVEL_HIGH
  141. 0 213 IRQ_TYPE_LEVEL_HIGH
  142. 0 214 IRQ_TYPE_LEVEL_HIGH
  143. 0 215 IRQ_TYPE_LEVEL_HIGH
  144. 0 216 IRQ_TYPE_LEVEL_HIGH
  145. 0 217 IRQ_TYPE_LEVEL_HIGH
  146. 0 218 IRQ_TYPE_LEVEL_HIGH
  147. 0 219 IRQ_TYPE_LEVEL_HIGH>;
  148. interrupt-names = "error",
  149. "ch0", "ch1", "ch2", "ch3",
  150. "ch4", "ch5", "ch6", "ch7",
  151. "ch8", "ch9", "ch10", "ch11",
  152. "ch12", "ch13", "ch14", "ch15",
  153. "ch16", "ch17", "ch18", "ch19";
  154. };
  155. };
  156. thermal@e61f0000 {
  157. compatible = "renesas,thermal-r8a73a4", "renesas,rcar-thermal";
  158. reg = <0 0xe61f0000 0 0x14>, <0 0xe61f0100 0 0x38>,
  159. <0 0xe61f0200 0 0x38>, <0 0xe61f0300 0 0x38>;
  160. interrupts = <0 69 IRQ_TYPE_LEVEL_HIGH>;
  161. };
  162. i2c0: i2c@e6500000 {
  163. #address-cells = <1>;
  164. #size-cells = <0>;
  165. compatible = "renesas,rmobile-iic";
  166. reg = <0 0xe6500000 0 0x428>;
  167. interrupts = <0 174 IRQ_TYPE_LEVEL_HIGH>;
  168. status = "disabled";
  169. };
  170. i2c1: i2c@e6510000 {
  171. #address-cells = <1>;
  172. #size-cells = <0>;
  173. compatible = "renesas,rmobile-iic";
  174. reg = <0 0xe6510000 0 0x428>;
  175. interrupts = <0 175 IRQ_TYPE_LEVEL_HIGH>;
  176. status = "disabled";
  177. };
  178. i2c2: i2c@e6520000 {
  179. #address-cells = <1>;
  180. #size-cells = <0>;
  181. compatible = "renesas,rmobile-iic";
  182. reg = <0 0xe6520000 0 0x428>;
  183. interrupts = <0 176 IRQ_TYPE_LEVEL_HIGH>;
  184. status = "disabled";
  185. };
  186. i2c3: i2c@e6530000 {
  187. #address-cells = <1>;
  188. #size-cells = <0>;
  189. compatible = "renesas,rmobile-iic";
  190. reg = <0 0xe6530000 0 0x428>;
  191. interrupts = <0 177 IRQ_TYPE_LEVEL_HIGH>;
  192. status = "disabled";
  193. };
  194. i2c4: i2c@e6540000 {
  195. #address-cells = <1>;
  196. #size-cells = <0>;
  197. compatible = "renesas,rmobile-iic";
  198. reg = <0 0xe6540000 0 0x428>;
  199. interrupts = <0 178 IRQ_TYPE_LEVEL_HIGH>;
  200. status = "disabled";
  201. };
  202. i2c5: i2c@e60b0000 {
  203. #address-cells = <1>;
  204. #size-cells = <0>;
  205. compatible = "renesas,rmobile-iic";
  206. reg = <0 0xe60b0000 0 0x428>;
  207. interrupts = <0 179 IRQ_TYPE_LEVEL_HIGH>;
  208. status = "disabled";
  209. };
  210. i2c6: i2c@e6550000 {
  211. #address-cells = <1>;
  212. #size-cells = <0>;
  213. compatible = "renesas,rmobile-iic";
  214. reg = <0 0xe6550000 0 0x428>;
  215. interrupts = <0 184 IRQ_TYPE_LEVEL_HIGH>;
  216. status = "disabled";
  217. };
  218. i2c7: i2c@e6560000 {
  219. #address-cells = <1>;
  220. #size-cells = <0>;
  221. compatible = "renesas,rmobile-iic";
  222. reg = <0 0xe6560000 0 0x428>;
  223. interrupts = <0 185 IRQ_TYPE_LEVEL_HIGH>;
  224. status = "disabled";
  225. };
  226. i2c8: i2c@e6570000 {
  227. #address-cells = <1>;
  228. #size-cells = <0>;
  229. compatible = "renesas,rmobile-iic";
  230. reg = <0 0xe6570000 0 0x428>;
  231. interrupts = <0 173 IRQ_TYPE_LEVEL_HIGH>;
  232. status = "disabled";
  233. };
  234. scifa0: serial@e6c40000 {
  235. compatible = "renesas,scifa-r8a73a4", "renesas,scifa";
  236. reg = <0 0xe6c40000 0 0x100>;
  237. interrupts = <0 144 IRQ_TYPE_LEVEL_HIGH>;
  238. status = "disabled";
  239. };
  240. scifa1: serial@e6c50000 {
  241. compatible = "renesas,scifa-r8a73a4", "renesas,scifa";
  242. reg = <0 0xe6c50000 0 0x100>;
  243. interrupts = <0 145 IRQ_TYPE_LEVEL_HIGH>;
  244. status = "disabled";
  245. };
  246. scifb2: serial@e6c20000 {
  247. compatible = "renesas,scifb-r8a73a4", "renesas,scifb";
  248. reg = <0 0xe6c20000 0 0x100>;
  249. interrupts = <0 148 IRQ_TYPE_LEVEL_HIGH>;
  250. status = "disabled";
  251. };
  252. scifb3: serial@e6c30000 {
  253. compatible = "renesas,scifb-r8a73a4", "renesas,scifb";
  254. reg = <0 0xe6c30000 0 0x100>;
  255. interrupts = <0 149 IRQ_TYPE_LEVEL_HIGH>;
  256. status = "disabled";
  257. };
  258. scifb4: serial@e6ce0000 {
  259. compatible = "renesas,scifb-r8a73a4", "renesas,scifb";
  260. reg = <0 0xe6ce0000 0 0x100>;
  261. interrupts = <0 150 IRQ_TYPE_LEVEL_HIGH>;
  262. status = "disabled";
  263. };
  264. scifb5: serial@e6cf0000 {
  265. compatible = "renesas,scifb-r8a73a4", "renesas,scifb";
  266. reg = <0 0xe6cf0000 0 0x100>;
  267. interrupts = <0 151 IRQ_TYPE_LEVEL_HIGH>;
  268. status = "disabled";
  269. };
  270. mmcif0: mmc@ee200000 {
  271. compatible = "renesas,sh-mmcif";
  272. reg = <0 0xee200000 0 0x80>;
  273. interrupts = <0 169 IRQ_TYPE_LEVEL_HIGH>;
  274. reg-io-width = <4>;
  275. status = "disabled";
  276. };
  277. mmcif1: mmc@ee220000 {
  278. compatible = "renesas,sh-mmcif";
  279. reg = <0 0xee220000 0 0x80>;
  280. interrupts = <0 170 IRQ_TYPE_LEVEL_HIGH>;
  281. reg-io-width = <4>;
  282. status = "disabled";
  283. };
  284. pfc: pfc@e6050000 {
  285. compatible = "renesas,pfc-r8a73a4";
  286. reg = <0 0xe6050000 0 0x9000>;
  287. gpio-controller;
  288. #gpio-cells = <2>;
  289. interrupts-extended =
  290. <&irqc0 0 0>, <&irqc0 1 0>, <&irqc0 2 0>, <&irqc0 3 0>,
  291. <&irqc0 4 0>, <&irqc0 5 0>, <&irqc0 6 0>, <&irqc0 7 0>,
  292. <&irqc0 8 0>, <&irqc0 9 0>, <&irqc0 10 0>, <&irqc0 11 0>,
  293. <&irqc0 12 0>, <&irqc0 13 0>, <&irqc0 14 0>, <&irqc0 15 0>,
  294. <&irqc0 16 0>, <&irqc0 17 0>, <&irqc0 18 0>, <&irqc0 19 0>,
  295. <&irqc0 20 0>, <&irqc0 21 0>, <&irqc0 22 0>, <&irqc0 23 0>,
  296. <&irqc0 24 0>, <&irqc0 25 0>, <&irqc0 26 0>, <&irqc0 27 0>,
  297. <&irqc0 28 0>, <&irqc0 29 0>, <&irqc0 30 0>, <&irqc0 31 0>,
  298. <&irqc1 0 0>, <&irqc1 1 0>, <&irqc1 2 0>, <&irqc1 3 0>,
  299. <&irqc1 4 0>, <&irqc1 5 0>, <&irqc1 6 0>, <&irqc1 7 0>,
  300. <&irqc1 8 0>, <&irqc1 9 0>, <&irqc1 10 0>, <&irqc1 11 0>,
  301. <&irqc1 12 0>, <&irqc1 13 0>, <&irqc1 14 0>, <&irqc1 15 0>,
  302. <&irqc1 16 0>, <&irqc1 17 0>, <&irqc1 18 0>, <&irqc1 19 0>,
  303. <&irqc1 20 0>, <&irqc1 21 0>, <&irqc1 22 0>, <&irqc1 23 0>,
  304. <&irqc1 24 0>, <&irqc1 25 0>;
  305. };
  306. sdhi0: sd@ee100000 {
  307. compatible = "renesas,sdhi-r8a73a4";
  308. reg = <0 0xee100000 0 0x100>;
  309. interrupts = <0 165 IRQ_TYPE_LEVEL_HIGH>;
  310. cap-sd-highspeed;
  311. status = "disabled";
  312. };
  313. sdhi1: sd@ee120000 {
  314. compatible = "renesas,sdhi-r8a73a4";
  315. reg = <0 0xee120000 0 0x100>;
  316. interrupts = <0 166 IRQ_TYPE_LEVEL_HIGH>;
  317. cap-sd-highspeed;
  318. status = "disabled";
  319. };
  320. sdhi2: sd@ee140000 {
  321. compatible = "renesas,sdhi-r8a73a4";
  322. reg = <0 0xee140000 0 0x100>;
  323. interrupts = <0 167 IRQ_TYPE_LEVEL_HIGH>;
  324. cap-sd-highspeed;
  325. status = "disabled";
  326. };
  327. };