r8a7778.dtsi 6.2 KB

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  1. /*
  2. * Device Tree Source for Renesas r8a7778
  3. *
  4. * Copyright (C) 2013 Renesas Solutions Corp.
  5. * Copyright (C) 2013 Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
  6. *
  7. * based on r8a7779
  8. *
  9. * Copyright (C) 2013 Renesas Solutions Corp.
  10. * Copyright (C) 2013 Simon Horman
  11. *
  12. * This file is licensed under the terms of the GNU General Public License
  13. * version 2. This program is licensed "as is" without any warranty of any
  14. * kind, whether express or implied.
  15. */
  16. /include/ "skeleton.dtsi"
  17. #include <dt-bindings/interrupt-controller/irq.h>
  18. / {
  19. compatible = "renesas,r8a7778";
  20. interrupt-parent = <&gic>;
  21. cpus {
  22. #address-cells = <1>;
  23. #size-cells = <0>;
  24. cpu@0 {
  25. device_type = "cpu";
  26. compatible = "arm,cortex-a9";
  27. reg = <0>;
  28. clock-frequency = <800000000>;
  29. };
  30. };
  31. aliases {
  32. spi0 = &hspi0;
  33. spi1 = &hspi1;
  34. spi2 = &hspi2;
  35. };
  36. gic: interrupt-controller@fe438000 {
  37. compatible = "arm,cortex-a9-gic";
  38. #interrupt-cells = <3>;
  39. interrupt-controller;
  40. reg = <0xfe438000 0x1000>,
  41. <0xfe430000 0x100>;
  42. };
  43. /* irqpin: IRQ0 - IRQ3 */
  44. irqpin: irqpin@fe78001c {
  45. compatible = "renesas,intc-irqpin-r8a7778", "renesas,intc-irqpin";
  46. #interrupt-cells = <2>;
  47. interrupt-controller;
  48. status = "disabled"; /* default off */
  49. reg = <0xfe78001c 4>,
  50. <0xfe780010 4>,
  51. <0xfe780024 4>,
  52. <0xfe780044 4>,
  53. <0xfe780064 4>;
  54. interrupts = <0 27 IRQ_TYPE_LEVEL_HIGH
  55. 0 28 IRQ_TYPE_LEVEL_HIGH
  56. 0 29 IRQ_TYPE_LEVEL_HIGH
  57. 0 30 IRQ_TYPE_LEVEL_HIGH>;
  58. sense-bitfield-width = <2>;
  59. };
  60. gpio0: gpio@ffc40000 {
  61. compatible = "renesas,gpio-r8a7778", "renesas,gpio-rcar";
  62. reg = <0xffc40000 0x2c>;
  63. interrupts = <0 103 IRQ_TYPE_LEVEL_HIGH>;
  64. #gpio-cells = <2>;
  65. gpio-controller;
  66. gpio-ranges = <&pfc 0 0 32>;
  67. #interrupt-cells = <2>;
  68. interrupt-controller;
  69. };
  70. gpio1: gpio@ffc41000 {
  71. compatible = "renesas,gpio-r8a7778", "renesas,gpio-rcar";
  72. reg = <0xffc41000 0x2c>;
  73. interrupts = <0 103 IRQ_TYPE_LEVEL_HIGH>;
  74. #gpio-cells = <2>;
  75. gpio-controller;
  76. gpio-ranges = <&pfc 0 32 32>;
  77. #interrupt-cells = <2>;
  78. interrupt-controller;
  79. };
  80. gpio2: gpio@ffc42000 {
  81. compatible = "renesas,gpio-r8a7778", "renesas,gpio-rcar";
  82. reg = <0xffc42000 0x2c>;
  83. interrupts = <0 103 IRQ_TYPE_LEVEL_HIGH>;
  84. #gpio-cells = <2>;
  85. gpio-controller;
  86. gpio-ranges = <&pfc 0 64 32>;
  87. #interrupt-cells = <2>;
  88. interrupt-controller;
  89. };
  90. gpio3: gpio@ffc43000 {
  91. compatible = "renesas,gpio-r8a7778", "renesas,gpio-rcar";
  92. reg = <0xffc43000 0x2c>;
  93. interrupts = <0 103 IRQ_TYPE_LEVEL_HIGH>;
  94. #gpio-cells = <2>;
  95. gpio-controller;
  96. gpio-ranges = <&pfc 0 96 32>;
  97. #interrupt-cells = <2>;
  98. interrupt-controller;
  99. };
  100. gpio4: gpio@ffc44000 {
  101. compatible = "renesas,gpio-r8a7778", "renesas,gpio-rcar";
  102. reg = <0xffc44000 0x2c>;
  103. interrupts = <0 103 IRQ_TYPE_LEVEL_HIGH>;
  104. #gpio-cells = <2>;
  105. gpio-controller;
  106. gpio-ranges = <&pfc 0 128 27>;
  107. #interrupt-cells = <2>;
  108. interrupt-controller;
  109. };
  110. pfc: pfc@fffc0000 {
  111. compatible = "renesas,pfc-r8a7778";
  112. reg = <0xfffc0000 0x118>;
  113. };
  114. i2c0: i2c@ffc70000 {
  115. #address-cells = <1>;
  116. #size-cells = <0>;
  117. compatible = "renesas,i2c-r8a7778";
  118. reg = <0xffc70000 0x1000>;
  119. interrupts = <0 67 IRQ_TYPE_LEVEL_HIGH>;
  120. status = "disabled";
  121. };
  122. i2c1: i2c@ffc71000 {
  123. #address-cells = <1>;
  124. #size-cells = <0>;
  125. compatible = "renesas,i2c-r8a7778";
  126. reg = <0xffc71000 0x1000>;
  127. interrupts = <0 78 IRQ_TYPE_LEVEL_HIGH>;
  128. status = "disabled";
  129. };
  130. i2c2: i2c@ffc72000 {
  131. #address-cells = <1>;
  132. #size-cells = <0>;
  133. compatible = "renesas,i2c-r8a7778";
  134. reg = <0xffc72000 0x1000>;
  135. interrupts = <0 76 IRQ_TYPE_LEVEL_HIGH>;
  136. status = "disabled";
  137. };
  138. i2c3: i2c@ffc73000 {
  139. #address-cells = <1>;
  140. #size-cells = <0>;
  141. compatible = "renesas,i2c-r8a7778";
  142. reg = <0xffc73000 0x1000>;
  143. interrupts = <0 77 IRQ_TYPE_LEVEL_HIGH>;
  144. status = "disabled";
  145. };
  146. scif0: serial@ffe40000 {
  147. compatible = "renesas,scif-r8a7778", "renesas,scif";
  148. reg = <0xffe40000 0x100>;
  149. interrupts = <0 70 IRQ_TYPE_LEVEL_HIGH>;
  150. status = "disabled";
  151. };
  152. scif1: serial@ffe41000 {
  153. compatible = "renesas,scif-r8a7778", "renesas,scif";
  154. reg = <0xffe41000 0x100>;
  155. interrupts = <0 71 IRQ_TYPE_LEVEL_HIGH>;
  156. status = "disabled";
  157. };
  158. scif2: serial@ffe42000 {
  159. compatible = "renesas,scif-r8a7778", "renesas,scif";
  160. reg = <0xffe42000 0x100>;
  161. interrupts = <0 72 IRQ_TYPE_LEVEL_HIGH>;
  162. status = "disabled";
  163. };
  164. scif3: serial@ffe43000 {
  165. compatible = "renesas,scif-r8a7778", "renesas,scif";
  166. reg = <0xffe43000 0x100>;
  167. interrupts = <0 73 IRQ_TYPE_LEVEL_HIGH>;
  168. status = "disabled";
  169. };
  170. scif4: serial@ffe44000 {
  171. compatible = "renesas,scif-r8a7778", "renesas,scif";
  172. reg = <0xffe44000 0x100>;
  173. interrupts = <0 74 IRQ_TYPE_LEVEL_HIGH>;
  174. status = "disabled";
  175. };
  176. scif5: serial@ffe45000 {
  177. compatible = "renesas,scif-r8a7778", "renesas,scif";
  178. reg = <0xffe45000 0x100>;
  179. interrupts = <0 75 IRQ_TYPE_LEVEL_HIGH>;
  180. status = "disabled";
  181. };
  182. mmcif: mmc@ffe4e000 {
  183. compatible = "renesas,sh-mmcif";
  184. reg = <0xffe4e000 0x100>;
  185. interrupts = <0 61 IRQ_TYPE_LEVEL_HIGH>;
  186. status = "disabled";
  187. };
  188. sdhi0: sd@ffe4c000 {
  189. compatible = "renesas,sdhi-r8a7778";
  190. reg = <0xffe4c000 0x100>;
  191. interrupts = <0 87 IRQ_TYPE_LEVEL_HIGH>;
  192. cap-sd-highspeed;
  193. cap-sdio-irq;
  194. status = "disabled";
  195. };
  196. sdhi1: sd@ffe4d000 {
  197. compatible = "renesas,sdhi-r8a7778";
  198. reg = <0xffe4d000 0x100>;
  199. interrupts = <0 88 IRQ_TYPE_LEVEL_HIGH>;
  200. cap-sd-highspeed;
  201. cap-sdio-irq;
  202. status = "disabled";
  203. };
  204. sdhi2: sd@ffe4f000 {
  205. compatible = "renesas,sdhi-r8a7778";
  206. reg = <0xffe4f000 0x100>;
  207. interrupts = <0 86 IRQ_TYPE_LEVEL_HIGH>;
  208. cap-sd-highspeed;
  209. cap-sdio-irq;
  210. status = "disabled";
  211. };
  212. hspi0: spi@fffc7000 {
  213. compatible = "renesas,hspi-r8a7778", "renesas,hspi";
  214. reg = <0xfffc7000 0x18>;
  215. interrupts = <0 63 IRQ_TYPE_LEVEL_HIGH>;
  216. #address-cells = <1>;
  217. #size-cells = <0>;
  218. status = "disabled";
  219. };
  220. hspi1: spi@fffc8000 {
  221. compatible = "renesas,hspi-r8a7778", "renesas,hspi";
  222. reg = <0xfffc8000 0x18>;
  223. interrupts = <0 84 IRQ_TYPE_LEVEL_HIGH>;
  224. #address-cells = <1>;
  225. #size-cells = <0>;
  226. status = "disabled";
  227. };
  228. hspi2: spi@fffc6000 {
  229. compatible = "renesas,hspi-r8a7778", "renesas,hspi";
  230. reg = <0xfffc6000 0x18>;
  231. interrupts = <0 85 IRQ_TYPE_LEVEL_HIGH>;
  232. #address-cells = <1>;
  233. #size-cells = <0>;
  234. status = "disabled";
  235. };
  236. };