r8a7790-lager.dts 7.6 KB

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  1. /*
  2. * Device Tree Source for the Lager board
  3. *
  4. * Copyright (C) 2013-2014 Renesas Solutions Corp.
  5. * Copyright (C) 2014 Cogent Embedded, Inc.
  6. *
  7. * This file is licensed under the terms of the GNU General Public License
  8. * version 2. This program is licensed "as is" without any warranty of any
  9. * kind, whether express or implied.
  10. */
  11. /dts-v1/;
  12. #include "r8a7790.dtsi"
  13. #include <dt-bindings/gpio/gpio.h>
  14. #include <dt-bindings/input/input.h>
  15. / {
  16. model = "Lager";
  17. compatible = "renesas,lager", "renesas,r8a7790";
  18. aliases {
  19. serial6 = &scif0;
  20. serial7 = &scif1;
  21. };
  22. chosen {
  23. bootargs = "console=ttySC6,115200 ignore_loglevel rw root=/dev/nfs ip=dhcp";
  24. };
  25. memory@40000000 {
  26. device_type = "memory";
  27. reg = <0 0x40000000 0 0x40000000>;
  28. };
  29. memory@140000000 {
  30. device_type = "memory";
  31. reg = <1 0x40000000 0 0xc0000000>;
  32. };
  33. lbsc {
  34. #address-cells = <1>;
  35. #size-cells = <1>;
  36. };
  37. gpio_keys {
  38. compatible = "gpio-keys";
  39. button@1 {
  40. linux,code = <KEY_1>;
  41. label = "SW2-1";
  42. gpio-key,wakeup;
  43. debounce-interval = <20>;
  44. gpios = <&gpio1 14 GPIO_ACTIVE_LOW>;
  45. };
  46. button@2 {
  47. linux,code = <KEY_2>;
  48. label = "SW2-2";
  49. gpio-key,wakeup;
  50. debounce-interval = <20>;
  51. gpios = <&gpio1 24 GPIO_ACTIVE_LOW>;
  52. };
  53. button@3 {
  54. linux,code = <KEY_3>;
  55. label = "SW2-3";
  56. gpio-key,wakeup;
  57. debounce-interval = <20>;
  58. gpios = <&gpio1 26 GPIO_ACTIVE_LOW>;
  59. };
  60. button@4 {
  61. linux,code = <KEY_4>;
  62. label = "SW2-4";
  63. gpio-key,wakeup;
  64. debounce-interval = <20>;
  65. gpios = <&gpio1 28 GPIO_ACTIVE_LOW>;
  66. };
  67. };
  68. leds {
  69. compatible = "gpio-leds";
  70. led6 {
  71. gpios = <&gpio4 22 GPIO_ACTIVE_HIGH>;
  72. };
  73. led7 {
  74. gpios = <&gpio4 23 GPIO_ACTIVE_HIGH>;
  75. };
  76. led8 {
  77. gpios = <&gpio5 17 GPIO_ACTIVE_HIGH>;
  78. };
  79. };
  80. fixedregulator3v3: fixedregulator@0 {
  81. compatible = "regulator-fixed";
  82. regulator-name = "fixed-3.3V";
  83. regulator-min-microvolt = <3300000>;
  84. regulator-max-microvolt = <3300000>;
  85. regulator-boot-on;
  86. regulator-always-on;
  87. };
  88. vcc_sdhi0: regulator@1 {
  89. compatible = "regulator-fixed";
  90. regulator-name = "SDHI0 Vcc";
  91. regulator-min-microvolt = <3300000>;
  92. regulator-max-microvolt = <3300000>;
  93. gpio = <&gpio5 24 GPIO_ACTIVE_HIGH>;
  94. enable-active-high;
  95. };
  96. vccq_sdhi0: regulator@2 {
  97. compatible = "regulator-gpio";
  98. regulator-name = "SDHI0 VccQ";
  99. regulator-min-microvolt = <1800000>;
  100. regulator-max-microvolt = <3300000>;
  101. gpios = <&gpio5 29 GPIO_ACTIVE_HIGH>;
  102. gpios-states = <1>;
  103. states = <3300000 1
  104. 1800000 0>;
  105. };
  106. vcc_sdhi2: regulator@3 {
  107. compatible = "regulator-fixed";
  108. regulator-name = "SDHI2 Vcc";
  109. regulator-min-microvolt = <3300000>;
  110. regulator-max-microvolt = <3300000>;
  111. gpio = <&gpio5 25 GPIO_ACTIVE_HIGH>;
  112. enable-active-high;
  113. };
  114. vccq_sdhi2: regulator@4 {
  115. compatible = "regulator-gpio";
  116. regulator-name = "SDHI2 VccQ";
  117. regulator-min-microvolt = <1800000>;
  118. regulator-max-microvolt = <3300000>;
  119. gpios = <&gpio5 30 GPIO_ACTIVE_HIGH>;
  120. gpios-states = <1>;
  121. states = <3300000 1
  122. 1800000 0>;
  123. };
  124. };
  125. &extal_clk {
  126. clock-frequency = <20000000>;
  127. };
  128. &pfc {
  129. pinctrl-0 = <&du_pins>;
  130. pinctrl-names = "default";
  131. du_pins: du {
  132. renesas,groups = "du_rgb666", "du_sync_1", "du_clk_out_0";
  133. renesas,function = "du";
  134. };
  135. scif0_pins: serial0 {
  136. renesas,groups = "scif0_data";
  137. renesas,function = "scif0";
  138. };
  139. ether_pins: ether {
  140. renesas,groups = "eth_link", "eth_mdio", "eth_rmii";
  141. renesas,function = "eth";
  142. };
  143. phy1_pins: phy1 {
  144. renesas,groups = "intc_irq0";
  145. renesas,function = "intc";
  146. };
  147. scif1_pins: serial1 {
  148. renesas,groups = "scif1_data";
  149. renesas,function = "scif1";
  150. };
  151. sdhi0_pins: sd0 {
  152. renesas,groups = "sdhi0_data4", "sdhi0_ctrl";
  153. renesas,function = "sdhi0";
  154. };
  155. sdhi2_pins: sd2 {
  156. renesas,groups = "sdhi2_data4", "sdhi2_ctrl";
  157. renesas,function = "sdhi2";
  158. };
  159. mmc1_pins: mmc1 {
  160. renesas,groups = "mmc1_data8", "mmc1_ctrl";
  161. renesas,function = "mmc1";
  162. };
  163. qspi_pins: spi0 {
  164. renesas,groups = "qspi_ctrl", "qspi_data4";
  165. renesas,function = "qspi";
  166. };
  167. msiof1_pins: spi2 {
  168. renesas,groups = "msiof1_clk", "msiof1_sync", "msiof1_rx",
  169. "msiof1_tx";
  170. renesas,function = "msiof1";
  171. };
  172. iic1_pins: iic1 {
  173. renesas,groups = "iic1";
  174. renesas,function = "iic1";
  175. };
  176. iic2_pins: iic2 {
  177. renesas,groups = "iic2";
  178. renesas,function = "iic2";
  179. };
  180. iic3_pins: iic3 {
  181. renesas,groups = "iic3";
  182. renesas,function = "iic3";
  183. };
  184. usb0_pins: usb0 {
  185. renesas,groups = "usb0";
  186. renesas,function = "usb0";
  187. };
  188. usb1_pins: usb1 {
  189. renesas,groups = "usb1";
  190. renesas,function = "usb1";
  191. };
  192. usb2_pins: usb2 {
  193. renesas,groups = "usb2";
  194. renesas,function = "usb2";
  195. };
  196. vin1_pins: vin {
  197. renesas,groups = "vin1_data8", "vin1_clk";
  198. renesas,function = "vin1";
  199. };
  200. };
  201. &ether {
  202. pinctrl-0 = <&ether_pins &phy1_pins>;
  203. pinctrl-names = "default";
  204. phy-handle = <&phy1>;
  205. renesas,ether-link-active-low;
  206. status = "ok";
  207. phy1: ethernet-phy@1 {
  208. reg = <1>;
  209. interrupt-parent = <&irqc0>;
  210. interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
  211. micrel,led-mode = <1>;
  212. };
  213. };
  214. &cmt0 {
  215. status = "ok";
  216. };
  217. &mmcif1 {
  218. pinctrl-0 = <&mmc1_pins>;
  219. pinctrl-names = "default";
  220. vmmc-supply = <&fixedregulator3v3>;
  221. bus-width = <8>;
  222. non-removable;
  223. status = "okay";
  224. };
  225. &sata1 {
  226. status = "okay";
  227. };
  228. &qspi {
  229. pinctrl-0 = <&qspi_pins>;
  230. pinctrl-names = "default";
  231. status = "okay";
  232. flash: flash@0 {
  233. #address-cells = <1>;
  234. #size-cells = <1>;
  235. compatible = "spansion,s25fl512s";
  236. reg = <0>;
  237. spi-max-frequency = <30000000>;
  238. spi-tx-bus-width = <4>;
  239. spi-rx-bus-width = <4>;
  240. m25p,fast-read;
  241. partition@0 {
  242. label = "loader";
  243. reg = <0x00000000 0x00040000>;
  244. read-only;
  245. };
  246. partition@40000 {
  247. label = "user";
  248. reg = <0x00040000 0x00400000>;
  249. read-only;
  250. };
  251. partition@440000 {
  252. label = "flash";
  253. reg = <0x00440000 0x03bc0000>;
  254. };
  255. };
  256. };
  257. &scif0 {
  258. pinctrl-0 = <&scif0_pins>;
  259. pinctrl-names = "default";
  260. status = "okay";
  261. };
  262. &scif1 {
  263. pinctrl-0 = <&scif1_pins>;
  264. pinctrl-names = "default";
  265. status = "okay";
  266. };
  267. &msiof1 {
  268. pinctrl-0 = <&msiof1_pins>;
  269. pinctrl-names = "default";
  270. status = "okay";
  271. pmic: pmic@0 {
  272. compatible = "renesas,r2a11302ft";
  273. reg = <0>;
  274. spi-max-frequency = <6000000>;
  275. spi-cpol;
  276. spi-cpha;
  277. };
  278. };
  279. &sdhi0 {
  280. pinctrl-0 = <&sdhi0_pins>;
  281. pinctrl-names = "default";
  282. vmmc-supply = <&vcc_sdhi0>;
  283. vqmmc-supply = <&vccq_sdhi0>;
  284. cd-gpios = <&gpio3 6 GPIO_ACTIVE_LOW>;
  285. status = "okay";
  286. };
  287. &sdhi2 {
  288. pinctrl-0 = <&sdhi2_pins>;
  289. pinctrl-names = "default";
  290. vmmc-supply = <&vcc_sdhi2>;
  291. vqmmc-supply = <&vccq_sdhi2>;
  292. cd-gpios = <&gpio3 22 GPIO_ACTIVE_LOW>;
  293. status = "okay";
  294. };
  295. &cpu0 {
  296. cpu0-supply = <&vdd_dvfs>;
  297. };
  298. &iic0 {
  299. status = "ok";
  300. };
  301. &iic1 {
  302. status = "ok";
  303. pinctrl-0 = <&iic1_pins>;
  304. pinctrl-names = "default";
  305. };
  306. &iic2 {
  307. status = "ok";
  308. pinctrl-0 = <&iic2_pins>;
  309. pinctrl-names = "default";
  310. composite-in@20 {
  311. compatible = "adi,adv7180";
  312. reg = <0x20>;
  313. remote = <&vin1>;
  314. port {
  315. adv7180: endpoint {
  316. bus-width = <8>;
  317. remote-endpoint = <&vin1ep0>;
  318. };
  319. };
  320. };
  321. };
  322. &iic3 {
  323. pinctrl-names = "default";
  324. pinctrl-0 = <&iic3_pins>;
  325. status = "okay";
  326. vdd_dvfs: regulator@68 {
  327. compatible = "dlg,da9210";
  328. reg = <0x68>;
  329. regulator-min-microvolt = <1000000>;
  330. regulator-max-microvolt = <1000000>;
  331. regulator-boot-on;
  332. regulator-always-on;
  333. };
  334. };
  335. &pci0 {
  336. status = "okay";
  337. pinctrl-0 = <&usb0_pins>;
  338. pinctrl-names = "default";
  339. };
  340. &pci1 {
  341. status = "okay";
  342. pinctrl-0 = <&usb1_pins>;
  343. pinctrl-names = "default";
  344. };
  345. &pci2 {
  346. status = "okay";
  347. pinctrl-0 = <&usb2_pins>;
  348. pinctrl-names = "default";
  349. };
  350. /* composite video input */
  351. &vin1 {
  352. pinctrl-0 = <&vin1_pins>;
  353. pinctrl-names = "default";
  354. status = "ok";
  355. port {
  356. #address-cells = <1>;
  357. #size-cells = <0>;
  358. vin1ep0: endpoint {
  359. remote-endpoint = <&adv7180>;
  360. bus-width = <8>;
  361. };
  362. };
  363. };