r8a7791-henninger.dts 5.2 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297
  1. /*
  2. * Device Tree Source for the Henninger board
  3. *
  4. * Copyright (C) 2014 Renesas Solutions Corp.
  5. * Copyright (C) 2014 Cogent Embedded, Inc.
  6. *
  7. * This file is licensed under the terms of the GNU General Public License
  8. * version 2. This program is licensed "as is" without any warranty of any
  9. * kind, whether express or implied.
  10. */
  11. /dts-v1/;
  12. #include "r8a7791.dtsi"
  13. #include <dt-bindings/gpio/gpio.h>
  14. / {
  15. model = "Henninger";
  16. compatible = "renesas,henninger", "renesas,r8a7791";
  17. aliases {
  18. serial0 = &scif0;
  19. };
  20. chosen {
  21. bootargs = "console=ttySC0,38400 ignore_loglevel rw root=/dev/nfs ip=dhcp";
  22. };
  23. memory@40000000 {
  24. device_type = "memory";
  25. reg = <0 0x40000000 0 0x40000000>;
  26. };
  27. memory@200000000 {
  28. device_type = "memory";
  29. reg = <2 0x00000000 0 0x40000000>;
  30. };
  31. vcc_sdhi0: regulator@0 {
  32. compatible = "regulator-fixed";
  33. regulator-name = "SDHI0 Vcc";
  34. regulator-min-microvolt = <3300000>;
  35. regulator-max-microvolt = <3300000>;
  36. regulator-always-on;
  37. };
  38. vccq_sdhi0: regulator@1 {
  39. compatible = "regulator-gpio";
  40. regulator-name = "SDHI0 VccQ";
  41. regulator-min-microvolt = <1800000>;
  42. regulator-max-microvolt = <3300000>;
  43. gpios = <&gpio2 12 GPIO_ACTIVE_HIGH>;
  44. gpios-states = <1>;
  45. states = <3300000 1
  46. 1800000 0>;
  47. };
  48. vcc_sdhi2: regulator@2 {
  49. compatible = "regulator-fixed";
  50. regulator-name = "SDHI2 Vcc";
  51. regulator-min-microvolt = <3300000>;
  52. regulator-max-microvolt = <3300000>;
  53. regulator-always-on;
  54. };
  55. vccq_sdhi2: regulator@3 {
  56. compatible = "regulator-gpio";
  57. regulator-name = "SDHI2 VccQ";
  58. regulator-min-microvolt = <1800000>;
  59. regulator-max-microvolt = <3300000>;
  60. gpios = <&gpio2 26 GPIO_ACTIVE_HIGH>;
  61. gpios-states = <1>;
  62. states = <3300000 1
  63. 1800000 0>;
  64. };
  65. };
  66. &extal_clk {
  67. clock-frequency = <20000000>;
  68. };
  69. &pfc {
  70. scif0_pins: serial0 {
  71. renesas,groups = "scif0_data_d";
  72. renesas,function = "scif0";
  73. };
  74. ether_pins: ether {
  75. renesas,groups = "eth_link", "eth_mdio", "eth_rmii";
  76. renesas,function = "eth";
  77. };
  78. phy1_pins: phy1 {
  79. renesas,groups = "intc_irq0";
  80. renesas,function = "intc";
  81. };
  82. sdhi0_pins: sd0 {
  83. renesas,groups = "sdhi0_data4", "sdhi0_ctrl";
  84. renesas,function = "sdhi0";
  85. };
  86. sdhi2_pins: sd2 {
  87. renesas,groups = "sdhi2_data4", "sdhi2_ctrl";
  88. renesas,function = "sdhi2";
  89. };
  90. i2c2_pins: i2c2 {
  91. renesas,groups = "i2c2";
  92. renesas,function = "i2c2";
  93. };
  94. qspi_pins: spi0 {
  95. renesas,groups = "qspi_ctrl", "qspi_data4";
  96. renesas,function = "qspi";
  97. };
  98. msiof0_pins: spi1 {
  99. renesas,groups = "msiof0_clk", "msiof0_sync", "msiof0_rx",
  100. "msiof0_tx";
  101. renesas,function = "msiof0";
  102. };
  103. usb0_pins: usb0 {
  104. renesas,groups = "usb0";
  105. renesas,function = "usb0";
  106. };
  107. usb1_pins: usb1 {
  108. renesas,groups = "usb1";
  109. renesas,function = "usb1";
  110. };
  111. vin0_pins: vin0 {
  112. renesas,groups = "vin0_data8", "vin0_clk";
  113. renesas,function = "vin0";
  114. };
  115. };
  116. &scif0 {
  117. pinctrl-0 = <&scif0_pins>;
  118. pinctrl-names = "default";
  119. status = "okay";
  120. };
  121. &ether {
  122. pinctrl-0 = <&ether_pins &phy1_pins>;
  123. pinctrl-names = "default";
  124. phy-handle = <&phy1>;
  125. renesas,ether-link-active-low;
  126. status = "ok";
  127. phy1: ethernet-phy@1 {
  128. reg = <1>;
  129. interrupt-parent = <&irqc0>;
  130. interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
  131. micrel,led-mode = <1>;
  132. };
  133. };
  134. &sata0 {
  135. status = "okay";
  136. };
  137. &sdhi0 {
  138. pinctrl-0 = <&sdhi0_pins>;
  139. pinctrl-names = "default";
  140. vmmc-supply = <&vcc_sdhi0>;
  141. vqmmc-supply = <&vccq_sdhi0>;
  142. cd-gpios = <&gpio6 6 GPIO_ACTIVE_LOW>;
  143. wp-gpios = <&gpio6 7 GPIO_ACTIVE_HIGH>;
  144. status = "okay";
  145. };
  146. &sdhi2 {
  147. pinctrl-0 = <&sdhi2_pins>;
  148. pinctrl-names = "default";
  149. vmmc-supply = <&vcc_sdhi2>;
  150. vqmmc-supply = <&vccq_sdhi2>;
  151. cd-gpios = <&gpio6 22 GPIO_ACTIVE_LOW>;
  152. status = "okay";
  153. };
  154. &i2c2 {
  155. pinctrl-0 = <&i2c2_pins>;
  156. pinctrl-names = "default";
  157. status = "okay";
  158. clock-frequency = <400000>;
  159. composite-in@20 {
  160. compatible = "adi,adv7180";
  161. reg = <0x20>;
  162. remote = <&vin0>;
  163. port {
  164. adv7180: endpoint {
  165. bus-width = <8>;
  166. remote-endpoint = <&vin0ep>;
  167. };
  168. };
  169. };
  170. };
  171. &qspi {
  172. pinctrl-0 = <&qspi_pins>;
  173. pinctrl-names = "default";
  174. status = "okay";
  175. flash@0 {
  176. #address-cells = <1>;
  177. #size-cells = <1>;
  178. compatible = "spansion,s25fl512s";
  179. reg = <0>;
  180. spi-max-frequency = <30000000>;
  181. spi-tx-bus-width = <4>;
  182. spi-rx-bus-width = <4>;
  183. m25p,fast-read;
  184. partition@0 {
  185. label = "loader_prg";
  186. reg = <0x00000000 0x00040000>;
  187. read-only;
  188. };
  189. partition@40000 {
  190. label = "user_prg";
  191. reg = <0x00040000 0x00400000>;
  192. read-only;
  193. };
  194. partition@440000 {
  195. label = "flash_fs";
  196. reg = <0x00440000 0x03bc0000>;
  197. };
  198. };
  199. };
  200. &msiof0 {
  201. pinctrl-0 = <&msiof0_pins>;
  202. pinctrl-names = "default";
  203. status = "okay";
  204. pmic@0 {
  205. compatible = "renesas,r2a11302ft";
  206. reg = <0>;
  207. spi-max-frequency = <6000000>;
  208. spi-cpol;
  209. spi-cpha;
  210. };
  211. };
  212. &pci0 {
  213. status = "okay";
  214. pinctrl-0 = <&usb0_pins>;
  215. pinctrl-names = "default";
  216. };
  217. &pci1 {
  218. status = "okay";
  219. pinctrl-0 = <&usb1_pins>;
  220. pinctrl-names = "default";
  221. };
  222. &pcie_bus_clk {
  223. status = "okay";
  224. };
  225. &pciec {
  226. status = "okay";
  227. };
  228. /* composite video input */
  229. &vin0 {
  230. status = "ok";
  231. pinctrl-0 = <&vin0_pins>;
  232. pinctrl-names = "default";
  233. port {
  234. #address-cells = <1>;
  235. #size-cells = <0>;
  236. vin0ep: endpoint {
  237. remote-endpoint = <&adv7180>;
  238. bus-width = <8>;
  239. };
  240. };
  241. };