ste-hrefv60plus.dtsi 5.4 KB

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  1. /*
  2. * Copyright 2012 ST-Ericsson AB
  3. *
  4. * The code contained herein is licensed under the GNU General Public
  5. * License. You may obtain a copy of the GNU General Public License
  6. * Version 2 or later at the following locations:
  7. *
  8. * http://www.opensource.org/licenses/gpl-license.html
  9. * http://www.gnu.org/copyleft/gpl.html
  10. */
  11. #include "ste-dbx5x0.dtsi"
  12. #include "ste-href-ab8500.dtsi"
  13. #include "ste-href.dtsi"
  14. / {
  15. model = "ST-Ericsson HREF (v60+) platform with Device Tree";
  16. compatible = "st-ericsson,hrefv60+", "st-ericsson,u8500";
  17. soc {
  18. // External Micro SD slot
  19. sdi0_per1@80126000 {
  20. cd-gpios = <&gpio2 31 0x4>; // 95
  21. };
  22. vmmci: regulator-gpio {
  23. gpios = <&gpio0 5 0x4>;
  24. enable-gpio = <&gpio5 9 0x4>;
  25. };
  26. pinctrl {
  27. /*
  28. * Set this up using hogs, as time goes by and as seems fit, these
  29. * can be moved over to being controlled by respective device.
  30. */
  31. pinctrl-names = "default";
  32. pinctrl-0 = <&ipgpio_hrefv60_mode>,
  33. <&etm_hrefv60_mode>,
  34. <&nahj_hrefv60_mode>,
  35. <&nfc_hrefv60_mode>,
  36. <&force_hrefv60_mode>,
  37. <&dipro_hrefv60_mode>,
  38. <&vaudio_hf_hrefv60_mode>,
  39. <&gbf_hrefv60_mode>,
  40. <&hdtv_hrefv60_mode>,
  41. <&touch_hrefv60_mode>;
  42. sdi0 {
  43. /* SD card detect GPIO pin, extend default state */
  44. sdi0_default_mode: sdi0_default {
  45. default_hrefv60_cfg1 {
  46. ste,pins = "GPIO95_E8";
  47. ste,config = <&gpio_in_pu>;
  48. };
  49. };
  50. };
  51. ipgpio {
  52. /*
  53. * XENON Flashgun on image processor GPIO (controlled from image
  54. * processor firmware), mux in these image processor GPIO lines 0
  55. * (XENON_FLASH_ID), 1 (XENON_READY) and there is an assistant
  56. * LED on IP GPIO 4 (XENON_EN2) on altfunction C, that need bias
  57. * from GPIO21 so pull up 0, 1 and drive 4 and GPIO21 low as output.
  58. */
  59. ipgpio_hrefv60_mode: ipgpio_hrefv60 {
  60. hrefv60_mux {
  61. ste,function = "ipgpio";
  62. ste,pins = "ipgpio0_c_1", "ipgpio1_c_1", "ipgpio4_c_1";
  63. };
  64. hrefv60_cfg1 {
  65. ste,pins = "GPIO6_AF6", "GPIO7_AG5";
  66. ste,config = <&in_pu>;
  67. };
  68. hrefv60_cfg2 {
  69. ste,pins = "GPIO21_AB3";
  70. ste,config = <&gpio_out_lo>;
  71. };
  72. hrefv60_cfg3 {
  73. ste,pins = "GPIO64_F3";
  74. ste,config = <&out_lo>;
  75. };
  76. };
  77. };
  78. etm {
  79. /*
  80. * Drive D19-D23 for the ETM PTM trace interface low,
  81. * (presumably pins are unconnected therefore grounded here,
  82. * the "other alt C1" setting enables these pins)
  83. */
  84. etm_hrefv60_mode: etm_hrefv60 {
  85. hrefv60_cfg1 {
  86. ste,pins =
  87. "GPIO70_G5",
  88. "GPIO71_G4",
  89. "GPIO72_H4",
  90. "GPIO73_H3",
  91. "GPIO74_J3";
  92. ste,config = <&gpio_out_lo>;
  93. };
  94. };
  95. };
  96. nahj {
  97. nahj_hrefv60_mode: nahj_hrefv60 {
  98. /* NAHJ CTRL on GPIO76 to low, CTRL_INV on GPIO216 to high */
  99. hrefv60_cfg1 {
  100. ste,pins = "GPIO76_J2";
  101. ste,config = <&gpio_out_lo>;
  102. };
  103. hrefv60_cfg2 {
  104. ste,pins = "GPIO216_AG12";
  105. ste,config = <&gpio_out_hi>;
  106. };
  107. };
  108. };
  109. nfc {
  110. nfc_hrefv60_mode: nfc_hrefv60 {
  111. /* NFC ENA and RESET to low, pulldown IRQ line */
  112. hrefv60_cfg1 {
  113. ste,pins =
  114. "GPIO77_H1", /* NFC_ENA */
  115. "GPIO142_C11"; /* NFC_RESET */
  116. ste,config = <&gpio_out_lo>;
  117. };
  118. hrefv60_cfg2 {
  119. ste,pins = "GPIO144_B13"; /* NFC_IRQ */
  120. ste,config = <&gpio_in_pd>;
  121. };
  122. };
  123. };
  124. force {
  125. force_hrefv60_mode: force_hrefv60 {
  126. hrefv60_cfg1 {
  127. ste,pins = "GPIO91_B6"; /* FORCE_SENSING_INT */
  128. ste,config = <&gpio_in_pu>;
  129. };
  130. hrefv60_cfg2 {
  131. ste,pins =
  132. "GPIO92_D6", /* FORCE_SENSING_RST */
  133. "GPIO97_D9"; /* FORCE_SENSING_WU */
  134. ste,config = <&gpio_out_lo>;
  135. };
  136. };
  137. };
  138. dipro {
  139. dipro_hrefv60_mode: dipro_hrefv60 {
  140. hrefv60_cfg1 {
  141. ste,pins = "GPIO139_C9"; /* DIPRO_INT */
  142. ste,config = <&gpio_in_pu>;
  143. };
  144. };
  145. };
  146. vaudio_hf {
  147. vaudio_hf_hrefv60_mode: vaudio_hf_hrefv60 {
  148. /* Audio Amplifier HF enable GPIO */
  149. hrefv60_cfg1 {
  150. ste,pins = "GPIO149_B14"; /* VAUDIO_HF_EN, enable MAX8968 */
  151. ste,config = <&gpio_out_hi>;
  152. };
  153. };
  154. };
  155. gbf {
  156. gbf_hrefv60_mode: gbf_hrefv60 {
  157. /*
  158. * GBF (GPS, Bluetooth, FM-radio) interface,
  159. * pull low to reset state
  160. */
  161. hrefv60_cfg1 {
  162. ste,pins = "GPIO171_D23"; /* GBF_ENA_RESET */
  163. ste,config = <&gpio_out_lo>;
  164. };
  165. };
  166. };
  167. hdtv {
  168. hdtv_hrefv60_mode: hdtv_hrefv60 {
  169. /* MSP : HDTV INTERFACE GPIO line */
  170. hrefv60_cfg1 {
  171. ste,pins = "GPIO192_AJ27";
  172. ste,config = <&gpio_in_pd>;
  173. };
  174. };
  175. };
  176. touch {
  177. touch_hrefv60_mode: touch_hrefv60 {
  178. /*
  179. * Touch screen uses GPIO 143 for RST1, GPIO 146 for RST2 and
  180. * GPIO 67 for interrupts. Pull-up the IRQ line and drive both
  181. * reset signals low.
  182. */
  183. hrefv60_cfg1 {
  184. ste,pins = "GPIO143_D12", "GPIO146_D13";
  185. ste,config = <&gpio_out_lo>;
  186. };
  187. hrefv60_cfg2 {
  188. ste,pins = "GPIO67_G2";
  189. ste,config = <&gpio_in_pu>;
  190. };
  191. };
  192. };
  193. mcde {
  194. lcd_hrefv60_mode: lcd_hrefv60 {
  195. /*
  196. * Display Interface 1 uses GPIO 65 for RST (reset).
  197. * Display Interface 2 uses GPIO 66 for RST (reset).
  198. * Drive DISP1 reset high (not reset), driver DISP2 reset low (reset)
  199. */
  200. hrefv60_cfg1 {
  201. ste,pins ="GPIO65_F1";
  202. ste,config = <&gpio_out_hi>;
  203. };
  204. hrefv60_cfg2 {
  205. ste,pins ="GPIO66_G3";
  206. ste,config = <&gpio_out_lo>;
  207. };
  208. };
  209. };
  210. };
  211. };
  212. };