stih407-pinctrl.dtsi 14 KB

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  1. /*
  2. * Copyright (C) 2014 STMicroelectronics Limited.
  3. * Author: Giuseppe Cavallaro <peppe.cavallaro@st.com>
  4. *
  5. * This program is free software; you can redistribute it and/or modify
  6. * it under the terms of the GNU General Public License version 2 as
  7. * publishhed by the Free Software Foundation.
  8. */
  9. #include "st-pincfg.h"
  10. #include <dt-bindings/interrupt-controller/arm-gic.h>
  11. / {
  12. aliases {
  13. /* 0-5: PIO_SBC */
  14. gpio0 = &pio0;
  15. gpio1 = &pio1;
  16. gpio2 = &pio2;
  17. gpio3 = &pio3;
  18. gpio4 = &pio4;
  19. gpio5 = &pio5;
  20. /* 10-19: PIO_FRONT0 */
  21. gpio6 = &pio10;
  22. gpio7 = &pio11;
  23. gpio8 = &pio12;
  24. gpio9 = &pio13;
  25. gpio10 = &pio14;
  26. gpio11 = &pio15;
  27. gpio12 = &pio16;
  28. gpio13 = &pio17;
  29. gpio14 = &pio18;
  30. gpio15 = &pio19;
  31. /* 20: PIO_FRONT1 */
  32. gpio16 = &pio20;
  33. /* 30-35: PIO_REAR */
  34. gpio17 = &pio30;
  35. gpio18 = &pio31;
  36. gpio19 = &pio32;
  37. gpio20 = &pio33;
  38. gpio21 = &pio34;
  39. gpio22 = &pio35;
  40. /* 40-42: PIO_FLASH */
  41. gpio23 = &pio40;
  42. gpio24 = &pio41;
  43. gpio25 = &pio42;
  44. };
  45. soc {
  46. pin-controller-sbc {
  47. #address-cells = <1>;
  48. #size-cells = <1>;
  49. compatible = "st,stih407-sbc-pinctrl";
  50. st,syscfg = <&syscfg_sbc>;
  51. reg = <0x0961f080 0x4>;
  52. reg-names = "irqmux";
  53. interrupts = <GIC_SPI 188 IRQ_TYPE_NONE>;
  54. interrupts-names = "irqmux";
  55. ranges = <0 0x09610000 0x6000>;
  56. pio0: gpio@09610000 {
  57. gpio-controller;
  58. #gpio-cells = <1>;
  59. interrupt-controller;
  60. #interrupt-cells = <2>;
  61. reg = <0x0 0x100>;
  62. st,bank-name = "PIO0";
  63. };
  64. pio1: gpio@09611000 {
  65. gpio-controller;
  66. #gpio-cells = <1>;
  67. interrupt-controller;
  68. #interrupt-cells = <2>;
  69. reg = <0x1000 0x100>;
  70. st,bank-name = "PIO1";
  71. };
  72. pio2: gpio@09612000 {
  73. gpio-controller;
  74. #gpio-cells = <1>;
  75. interrupt-controller;
  76. #interrupt-cells = <2>;
  77. reg = <0x2000 0x100>;
  78. st,bank-name = "PIO2";
  79. };
  80. pio3: gpio@09613000 {
  81. gpio-controller;
  82. #gpio-cells = <1>;
  83. interrupt-controller;
  84. #interrupt-cells = <2>;
  85. reg = <0x3000 0x100>;
  86. st,bank-name = "PIO3";
  87. };
  88. pio4: gpio@09614000 {
  89. gpio-controller;
  90. #gpio-cells = <1>;
  91. interrupt-controller;
  92. #interrupt-cells = <2>;
  93. reg = <0x4000 0x100>;
  94. st,bank-name = "PIO4";
  95. };
  96. pio5: gpio@09615000 {
  97. gpio-controller;
  98. #gpio-cells = <1>;
  99. interrupt-controller;
  100. #interrupt-cells = <2>;
  101. reg = <0x5000 0x100>;
  102. st,bank-name = "PIO5";
  103. };
  104. rc {
  105. pinctrl_ir: ir0 {
  106. st,pins {
  107. ir = <&pio4 0 ALT2 IN>;
  108. };
  109. };
  110. };
  111. /* SBC_ASC0 - UART10 */
  112. sbc_serial0 {
  113. pinctrl_sbc_serial0: sbc_serial0-0 {
  114. st,pins {
  115. tx = <&pio3 4 ALT1 OUT>;
  116. rx = <&pio3 5 ALT1 IN>;
  117. };
  118. };
  119. };
  120. /* SBC_ASC1 - UART11 */
  121. sbc_serial1 {
  122. pinctrl_sbc_serial1: sbc_serial1-0 {
  123. st,pins {
  124. tx = <&pio2 6 ALT3 OUT>;
  125. rx = <&pio2 7 ALT3 IN>;
  126. };
  127. };
  128. };
  129. i2c10 {
  130. pinctrl_i2c10_default: i2c10-default {
  131. st,pins {
  132. sda = <&pio4 6 ALT1 BIDIR>;
  133. scl = <&pio4 5 ALT1 BIDIR>;
  134. };
  135. };
  136. };
  137. i2c11 {
  138. pinctrl_i2c11_default: i2c11-default {
  139. st,pins {
  140. sda = <&pio5 1 ALT1 BIDIR>;
  141. scl = <&pio5 0 ALT1 BIDIR>;
  142. };
  143. };
  144. };
  145. keyscan {
  146. pinctrl_keyscan: keyscan {
  147. st,pins {
  148. keyin0 = <&pio4 0 ALT6 IN>;
  149. keyin1 = <&pio4 5 ALT4 IN>;
  150. keyin2 = <&pio0 4 ALT2 IN>;
  151. keyin3 = <&pio2 6 ALT2 IN>;
  152. keyout0 = <&pio4 6 ALT4 OUT>;
  153. keyout1 = <&pio1 7 ALT2 OUT>;
  154. keyout2 = <&pio0 6 ALT2 OUT>;
  155. keyout3 = <&pio2 7 ALT2 OUT>;
  156. };
  157. };
  158. };
  159. gmac1 {
  160. /*
  161. * Almost all the boards based on STiH407 SoC have an embedded
  162. * switch where the mdio/mdc have been used for managing the SMI
  163. * iface via I2C. For this reason these lines can be allocated
  164. * by using dedicated configuration (in case of there will be a
  165. * standard PHY transceiver on-board).
  166. */
  167. pinctrl_rgmii1: rgmii1-0 {
  168. st,pins {
  169. txd0 = <&pio0 0 ALT1 OUT DE_IO 0 CLK_A>;
  170. txd1 = <&pio0 1 ALT1 OUT DE_IO 0 CLK_A>;
  171. txd2 = <&pio0 2 ALT1 OUT DE_IO 0 CLK_A>;
  172. txd3 = <&pio0 3 ALT1 OUT DE_IO 0 CLK_A>;
  173. txen = <&pio0 5 ALT1 OUT DE_IO 0 CLK_A>;
  174. txclk = <&pio0 6 ALT1 IN NICLK 0 CLK_A>;
  175. rxd0 = <&pio1 4 ALT1 IN DE_IO 0 CLK_A>;
  176. rxd1 = <&pio1 5 ALT1 IN DE_IO 0 CLK_A>;
  177. rxd2 = <&pio1 6 ALT1 IN DE_IO 0 CLK_A>;
  178. rxd3 = <&pio1 7 ALT1 IN DE_IO 0 CLK_A>;
  179. rxdv = <&pio2 0 ALT1 IN DE_IO 0 CLK_A>;
  180. rxclk = <&pio2 2 ALT1 IN NICLK 500 CLK_A>;
  181. clk125 = <&pio3 7 ALT4 IN NICLK 0 CLK_A>;
  182. phyclk = <&pio2 3 ALT4 OUT NICLK 1750 CLK_B>;
  183. };
  184. };
  185. pinctrl_rgmii1_mdio: rgmii1-mdio {
  186. st,pins {
  187. mdio = <&pio1 0 ALT1 OUT BYPASS 0>;
  188. mdc = <&pio1 1 ALT1 OUT NICLK 0 CLK_A>;
  189. mdint = <&pio1 3 ALT1 IN BYPASS 0>;
  190. };
  191. };
  192. pinctrl_mii1: mii1 {
  193. st,pins {
  194. txd0 = <&pio0 0 ALT1 OUT SE_NICLK_IO 0 CLK_A>;
  195. txd1 = <&pio0 1 ALT1 OUT SE_NICLK_IO 0 CLK_A>;
  196. txd2 = <&pio0 2 ALT1 OUT SE_NICLK_IO 0 CLK_A>;
  197. txd3 = <&pio0 3 ALT1 OUT SE_NICLK_IO 0 CLK_A>;
  198. txer = <&pio0 4 ALT1 OUT SE_NICLK_IO 0 CLK_A>;
  199. txen = <&pio0 5 ALT1 OUT SE_NICLK_IO 0 CLK_A>;
  200. txclk = <&pio0 6 ALT1 IN NICLK 0 CLK_A>;
  201. col = <&pio0 7 ALT1 IN BYPASS 1000>;
  202. mdio = <&pio1 0 ALT1 OUT BYPASS 1500>;
  203. mdc = <&pio1 1 ALT1 OUT NICLK 0 CLK_A>;
  204. crs = <&pio1 2 ALT1 IN BYPASS 1000>;
  205. mdint = <&pio1 3 ALT1 IN BYPASS 0>;
  206. rxd0 = <&pio1 4 ALT1 IN SE_NICLK_IO 0 CLK_A>;
  207. rxd1 = <&pio1 5 ALT1 IN SE_NICLK_IO 0 CLK_A>;
  208. rxd2 = <&pio1 6 ALT1 IN SE_NICLK_IO 0 CLK_A>;
  209. rxd3 = <&pio1 7 ALT1 IN SE_NICLK_IO 0 CLK_A>;
  210. rxdv = <&pio2 0 ALT1 IN SE_NICLK_IO 0 CLK_A>;
  211. rx_er = <&pio2 1 ALT1 IN SE_NICLK_IO 0 CLK_A>;
  212. rxclk = <&pio2 2 ALT1 IN NICLK 0 CLK_A>;
  213. phyclk = <&pio2 3 ALT1 OUT NICLK 0 CLK_A>;
  214. };
  215. };
  216. };
  217. pwm1 {
  218. pinctrl_pwm1_chan0_default: pwm1-0-default {
  219. st,pins {
  220. pwm-out = <&pio3 0 ALT1 OUT>;
  221. };
  222. };
  223. pinctrl_pwm1_chan1_default: pwm1-1-default {
  224. st,pins {
  225. pwm-out = <&pio4 4 ALT1 OUT>;
  226. };
  227. };
  228. pinctrl_pwm1_chan2_default: pwm1-2-default {
  229. st,pins {
  230. pwm-out = <&pio4 6 ALT3 OUT>;
  231. };
  232. };
  233. pinctrl_pwm1_chan3_default: pwm1-3-default {
  234. st,pins {
  235. pwm-out = <&pio4 7 ALT3 OUT>;
  236. };
  237. };
  238. };
  239. };
  240. pin-controller-front0 {
  241. #address-cells = <1>;
  242. #size-cells = <1>;
  243. compatible = "st,stih407-front-pinctrl";
  244. st,syscfg = <&syscfg_front>;
  245. reg = <0x0920f080 0x4>;
  246. reg-names = "irqmux";
  247. interrupts = <GIC_SPI 189 IRQ_TYPE_NONE>;
  248. interrupts-names = "irqmux";
  249. ranges = <0 0x09200000 0x10000>;
  250. pio10: pio@09200000 {
  251. gpio-controller;
  252. #gpio-cells = <1>;
  253. interrupt-controller;
  254. #interrupt-cells = <2>;
  255. reg = <0x0 0x100>;
  256. st,bank-name = "PIO10";
  257. };
  258. pio11: pio@09201000 {
  259. gpio-controller;
  260. #gpio-cells = <1>;
  261. interrupt-controller;
  262. #interrupt-cells = <2>;
  263. reg = <0x1000 0x100>;
  264. st,bank-name = "PIO11";
  265. };
  266. pio12: pio@09202000 {
  267. gpio-controller;
  268. #gpio-cells = <1>;
  269. interrupt-controller;
  270. #interrupt-cells = <2>;
  271. reg = <0x2000 0x100>;
  272. st,bank-name = "PIO12";
  273. };
  274. pio13: pio@09203000 {
  275. gpio-controller;
  276. #gpio-cells = <1>;
  277. interrupt-controller;
  278. #interrupt-cells = <2>;
  279. reg = <0x3000 0x100>;
  280. st,bank-name = "PIO13";
  281. };
  282. pio14: pio@09204000 {
  283. gpio-controller;
  284. #gpio-cells = <1>;
  285. interrupt-controller;
  286. #interrupt-cells = <2>;
  287. reg = <0x4000 0x100>;
  288. st,bank-name = "PIO14";
  289. };
  290. pio15: pio@09205000 {
  291. gpio-controller;
  292. #gpio-cells = <1>;
  293. interrupt-controller;
  294. #interrupt-cells = <2>;
  295. reg = <0x5000 0x100>;
  296. st,bank-name = "PIO15";
  297. };
  298. pio16: pio@09206000 {
  299. gpio-controller;
  300. #gpio-cells = <1>;
  301. interrupt-controller;
  302. #interrupt-cells = <2>;
  303. reg = <0x6000 0x100>;
  304. st,bank-name = "PIO16";
  305. };
  306. pio17: pio@09207000 {
  307. gpio-controller;
  308. #gpio-cells = <1>;
  309. interrupt-controller;
  310. #interrupt-cells = <2>;
  311. reg = <0x7000 0x100>;
  312. st,bank-name = "PIO17";
  313. };
  314. pio18: pio@09208000 {
  315. gpio-controller;
  316. #gpio-cells = <1>;
  317. interrupt-controller;
  318. #interrupt-cells = <2>;
  319. reg = <0x8000 0x100>;
  320. st,bank-name = "PIO18";
  321. };
  322. pio19: pio@09209000 {
  323. gpio-controller;
  324. #gpio-cells = <1>;
  325. interrupt-controller;
  326. #interrupt-cells = <2>;
  327. reg = <0x9000 0x100>;
  328. st,bank-name = "PIO19";
  329. };
  330. /* Comms */
  331. serial0 {
  332. pinctrl_serial0: serial0-0 {
  333. st,pins {
  334. tx = <&pio17 0 ALT1 OUT>;
  335. rx = <&pio17 1 ALT1 IN>;
  336. };
  337. };
  338. };
  339. serial1 {
  340. pinctrl_serial1: serial1-0 {
  341. st,pins {
  342. tx = <&pio16 0 ALT1 OUT>;
  343. rx = <&pio16 1 ALT1 IN>;
  344. };
  345. };
  346. };
  347. serial2 {
  348. pinctrl_serial2: serial2-0 {
  349. st,pins {
  350. tx = <&pio15 0 ALT1 OUT>;
  351. rx = <&pio15 1 ALT1 IN>;
  352. };
  353. };
  354. };
  355. mmc1 {
  356. pinctrl_sd1: sd1-0 {
  357. st,pins {
  358. sd_clk = <&pio19 3 ALT5 BIDIR NICLK 0 CLK_B>;
  359. sd_cmd = <&pio19 2 ALT5 BIDIR_PU BYPASS 0>;
  360. sd_dat0 = <&pio19 4 ALT5 BIDIR_PU BYPASS 0>;
  361. sd_dat1 = <&pio19 5 ALT5 BIDIR_PU BYPASS 0>;
  362. sd_dat2 = <&pio19 6 ALT5 BIDIR_PU BYPASS 0>;
  363. sd_dat3 = <&pio19 7 ALT5 BIDIR_PU BYPASS 0>;
  364. sd_led = <&pio16 6 ALT6 OUT>;
  365. sd_pwren = <&pio16 7 ALT6 OUT>;
  366. sd_cd = <&pio19 0 ALT6 IN>;
  367. sd_wp = <&pio19 1 ALT6 IN>;
  368. };
  369. };
  370. };
  371. i2c0 {
  372. pinctrl_i2c0_default: i2c0-default {
  373. st,pins {
  374. sda = <&pio10 6 ALT2 BIDIR>;
  375. scl = <&pio10 5 ALT2 BIDIR>;
  376. };
  377. };
  378. };
  379. i2c1 {
  380. pinctrl_i2c1_default: i2c1-default {
  381. st,pins {
  382. sda = <&pio11 1 ALT2 BIDIR>;
  383. scl = <&pio11 0 ALT2 BIDIR>;
  384. };
  385. };
  386. };
  387. i2c2 {
  388. pinctrl_i2c2_default: i2c2-default {
  389. st,pins {
  390. sda = <&pio15 6 ALT2 BIDIR>;
  391. scl = <&pio15 5 ALT2 BIDIR>;
  392. };
  393. };
  394. };
  395. i2c3 {
  396. pinctrl_i2c3_default: i2c3-default {
  397. st,pins {
  398. sda = <&pio18 6 ALT1 BIDIR>;
  399. scl = <&pio18 5 ALT1 BIDIR>;
  400. };
  401. };
  402. };
  403. spi0 {
  404. pinctrl_spi0_default: spi0-default {
  405. st,pins {
  406. mtsr = <&pio12 6 ALT2 BIDIR>;
  407. mrst = <&pio12 7 ALT2 BIDIR>;
  408. scl = <&pio12 5 ALT2 BIDIR>;
  409. };
  410. };
  411. };
  412. };
  413. pin-controller-front1 {
  414. #address-cells = <1>;
  415. #size-cells = <1>;
  416. compatible = "st,stih407-front-pinctrl";
  417. st,syscfg = <&syscfg_front>;
  418. reg = <0x0921f080 0x4>;
  419. reg-names = "irqmux";
  420. interrupts = <GIC_SPI 190 IRQ_TYPE_NONE>;
  421. interrupts-names = "irqmux";
  422. ranges = <0 0x09210000 0x10000>;
  423. pio20: pio@09210000 {
  424. gpio-controller;
  425. #gpio-cells = <1>;
  426. interrupt-controller;
  427. #interrupt-cells = <2>;
  428. reg = <0x0 0x100>;
  429. st,bank-name = "PIO20";
  430. };
  431. };
  432. pin-controller-rear {
  433. #address-cells = <1>;
  434. #size-cells = <1>;
  435. compatible = "st,stih407-rear-pinctrl";
  436. st,syscfg = <&syscfg_rear>;
  437. reg = <0x0922f080 0x4>;
  438. reg-names = "irqmux";
  439. interrupts = <GIC_SPI 191 IRQ_TYPE_NONE>;
  440. interrupts-names = "irqmux";
  441. ranges = <0 0x09220000 0x6000>;
  442. pio30: gpio@09220000 {
  443. gpio-controller;
  444. #gpio-cells = <1>;
  445. interrupt-controller;
  446. #interrupt-cells = <2>;
  447. reg = <0x0 0x100>;
  448. st,bank-name = "PIO30";
  449. };
  450. pio31: gpio@09221000 {
  451. gpio-controller;
  452. #gpio-cells = <1>;
  453. interrupt-controller;
  454. #interrupt-cells = <2>;
  455. reg = <0x1000 0x100>;
  456. st,bank-name = "PIO31";
  457. };
  458. pio32: gpio@09222000 {
  459. gpio-controller;
  460. #gpio-cells = <1>;
  461. interrupt-controller;
  462. #interrupt-cells = <2>;
  463. reg = <0x2000 0x100>;
  464. st,bank-name = "PIO32";
  465. };
  466. pio33: gpio@09223000 {
  467. gpio-controller;
  468. #gpio-cells = <1>;
  469. interrupt-controller;
  470. #interrupt-cells = <2>;
  471. reg = <0x3000 0x100>;
  472. st,bank-name = "PIO33";
  473. };
  474. pio34: gpio@09224000 {
  475. gpio-controller;
  476. #gpio-cells = <1>;
  477. interrupt-controller;
  478. #interrupt-cells = <2>;
  479. reg = <0x4000 0x100>;
  480. st,bank-name = "PIO34";
  481. };
  482. pio35: gpio@09225000 {
  483. gpio-controller;
  484. #gpio-cells = <1>;
  485. interrupt-controller;
  486. #interrupt-cells = <2>;
  487. reg = <0x5000 0x100>;
  488. st,bank-name = "PIO35";
  489. };
  490. i2c4 {
  491. pinctrl_i2c4_default: i2c4-default {
  492. st,pins {
  493. sda = <&pio30 1 ALT1 BIDIR>;
  494. scl = <&pio30 0 ALT1 BIDIR>;
  495. };
  496. };
  497. };
  498. i2c5 {
  499. pinctrl_i2c5_default: i2c5-default {
  500. st,pins {
  501. sda = <&pio34 4 ALT1 BIDIR>;
  502. scl = <&pio34 3 ALT1 BIDIR>;
  503. };
  504. };
  505. };
  506. usb3 {
  507. pinctrl_usb3: usb3-2 {
  508. st,pins {
  509. usb-oc-detect = <&pio35 4 ALT1 IN>;
  510. usb-pwr-enable = <&pio35 5 ALT1 OUT>;
  511. usb-vbus-valid = <&pio35 6 ALT1 IN>;
  512. };
  513. };
  514. };
  515. pwm0 {
  516. pinctrl_pwm0_chan0_default: pwm0-0-default {
  517. st,pins {
  518. pwm-out = <&pio31 1 ALT1 OUT>;
  519. };
  520. };
  521. };
  522. };
  523. pin-controller-flash {
  524. #address-cells = <1>;
  525. #size-cells = <1>;
  526. compatible = "st,stih407-flash-pinctrl";
  527. st,syscfg = <&syscfg_flash>;
  528. reg = <0x0923f080 0x4>;
  529. reg-names = "irqmux";
  530. interrupts = <GIC_SPI 192 IRQ_TYPE_NONE>;
  531. interrupts-names = "irqmux";
  532. ranges = <0 0x09230000 0x3000>;
  533. pio40: gpio@09230000 {
  534. gpio-controller;
  535. #gpio-cells = <1>;
  536. interrupt-controller;
  537. #interrupt-cells = <2>;
  538. reg = <0 0x100>;
  539. st,bank-name = "PIO40";
  540. };
  541. pio41: gpio@09231000 {
  542. gpio-controller;
  543. #gpio-cells = <1>;
  544. interrupt-controller;
  545. #interrupt-cells = <2>;
  546. reg = <0x1000 0x100>;
  547. st,bank-name = "PIO41";
  548. };
  549. pio42: gpio@09232000 {
  550. gpio-controller;
  551. #gpio-cells = <1>;
  552. interrupt-controller;
  553. #interrupt-cells = <2>;
  554. reg = <0x2000 0x100>;
  555. st,bank-name = "PIO42";
  556. };
  557. mmc0 {
  558. pinctrl_mmc0: mmc0-0 {
  559. st,pins {
  560. emmc_clk = <&pio40 6 ALT1 BIDIR>;
  561. emmc_cmd = <&pio40 7 ALT1 BIDIR_PU>;
  562. emmc_d0 = <&pio41 0 ALT1 BIDIR_PU>;
  563. emmc_d1 = <&pio41 1 ALT1 BIDIR_PU>;
  564. emmc_d2 = <&pio41 2 ALT1 BIDIR_PU>;
  565. emmc_d3 = <&pio41 3 ALT1 BIDIR_PU>;
  566. emmc_d4 = <&pio41 4 ALT1 BIDIR_PU>;
  567. emmc_d5 = <&pio41 5 ALT1 BIDIR_PU>;
  568. emmc_d6 = <&pio41 6 ALT1 BIDIR_PU>;
  569. emmc_d7 = <&pio41 7 ALT1 BIDIR_PU>;
  570. };
  571. };
  572. };
  573. };
  574. };
  575. };