tegra114-dalmore.dts 34 KB

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  1. /*
  2. * This dts file supports Dalmore A04.
  3. * Other board revisions are not supported
  4. */
  5. /dts-v1/;
  6. #include <dt-bindings/input/input.h>
  7. #include "tegra114.dtsi"
  8. / {
  9. model = "NVIDIA Tegra114 Dalmore evaluation board";
  10. compatible = "nvidia,dalmore", "nvidia,tegra114";
  11. aliases {
  12. rtc0 = "/i2c@7000d000/tps65913@58";
  13. rtc1 = "/rtc@7000e000";
  14. serial0 = &uartd;
  15. };
  16. memory {
  17. reg = <0x80000000 0x40000000>;
  18. };
  19. host1x@50000000 {
  20. hdmi@54280000 {
  21. status = "okay";
  22. hdmi-supply = <&vdd_5v0_hdmi>;
  23. vdd-supply = <&vdd_hdmi_reg>;
  24. pll-supply = <&palmas_smps3_reg>;
  25. nvidia,ddc-i2c-bus = <&hdmi_ddc>;
  26. nvidia,hpd-gpio =
  27. <&gpio TEGRA_GPIO(N, 7) GPIO_ACTIVE_HIGH>;
  28. };
  29. dsi@54300000 {
  30. status = "okay";
  31. avdd-dsi-csi-supply = <&avdd_1v2_reg>;
  32. panel@0 {
  33. compatible = "panasonic,vvx10f004b00",
  34. "simple-panel";
  35. reg = <0>;
  36. power-supply = <&avdd_lcd_reg>;
  37. backlight = <&backlight>;
  38. };
  39. };
  40. };
  41. pinmux@70000868 {
  42. pinctrl-names = "default";
  43. pinctrl-0 = <&state_default>;
  44. state_default: pinmux {
  45. clk1_out_pw4 {
  46. nvidia,pins = "clk1_out_pw4";
  47. nvidia,function = "extperiph1";
  48. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  49. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  50. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  51. };
  52. dap1_din_pn1 {
  53. nvidia,pins = "dap1_din_pn1";
  54. nvidia,function = "i2s0";
  55. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  56. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  57. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  58. };
  59. dap1_dout_pn2 {
  60. nvidia,pins = "dap1_dout_pn2",
  61. "dap1_fs_pn0",
  62. "dap1_sclk_pn3";
  63. nvidia,function = "i2s0";
  64. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  65. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  66. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  67. };
  68. dap2_din_pa4 {
  69. nvidia,pins = "dap2_din_pa4";
  70. nvidia,function = "i2s1";
  71. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  72. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  73. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  74. };
  75. dap2_dout_pa5 {
  76. nvidia,pins = "dap2_dout_pa5",
  77. "dap2_fs_pa2",
  78. "dap2_sclk_pa3";
  79. nvidia,function = "i2s1";
  80. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  81. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  82. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  83. };
  84. dap4_din_pp5 {
  85. nvidia,pins = "dap4_din_pp5",
  86. "dap4_dout_pp6",
  87. "dap4_fs_pp4",
  88. "dap4_sclk_pp7";
  89. nvidia,function = "i2s3";
  90. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  91. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  92. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  93. };
  94. dvfs_pwm_px0 {
  95. nvidia,pins = "dvfs_pwm_px0",
  96. "dvfs_clk_px2";
  97. nvidia,function = "cldvfs";
  98. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  99. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  100. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  101. };
  102. ulpi_clk_py0 {
  103. nvidia,pins = "ulpi_clk_py0",
  104. "ulpi_data0_po1",
  105. "ulpi_data1_po2",
  106. "ulpi_data2_po3",
  107. "ulpi_data3_po4",
  108. "ulpi_data4_po5",
  109. "ulpi_data5_po6",
  110. "ulpi_data6_po7",
  111. "ulpi_data7_po0";
  112. nvidia,function = "ulpi";
  113. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  114. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  115. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  116. };
  117. ulpi_dir_py1 {
  118. nvidia,pins = "ulpi_dir_py1",
  119. "ulpi_nxt_py2";
  120. nvidia,function = "ulpi";
  121. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  122. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  123. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  124. };
  125. ulpi_stp_py3 {
  126. nvidia,pins = "ulpi_stp_py3";
  127. nvidia,function = "ulpi";
  128. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  129. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  130. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  131. };
  132. cam_i2c_scl_pbb1 {
  133. nvidia,pins = "cam_i2c_scl_pbb1",
  134. "cam_i2c_sda_pbb2";
  135. nvidia,function = "i2c3";
  136. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  137. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  138. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  139. nvidia,lock = <TEGRA_PIN_DISABLE>;
  140. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  141. };
  142. cam_mclk_pcc0 {
  143. nvidia,pins = "cam_mclk_pcc0",
  144. "pbb0";
  145. nvidia,function = "vi_alt3";
  146. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  147. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  148. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  149. nvidia,lock = <TEGRA_PIN_DISABLE>;
  150. };
  151. gen2_i2c_scl_pt5 {
  152. nvidia,pins = "gen2_i2c_scl_pt5",
  153. "gen2_i2c_sda_pt6";
  154. nvidia,function = "i2c2";
  155. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  156. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  157. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  158. nvidia,lock = <TEGRA_PIN_DISABLE>;
  159. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  160. };
  161. gmi_a16_pj7 {
  162. nvidia,pins = "gmi_a16_pj7";
  163. nvidia,function = "uartd";
  164. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  165. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  166. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  167. };
  168. gmi_a17_pb0 {
  169. nvidia,pins = "gmi_a17_pb0",
  170. "gmi_a18_pb1";
  171. nvidia,function = "uartd";
  172. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  173. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  174. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  175. };
  176. gmi_a19_pk7 {
  177. nvidia,pins = "gmi_a19_pk7";
  178. nvidia,function = "uartd";
  179. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  180. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  181. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  182. };
  183. gmi_ad5_pg5 {
  184. nvidia,pins = "gmi_ad5_pg5",
  185. "gmi_cs6_n_pi3",
  186. "gmi_wr_n_pi0";
  187. nvidia,function = "spi4";
  188. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  189. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  190. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  191. };
  192. gmi_ad6_pg6 {
  193. nvidia,pins = "gmi_ad6_pg6",
  194. "gmi_ad7_pg7";
  195. nvidia,function = "spi4";
  196. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  197. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  198. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  199. };
  200. gmi_ad12_ph4 {
  201. nvidia,pins = "gmi_ad12_ph4";
  202. nvidia,function = "rsvd4";
  203. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  204. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  205. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  206. };
  207. gmi_ad9_ph1 {
  208. nvidia,pins = "gmi_ad9_ph1";
  209. nvidia,function = "pwm1";
  210. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  211. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  212. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  213. };
  214. gmi_cs1_n_pj2 {
  215. nvidia,pins = "gmi_cs1_n_pj2",
  216. "gmi_oe_n_pi1";
  217. nvidia,function = "soc";
  218. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  219. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  220. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  221. };
  222. clk2_out_pw5 {
  223. nvidia,pins = "clk2_out_pw5";
  224. nvidia,function = "extperiph2";
  225. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  226. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  227. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  228. };
  229. sdmmc1_clk_pz0 {
  230. nvidia,pins = "sdmmc1_clk_pz0";
  231. nvidia,function = "sdmmc1";
  232. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  233. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  234. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  235. };
  236. sdmmc1_cmd_pz1 {
  237. nvidia,pins = "sdmmc1_cmd_pz1",
  238. "sdmmc1_dat0_py7",
  239. "sdmmc1_dat1_py6",
  240. "sdmmc1_dat2_py5",
  241. "sdmmc1_dat3_py4";
  242. nvidia,function = "sdmmc1";
  243. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  244. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  245. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  246. };
  247. sdmmc1_wp_n_pv3 {
  248. nvidia,pins = "sdmmc1_wp_n_pv3";
  249. nvidia,function = "spi4";
  250. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  251. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  252. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  253. };
  254. sdmmc3_clk_pa6 {
  255. nvidia,pins = "sdmmc3_clk_pa6";
  256. nvidia,function = "sdmmc3";
  257. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  258. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  259. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  260. };
  261. sdmmc3_cmd_pa7 {
  262. nvidia,pins = "sdmmc3_cmd_pa7",
  263. "sdmmc3_dat0_pb7",
  264. "sdmmc3_dat1_pb6",
  265. "sdmmc3_dat2_pb5",
  266. "sdmmc3_dat3_pb4",
  267. "kb_col4_pq4",
  268. "sdmmc3_clk_lb_out_pee4",
  269. "sdmmc3_clk_lb_in_pee5";
  270. nvidia,function = "sdmmc3";
  271. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  272. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  273. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  274. };
  275. sdmmc4_clk_pcc4 {
  276. nvidia,pins = "sdmmc4_clk_pcc4";
  277. nvidia,function = "sdmmc4";
  278. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  279. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  280. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  281. };
  282. sdmmc4_cmd_pt7 {
  283. nvidia,pins = "sdmmc4_cmd_pt7",
  284. "sdmmc4_dat0_paa0",
  285. "sdmmc4_dat1_paa1",
  286. "sdmmc4_dat2_paa2",
  287. "sdmmc4_dat3_paa3",
  288. "sdmmc4_dat4_paa4",
  289. "sdmmc4_dat5_paa5",
  290. "sdmmc4_dat6_paa6",
  291. "sdmmc4_dat7_paa7";
  292. nvidia,function = "sdmmc4";
  293. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  294. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  295. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  296. };
  297. clk_32k_out_pa0 {
  298. nvidia,pins = "clk_32k_out_pa0";
  299. nvidia,function = "blink";
  300. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  301. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  302. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  303. };
  304. kb_col0_pq0 {
  305. nvidia,pins = "kb_col0_pq0",
  306. "kb_col1_pq1",
  307. "kb_col2_pq2",
  308. "kb_row0_pr0",
  309. "kb_row1_pr1",
  310. "kb_row2_pr2";
  311. nvidia,function = "kbc";
  312. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  313. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  314. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  315. };
  316. dap3_din_pp1 {
  317. nvidia,pins = "dap3_din_pp1",
  318. "dap3_sclk_pp3";
  319. nvidia,function = "displayb";
  320. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  321. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  322. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  323. };
  324. pv0 {
  325. nvidia,pins = "pv0";
  326. nvidia,function = "rsvd4";
  327. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  328. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  329. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  330. };
  331. kb_row7_pr7 {
  332. nvidia,pins = "kb_row7_pr7";
  333. nvidia,function = "rsvd2";
  334. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  335. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  336. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  337. };
  338. kb_row10_ps2 {
  339. nvidia,pins = "kb_row10_ps2";
  340. nvidia,function = "uarta";
  341. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  342. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  343. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  344. };
  345. kb_row9_ps1 {
  346. nvidia,pins = "kb_row9_ps1";
  347. nvidia,function = "uarta";
  348. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  349. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  350. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  351. };
  352. pwr_i2c_scl_pz6 {
  353. nvidia,pins = "pwr_i2c_scl_pz6",
  354. "pwr_i2c_sda_pz7";
  355. nvidia,function = "i2cpwr";
  356. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  357. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  358. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  359. nvidia,lock = <TEGRA_PIN_DISABLE>;
  360. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  361. };
  362. sys_clk_req_pz5 {
  363. nvidia,pins = "sys_clk_req_pz5";
  364. nvidia,function = "sysclk";
  365. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  366. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  367. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  368. };
  369. core_pwr_req {
  370. nvidia,pins = "core_pwr_req";
  371. nvidia,function = "pwron";
  372. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  373. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  374. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  375. };
  376. cpu_pwr_req {
  377. nvidia,pins = "cpu_pwr_req";
  378. nvidia,function = "cpu";
  379. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  380. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  381. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  382. };
  383. pwr_int_n {
  384. nvidia,pins = "pwr_int_n";
  385. nvidia,function = "pmi";
  386. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  387. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  388. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  389. };
  390. reset_out_n {
  391. nvidia,pins = "reset_out_n";
  392. nvidia,function = "reset_out_n";
  393. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  394. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  395. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  396. };
  397. clk3_out_pee0 {
  398. nvidia,pins = "clk3_out_pee0";
  399. nvidia,function = "extperiph3";
  400. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  401. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  402. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  403. };
  404. gen1_i2c_scl_pc4 {
  405. nvidia,pins = "gen1_i2c_scl_pc4",
  406. "gen1_i2c_sda_pc5";
  407. nvidia,function = "i2c1";
  408. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  409. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  410. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  411. nvidia,lock = <TEGRA_PIN_DISABLE>;
  412. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  413. };
  414. uart2_cts_n_pj5 {
  415. nvidia,pins = "uart2_cts_n_pj5";
  416. nvidia,function = "uartb";
  417. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  418. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  419. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  420. };
  421. uart2_rts_n_pj6 {
  422. nvidia,pins = "uart2_rts_n_pj6";
  423. nvidia,function = "uartb";
  424. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  425. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  426. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  427. };
  428. uart2_rxd_pc3 {
  429. nvidia,pins = "uart2_rxd_pc3";
  430. nvidia,function = "irda";
  431. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  432. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  433. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  434. };
  435. uart2_txd_pc2 {
  436. nvidia,pins = "uart2_txd_pc2";
  437. nvidia,function = "irda";
  438. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  439. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  440. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  441. };
  442. uart3_cts_n_pa1 {
  443. nvidia,pins = "uart3_cts_n_pa1",
  444. "uart3_rxd_pw7";
  445. nvidia,function = "uartc";
  446. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  447. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  448. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  449. };
  450. uart3_rts_n_pc0 {
  451. nvidia,pins = "uart3_rts_n_pc0",
  452. "uart3_txd_pw6";
  453. nvidia,function = "uartc";
  454. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  455. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  456. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  457. };
  458. owr {
  459. nvidia,pins = "owr";
  460. nvidia,function = "owr";
  461. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  462. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  463. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  464. };
  465. hdmi_cec_pee3 {
  466. nvidia,pins = "hdmi_cec_pee3";
  467. nvidia,function = "cec";
  468. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  469. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  470. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  471. nvidia,lock = <TEGRA_PIN_DISABLE>;
  472. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  473. };
  474. ddc_scl_pv4 {
  475. nvidia,pins = "ddc_scl_pv4",
  476. "ddc_sda_pv5";
  477. nvidia,function = "i2c4";
  478. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  479. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  480. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  481. nvidia,lock = <TEGRA_PIN_DISABLE>;
  482. nvidia,rcv-sel = <TEGRA_PIN_ENABLE>;
  483. };
  484. spdif_in_pk6 {
  485. nvidia,pins = "spdif_in_pk6";
  486. nvidia,function = "usb";
  487. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  488. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  489. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  490. nvidia,lock = <TEGRA_PIN_DISABLE>;
  491. };
  492. usb_vbus_en0_pn4 {
  493. nvidia,pins = "usb_vbus_en0_pn4";
  494. nvidia,function = "usb";
  495. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  496. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  497. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  498. nvidia,lock = <TEGRA_PIN_DISABLE>;
  499. nvidia,open-drain = <TEGRA_PIN_ENABLE>;
  500. };
  501. gpio_x6_aud_px6 {
  502. nvidia,pins = "gpio_x6_aud_px6";
  503. nvidia,function = "spi6";
  504. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  505. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  506. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  507. };
  508. gpio_x4_aud_px4 {
  509. nvidia,pins = "gpio_x4_aud_px4",
  510. "gpio_x7_aud_px7";
  511. nvidia,function = "rsvd1";
  512. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  513. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  514. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  515. };
  516. gpio_x5_aud_px5 {
  517. nvidia,pins = "gpio_x5_aud_px5";
  518. nvidia,function = "rsvd1";
  519. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  520. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  521. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  522. };
  523. gpio_w2_aud_pw2 {
  524. nvidia,pins = "gpio_w2_aud_pw2";
  525. nvidia,function = "rsvd2";
  526. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  527. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  528. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  529. };
  530. gpio_w3_aud_pw3 {
  531. nvidia,pins = "gpio_w3_aud_pw3";
  532. nvidia,function = "spi6";
  533. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  534. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  535. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  536. };
  537. gpio_x1_aud_px1 {
  538. nvidia,pins = "gpio_x1_aud_px1";
  539. nvidia,function = "rsvd4";
  540. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  541. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  542. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  543. };
  544. gpio_x3_aud_px3 {
  545. nvidia,pins = "gpio_x3_aud_px3";
  546. nvidia,function = "rsvd4";
  547. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  548. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  549. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  550. };
  551. dap3_fs_pp0 {
  552. nvidia,pins = "dap3_fs_pp0";
  553. nvidia,function = "i2s2";
  554. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  555. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  556. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  557. };
  558. dap3_dout_pp2 {
  559. nvidia,pins = "dap3_dout_pp2";
  560. nvidia,function = "i2s2";
  561. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  562. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  563. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  564. };
  565. pv1 {
  566. nvidia,pins = "pv1";
  567. nvidia,function = "rsvd1";
  568. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  569. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  570. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  571. };
  572. pbb3 {
  573. nvidia,pins = "pbb3",
  574. "pbb5",
  575. "pbb6",
  576. "pbb7";
  577. nvidia,function = "rsvd4";
  578. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  579. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  580. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  581. };
  582. pcc1 {
  583. nvidia,pins = "pcc1",
  584. "pcc2";
  585. nvidia,function = "rsvd4";
  586. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  587. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  588. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  589. };
  590. gmi_ad0_pg0 {
  591. nvidia,pins = "gmi_ad0_pg0",
  592. "gmi_ad1_pg1";
  593. nvidia,function = "gmi";
  594. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  595. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  596. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  597. };
  598. gmi_ad10_ph2 {
  599. nvidia,pins = "gmi_ad10_ph2",
  600. "gmi_ad11_ph3",
  601. "gmi_ad13_ph5",
  602. "gmi_ad8_ph0",
  603. "gmi_clk_pk1";
  604. nvidia,function = "gmi";
  605. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  606. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  607. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  608. };
  609. gmi_ad2_pg2 {
  610. nvidia,pins = "gmi_ad2_pg2",
  611. "gmi_ad3_pg3";
  612. nvidia,function = "gmi";
  613. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  614. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  615. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  616. };
  617. gmi_adv_n_pk0 {
  618. nvidia,pins = "gmi_adv_n_pk0",
  619. "gmi_cs0_n_pj0",
  620. "gmi_cs2_n_pk3",
  621. "gmi_cs4_n_pk2",
  622. "gmi_cs7_n_pi6",
  623. "gmi_dqs_p_pj3",
  624. "gmi_iordy_pi5",
  625. "gmi_wp_n_pc7";
  626. nvidia,function = "gmi";
  627. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  628. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  629. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  630. };
  631. gmi_cs3_n_pk4 {
  632. nvidia,pins = "gmi_cs3_n_pk4";
  633. nvidia,function = "gmi";
  634. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  635. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  636. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  637. };
  638. clk2_req_pcc5 {
  639. nvidia,pins = "clk2_req_pcc5";
  640. nvidia,function = "rsvd4";
  641. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  642. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  643. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  644. };
  645. kb_col3_pq3 {
  646. nvidia,pins = "kb_col3_pq3",
  647. "kb_col6_pq6",
  648. "kb_col7_pq7";
  649. nvidia,function = "kbc";
  650. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  651. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  652. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  653. };
  654. kb_col5_pq5 {
  655. nvidia,pins = "kb_col5_pq5";
  656. nvidia,function = "kbc";
  657. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  658. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  659. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  660. };
  661. kb_row3_pr3 {
  662. nvidia,pins = "kb_row3_pr3",
  663. "kb_row4_pr4",
  664. "kb_row6_pr6",
  665. "kb_row8_ps0";
  666. nvidia,function = "kbc";
  667. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  668. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  669. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  670. };
  671. clk3_req_pee1 {
  672. nvidia,pins = "clk3_req_pee1";
  673. nvidia,function = "rsvd4";
  674. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  675. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  676. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  677. };
  678. pu4 {
  679. nvidia,pins = "pu4";
  680. nvidia,function = "displayb";
  681. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  682. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  683. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  684. };
  685. pu5 {
  686. nvidia,pins = "pu5",
  687. "pu6";
  688. nvidia,function = "displayb";
  689. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  690. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  691. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  692. };
  693. hdmi_int_pn7 {
  694. nvidia,pins = "hdmi_int_pn7";
  695. nvidia,function = "rsvd1";
  696. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  697. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  698. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  699. };
  700. clk1_req_pee2 {
  701. nvidia,pins = "clk1_req_pee2",
  702. "usb_vbus_en1_pn5";
  703. nvidia,function = "rsvd4";
  704. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  705. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  706. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  707. };
  708. drive_sdio1 {
  709. nvidia,pins = "drive_sdio1";
  710. nvidia,high-speed-mode = <TEGRA_PIN_ENABLE>;
  711. nvidia,schmitt = <TEGRA_PIN_DISABLE>;
  712. nvidia,pull-down-strength = <36>;
  713. nvidia,pull-up-strength = <20>;
  714. nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_SLOW>;
  715. nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_SLOW>;
  716. };
  717. drive_sdio3 {
  718. nvidia,pins = "drive_sdio3";
  719. nvidia,high-speed-mode = <TEGRA_PIN_ENABLE>;
  720. nvidia,schmitt = <TEGRA_PIN_DISABLE>;
  721. nvidia,pull-down-strength = <22>;
  722. nvidia,pull-up-strength = <36>;
  723. nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_FASTEST>;
  724. nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_FASTEST>;
  725. };
  726. drive_gma {
  727. nvidia,pins = "drive_gma";
  728. nvidia,high-speed-mode = <TEGRA_PIN_ENABLE>;
  729. nvidia,schmitt = <TEGRA_PIN_DISABLE>;
  730. nvidia,pull-down-strength = <2>;
  731. nvidia,pull-up-strength = <1>;
  732. nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_FASTEST>;
  733. nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_FASTEST>;
  734. };
  735. };
  736. };
  737. serial@70006300 {
  738. status = "okay";
  739. };
  740. pwm@7000a000 {
  741. status = "okay";
  742. };
  743. i2c@7000c000 {
  744. status = "okay";
  745. clock-frequency = <100000>;
  746. battery: smart-battery@b {
  747. compatible = "ti,bq20z45", "sbs,sbs-battery";
  748. reg = <0xb>;
  749. battery-name = "battery";
  750. sbs,i2c-retry-count = <2>;
  751. sbs,poll-retry-count = <100>;
  752. power-supplies = <&charger>;
  753. };
  754. rt5640: rt5640@1c {
  755. compatible = "realtek,rt5640";
  756. reg = <0x1c>;
  757. interrupt-parent = <&gpio>;
  758. interrupts = <TEGRA_GPIO(W, 3) GPIO_ACTIVE_HIGH>;
  759. realtek,ldo1-en-gpios =
  760. <&gpio TEGRA_GPIO(V, 3) GPIO_ACTIVE_HIGH>;
  761. };
  762. temperature-sensor@4c {
  763. compatible = "onnn,nct1008";
  764. reg = <0x4c>;
  765. vcc-supply = <&palmas_ldo6_reg>;
  766. interrupt-parent = <&gpio>;
  767. interrupts = <TEGRA_GPIO(O, 4) IRQ_TYPE_LEVEL_LOW>;
  768. };
  769. };
  770. hdmi_ddc: i2c@7000c700 {
  771. status = "okay";
  772. };
  773. i2c@7000d000 {
  774. status = "okay";
  775. clock-frequency = <400000>;
  776. tps51632@43 {
  777. compatible = "ti,tps51632";
  778. reg = <0x43>;
  779. regulator-name = "vdd-cpu";
  780. regulator-min-microvolt = <500000>;
  781. regulator-max-microvolt = <1520000>;
  782. regulator-boot-on;
  783. regulator-always-on;
  784. };
  785. tps65090@48 {
  786. compatible = "ti,tps65090";
  787. reg = <0x48>;
  788. interrupt-parent = <&gpio>;
  789. interrupts = <TEGRA_GPIO(J, 0) IRQ_TYPE_LEVEL_HIGH>;
  790. vsys1-supply = <&vdd_ac_bat_reg>;
  791. vsys2-supply = <&vdd_ac_bat_reg>;
  792. vsys3-supply = <&vdd_ac_bat_reg>;
  793. infet1-supply = <&vdd_ac_bat_reg>;
  794. infet2-supply = <&vdd_ac_bat_reg>;
  795. infet3-supply = <&tps65090_dcdc2_reg>;
  796. infet4-supply = <&tps65090_dcdc2_reg>;
  797. infet5-supply = <&tps65090_dcdc2_reg>;
  798. infet6-supply = <&tps65090_dcdc2_reg>;
  799. infet7-supply = <&tps65090_dcdc2_reg>;
  800. vsys-l1-supply = <&vdd_ac_bat_reg>;
  801. vsys-l2-supply = <&vdd_ac_bat_reg>;
  802. charger: charger {
  803. compatible = "ti,tps65090-charger";
  804. ti,enable-low-current-chrg;
  805. };
  806. regulators {
  807. tps65090_dcdc1_reg: dcdc1 {
  808. regulator-name = "vdd-sys-5v0";
  809. regulator-always-on;
  810. regulator-boot-on;
  811. };
  812. tps65090_dcdc2_reg: dcdc2 {
  813. regulator-name = "vdd-sys-3v3";
  814. regulator-always-on;
  815. regulator-boot-on;
  816. };
  817. tps65090_dcdc3_reg: dcdc3 {
  818. regulator-name = "vdd-ao";
  819. regulator-always-on;
  820. regulator-boot-on;
  821. };
  822. vdd_bl_reg: fet1 {
  823. regulator-name = "vdd-lcd-bl";
  824. };
  825. fet3 {
  826. regulator-name = "vdd-modem-3v3";
  827. };
  828. avdd_lcd_reg: fet4 {
  829. regulator-name = "avdd-lcd";
  830. };
  831. fet5 {
  832. regulator-name = "vdd-lvds";
  833. };
  834. fet6 {
  835. regulator-name = "vdd-sd-slot";
  836. regulator-always-on;
  837. regulator-boot-on;
  838. };
  839. fet7 {
  840. regulator-name = "vdd-com-3v3";
  841. };
  842. ldo1 {
  843. regulator-name = "vdd-sby-5v0";
  844. regulator-always-on;
  845. regulator-boot-on;
  846. };
  847. ldo2 {
  848. regulator-name = "vdd-sby-3v3";
  849. regulator-always-on;
  850. regulator-boot-on;
  851. };
  852. };
  853. };
  854. palmas: tps65913@58 {
  855. compatible = "ti,palmas";
  856. reg = <0x58>;
  857. interrupts = <0 86 IRQ_TYPE_LEVEL_LOW>;
  858. #interrupt-cells = <2>;
  859. interrupt-controller;
  860. ti,system-power-controller;
  861. palmas_gpio: gpio {
  862. compatible = "ti,palmas-gpio";
  863. gpio-controller;
  864. #gpio-cells = <2>;
  865. };
  866. pmic {
  867. compatible = "ti,tps65913-pmic", "ti,palmas-pmic";
  868. smps1-in-supply = <&tps65090_dcdc3_reg>;
  869. smps3-in-supply = <&tps65090_dcdc3_reg>;
  870. smps4-in-supply = <&tps65090_dcdc2_reg>;
  871. smps7-in-supply = <&tps65090_dcdc2_reg>;
  872. smps8-in-supply = <&tps65090_dcdc2_reg>;
  873. smps9-in-supply = <&tps65090_dcdc2_reg>;
  874. ldo1-in-supply = <&tps65090_dcdc2_reg>;
  875. ldo2-in-supply = <&tps65090_dcdc2_reg>;
  876. ldo3-in-supply = <&palmas_smps3_reg>;
  877. ldo4-in-supply = <&tps65090_dcdc2_reg>;
  878. ldo5-in-supply = <&vdd_ac_bat_reg>;
  879. ldo6-in-supply = <&tps65090_dcdc2_reg>;
  880. ldo7-in-supply = <&tps65090_dcdc2_reg>;
  881. ldo8-in-supply = <&tps65090_dcdc3_reg>;
  882. ldo9-in-supply = <&palmas_smps9_reg>;
  883. ldoln-in-supply = <&tps65090_dcdc1_reg>;
  884. ldousb-in-supply = <&tps65090_dcdc1_reg>;
  885. regulators {
  886. smps12 {
  887. regulator-name = "vddio-ddr";
  888. regulator-min-microvolt = <1350000>;
  889. regulator-max-microvolt = <1350000>;
  890. regulator-always-on;
  891. regulator-boot-on;
  892. };
  893. palmas_smps3_reg: smps3 {
  894. regulator-name = "vddio-1v8";
  895. regulator-min-microvolt = <1800000>;
  896. regulator-max-microvolt = <1800000>;
  897. regulator-always-on;
  898. regulator-boot-on;
  899. };
  900. smps45 {
  901. regulator-name = "vdd-core";
  902. regulator-min-microvolt = <900000>;
  903. regulator-max-microvolt = <1400000>;
  904. regulator-always-on;
  905. regulator-boot-on;
  906. };
  907. smps457 {
  908. regulator-name = "vdd-core";
  909. regulator-min-microvolt = <900000>;
  910. regulator-max-microvolt = <1400000>;
  911. regulator-always-on;
  912. regulator-boot-on;
  913. };
  914. smps8 {
  915. regulator-name = "avdd-pll";
  916. regulator-min-microvolt = <1050000>;
  917. regulator-max-microvolt = <1050000>;
  918. regulator-always-on;
  919. regulator-boot-on;
  920. };
  921. palmas_smps9_reg: smps9 {
  922. regulator-name = "sdhci-vdd-sd-slot";
  923. regulator-min-microvolt = <2800000>;
  924. regulator-max-microvolt = <2800000>;
  925. regulator-always-on;
  926. };
  927. ldo1 {
  928. regulator-name = "avdd-cam1";
  929. regulator-min-microvolt = <2800000>;
  930. regulator-max-microvolt = <2800000>;
  931. };
  932. ldo2 {
  933. regulator-name = "avdd-cam2";
  934. regulator-min-microvolt = <2800000>;
  935. regulator-max-microvolt = <2800000>;
  936. };
  937. avdd_1v2_reg: ldo3 {
  938. regulator-name = "avdd-dsi-csi";
  939. regulator-min-microvolt = <1200000>;
  940. regulator-max-microvolt = <1200000>;
  941. };
  942. ldo4 {
  943. regulator-name = "vpp-fuse";
  944. regulator-min-microvolt = <1800000>;
  945. regulator-max-microvolt = <1800000>;
  946. };
  947. palmas_ldo6_reg: ldo6 {
  948. regulator-name = "vdd-sensor-2v85";
  949. regulator-min-microvolt = <2850000>;
  950. regulator-max-microvolt = <2850000>;
  951. };
  952. ldo7 {
  953. regulator-name = "vdd-af-cam1";
  954. regulator-min-microvolt = <2800000>;
  955. regulator-max-microvolt = <2800000>;
  956. };
  957. ldo8 {
  958. regulator-name = "vdd-rtc";
  959. regulator-min-microvolt = <900000>;
  960. regulator-max-microvolt = <900000>;
  961. regulator-always-on;
  962. regulator-boot-on;
  963. ti,enable-ldo8-tracking;
  964. };
  965. ldo9 {
  966. regulator-name = "vddio-sdmmc-2";
  967. regulator-min-microvolt = <1800000>;
  968. regulator-max-microvolt = <3300000>;
  969. regulator-always-on;
  970. regulator-boot-on;
  971. };
  972. ldoln {
  973. regulator-name = "hvdd-usb";
  974. regulator-min-microvolt = <3300000>;
  975. regulator-max-microvolt = <3300000>;
  976. };
  977. ldousb {
  978. regulator-name = "avdd-usb";
  979. regulator-min-microvolt = <3300000>;
  980. regulator-max-microvolt = <3300000>;
  981. regulator-always-on;
  982. regulator-boot-on;
  983. };
  984. regen1 {
  985. regulator-name = "rail-3v3";
  986. regulator-max-microvolt = <3300000>;
  987. regulator-always-on;
  988. regulator-boot-on;
  989. };
  990. regen2 {
  991. regulator-name = "rail-5v0";
  992. regulator-max-microvolt = <5000000>;
  993. regulator-always-on;
  994. regulator-boot-on;
  995. };
  996. };
  997. };
  998. rtc {
  999. compatible = "ti,palmas-rtc";
  1000. interrupt-parent = <&palmas>;
  1001. interrupts = <8 0>;
  1002. };
  1003. pinmux {
  1004. compatible = "ti,tps65913-pinctrl";
  1005. pinctrl-names = "default";
  1006. pinctrl-0 = <&palmas_default>;
  1007. palmas_default: pinmux {
  1008. pin_gpio6 {
  1009. pins = "gpio6";
  1010. function = "gpio";
  1011. };
  1012. };
  1013. };
  1014. };
  1015. };
  1016. spi@7000da00 {
  1017. status = "okay";
  1018. spi-max-frequency = <25000000>;
  1019. spi-flash@0 {
  1020. compatible = "winbond,w25q32dw";
  1021. reg = <0>;
  1022. spi-max-frequency = <20000000>;
  1023. };
  1024. };
  1025. pmc@7000e400 {
  1026. nvidia,invert-interrupt;
  1027. nvidia,suspend-mode = <1>;
  1028. nvidia,cpu-pwr-good-time = <500>;
  1029. nvidia,cpu-pwr-off-time = <300>;
  1030. nvidia,core-pwr-good-time = <641 3845>;
  1031. nvidia,core-pwr-off-time = <61036>;
  1032. nvidia,core-power-req-active-high;
  1033. nvidia,sys-clock-req-active-high;
  1034. };
  1035. ahub@70080000 {
  1036. i2s@70080400 {
  1037. status = "okay";
  1038. };
  1039. };
  1040. sdhci@78000400 {
  1041. cd-gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_LOW>;
  1042. wp-gpios = <&gpio TEGRA_GPIO(Q, 4) GPIO_ACTIVE_HIGH>;
  1043. bus-width = <4>;
  1044. status = "okay";
  1045. };
  1046. sdhci@78000600 {
  1047. bus-width = <8>;
  1048. status = "okay";
  1049. non-removable;
  1050. };
  1051. usb@7d008000 {
  1052. status = "okay";
  1053. };
  1054. usb-phy@7d008000 {
  1055. status = "okay";
  1056. vbus-supply = <&usb3_vbus_reg>;
  1057. };
  1058. backlight: backlight {
  1059. compatible = "pwm-backlight";
  1060. enable-gpios = <&gpio TEGRA_GPIO(H, 2) GPIO_ACTIVE_HIGH>;
  1061. power-supply = <&vdd_bl_reg>;
  1062. pwms = <&pwm 1 1000000>;
  1063. brightness-levels = <0 4 8 16 32 64 128 255>;
  1064. default-brightness-level = <6>;
  1065. };
  1066. clocks {
  1067. compatible = "simple-bus";
  1068. #address-cells = <1>;
  1069. #size-cells = <0>;
  1070. clk32k_in: clock@0 {
  1071. compatible = "fixed-clock";
  1072. reg=<0>;
  1073. #clock-cells = <0>;
  1074. clock-frequency = <32768>;
  1075. };
  1076. };
  1077. gpio-keys {
  1078. compatible = "gpio-keys";
  1079. home {
  1080. label = "Home";
  1081. gpios = <&gpio TEGRA_GPIO(I, 5) GPIO_ACTIVE_LOW>;
  1082. linux,code = <KEY_HOME>;
  1083. };
  1084. power {
  1085. label = "Power";
  1086. gpios = <&gpio TEGRA_GPIO(Q, 0) GPIO_ACTIVE_LOW>;
  1087. linux,code = <KEY_POWER>;
  1088. gpio-key,wakeup;
  1089. };
  1090. volume_down {
  1091. label = "Volume Down";
  1092. gpios = <&gpio TEGRA_GPIO(R, 1) GPIO_ACTIVE_LOW>;
  1093. linux,code = <KEY_VOLUMEDOWN>;
  1094. };
  1095. volume_up {
  1096. label = "Volume Up";
  1097. gpios = <&gpio TEGRA_GPIO(R, 2) GPIO_ACTIVE_LOW>;
  1098. linux,code = <KEY_VOLUMEUP>;
  1099. };
  1100. };
  1101. regulators {
  1102. compatible = "simple-bus";
  1103. #address-cells = <1>;
  1104. #size-cells = <0>;
  1105. vdd_ac_bat_reg: regulator@0 {
  1106. compatible = "regulator-fixed";
  1107. reg = <0>;
  1108. regulator-name = "vdd_ac_bat";
  1109. regulator-min-microvolt = <5000000>;
  1110. regulator-max-microvolt = <5000000>;
  1111. regulator-always-on;
  1112. };
  1113. dvdd_ts_reg: regulator@1 {
  1114. compatible = "regulator-fixed";
  1115. reg = <1>;
  1116. regulator-name = "dvdd_ts";
  1117. regulator-min-microvolt = <1800000>;
  1118. regulator-max-microvolt = <1800000>;
  1119. enable-active-high;
  1120. gpio = <&gpio TEGRA_GPIO(H, 5) GPIO_ACTIVE_HIGH>;
  1121. };
  1122. usb1_vbus_reg: regulator@3 {
  1123. compatible = "regulator-fixed";
  1124. reg = <3>;
  1125. regulator-name = "usb1_vbus";
  1126. regulator-min-microvolt = <5000000>;
  1127. regulator-max-microvolt = <5000000>;
  1128. enable-active-high;
  1129. gpio = <&gpio TEGRA_GPIO(N, 4) GPIO_ACTIVE_HIGH>;
  1130. gpio-open-drain;
  1131. vin-supply = <&tps65090_dcdc1_reg>;
  1132. };
  1133. usb3_vbus_reg: regulator@4 {
  1134. compatible = "regulator-fixed";
  1135. reg = <4>;
  1136. regulator-name = "usb2_vbus";
  1137. regulator-min-microvolt = <5000000>;
  1138. regulator-max-microvolt = <5000000>;
  1139. enable-active-high;
  1140. gpio = <&gpio TEGRA_GPIO(K, 6) GPIO_ACTIVE_HIGH>;
  1141. gpio-open-drain;
  1142. vin-supply = <&tps65090_dcdc1_reg>;
  1143. };
  1144. vdd_hdmi_reg: regulator@5 {
  1145. compatible = "regulator-fixed";
  1146. reg = <5>;
  1147. regulator-name = "vdd_hdmi_5v0";
  1148. regulator-min-microvolt = <5000000>;
  1149. regulator-max-microvolt = <5000000>;
  1150. vin-supply = <&tps65090_dcdc1_reg>;
  1151. };
  1152. vdd_cam_1v8_reg: regulator@6 {
  1153. compatible = "regulator-fixed";
  1154. reg = <6>;
  1155. regulator-name = "vdd_cam_1v8_reg";
  1156. regulator-min-microvolt = <1800000>;
  1157. regulator-max-microvolt = <1800000>;
  1158. enable-active-high;
  1159. gpio = <&palmas_gpio 6 0>;
  1160. };
  1161. vdd_5v0_hdmi: regulator@7 {
  1162. compatible = "regulator-fixed";
  1163. reg = <7>;
  1164. regulator-name = "VDD_5V0_HDMI_CON";
  1165. regulator-min-microvolt = <5000000>;
  1166. regulator-max-microvolt = <5000000>;
  1167. gpio = <&gpio TEGRA_GPIO(K, 1) GPIO_ACTIVE_HIGH>;
  1168. enable-active-high;
  1169. vin-supply = <&tps65090_dcdc1_reg>;
  1170. };
  1171. };
  1172. sound {
  1173. compatible = "nvidia,tegra-audio-rt5640-dalmore",
  1174. "nvidia,tegra-audio-rt5640";
  1175. nvidia,model = "NVIDIA Tegra Dalmore";
  1176. nvidia,audio-routing =
  1177. "Headphones", "HPOR",
  1178. "Headphones", "HPOL",
  1179. "Speakers", "SPORP",
  1180. "Speakers", "SPORN",
  1181. "Speakers", "SPOLP",
  1182. "Speakers", "SPOLN",
  1183. "Mic Jack", "MICBIAS1",
  1184. "IN2P", "Mic Jack";
  1185. nvidia,i2s-controller = <&tegra_i2s1>;
  1186. nvidia,audio-codec = <&rt5640>;
  1187. nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(R, 7) GPIO_ACTIVE_HIGH>;
  1188. clocks = <&tegra_car TEGRA114_CLK_PLL_A>,
  1189. <&tegra_car TEGRA114_CLK_PLL_A_OUT0>,
  1190. <&tegra_car TEGRA114_CLK_EXTERN1>;
  1191. clock-names = "pll_a", "pll_a_out0", "mclk";
  1192. };
  1193. };