tegra124-jetson-tk1.dts 54 KB

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  1. /dts-v1/;
  2. #include <dt-bindings/input/input.h>
  3. #include "tegra124.dtsi"
  4. / {
  5. model = "NVIDIA Tegra124 Jetson TK1";
  6. compatible = "nvidia,jetson-tk1", "nvidia,tegra124";
  7. aliases {
  8. rtc0 = "/i2c@0,7000d000/pmic@40";
  9. rtc1 = "/rtc@0,7000e000";
  10. serial0 = &uartd;
  11. };
  12. memory {
  13. reg = <0x0 0x80000000 0x0 0x80000000>;
  14. };
  15. pcie-controller@0,01003000 {
  16. status = "okay";
  17. avddio-pex-supply = <&vdd_1v05_run>;
  18. dvddio-pex-supply = <&vdd_1v05_run>;
  19. avdd-pex-pll-supply = <&vdd_1v05_run>;
  20. hvdd-pex-supply = <&vdd_3v3_lp0>;
  21. hvdd-pex-pll-e-supply = <&vdd_3v3_lp0>;
  22. vddio-pex-ctl-supply = <&vdd_3v3_lp0>;
  23. avdd-pll-erefe-supply = <&avdd_1v05_run>;
  24. pci@1,0 {
  25. status = "okay";
  26. };
  27. pci@2,0 {
  28. status = "okay";
  29. };
  30. };
  31. host1x@0,50000000 {
  32. hdmi@0,54280000 {
  33. status = "okay";
  34. hdmi-supply = <&vdd_5v0_hdmi>;
  35. pll-supply = <&vdd_hdmi_pll>;
  36. vdd-supply = <&vdd_3v3_hdmi>;
  37. nvidia,ddc-i2c-bus = <&hdmi_ddc>;
  38. nvidia,hpd-gpio =
  39. <&gpio TEGRA_GPIO(N, 7) GPIO_ACTIVE_HIGH>;
  40. };
  41. };
  42. pinmux: pinmux@0,70000868 {
  43. pinctrl-names = "boot";
  44. pinctrl-0 = <&state_boot>;
  45. state_boot: pinmux {
  46. clk_32k_out_pa0 {
  47. nvidia,pins = "clk_32k_out_pa0";
  48. nvidia,function = "soc";
  49. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  50. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  51. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  52. };
  53. uart3_cts_n_pa1 {
  54. nvidia,pins = "uart3_cts_n_pa1";
  55. nvidia,function = "uartc";
  56. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  57. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  58. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  59. };
  60. dap2_fs_pa2 {
  61. nvidia,pins = "dap2_fs_pa2";
  62. nvidia,function = "i2s1";
  63. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  64. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  65. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  66. };
  67. dap2_sclk_pa3 {
  68. nvidia,pins = "dap2_sclk_pa3";
  69. nvidia,function = "i2s1";
  70. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  71. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  72. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  73. };
  74. dap2_din_pa4 {
  75. nvidia,pins = "dap2_din_pa4";
  76. nvidia,function = "i2s1";
  77. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  78. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  79. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  80. };
  81. dap2_dout_pa5 {
  82. nvidia,pins = "dap2_dout_pa5";
  83. nvidia,function = "i2s1";
  84. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  85. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  86. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  87. };
  88. sdmmc3_clk_pa6 {
  89. nvidia,pins = "sdmmc3_clk_pa6";
  90. nvidia,function = "sdmmc3";
  91. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  92. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  93. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  94. };
  95. sdmmc3_cmd_pa7 {
  96. nvidia,pins = "sdmmc3_cmd_pa7";
  97. nvidia,function = "sdmmc3";
  98. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  99. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  100. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  101. };
  102. pb0 {
  103. nvidia,pins = "pb0";
  104. nvidia,function = "uartd";
  105. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  106. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  107. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  108. };
  109. pb1 {
  110. nvidia,pins = "pb1";
  111. nvidia,function = "uartd";
  112. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  113. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  114. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  115. };
  116. sdmmc3_dat3_pb4 {
  117. nvidia,pins = "sdmmc3_dat3_pb4";
  118. nvidia,function = "sdmmc3";
  119. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  120. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  121. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  122. };
  123. sdmmc3_dat2_pb5 {
  124. nvidia,pins = "sdmmc3_dat2_pb5";
  125. nvidia,function = "sdmmc3";
  126. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  127. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  128. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  129. };
  130. sdmmc3_dat1_pb6 {
  131. nvidia,pins = "sdmmc3_dat1_pb6";
  132. nvidia,function = "sdmmc3";
  133. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  134. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  135. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  136. };
  137. sdmmc3_dat0_pb7 {
  138. nvidia,pins = "sdmmc3_dat0_pb7";
  139. nvidia,function = "sdmmc3";
  140. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  141. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  142. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  143. };
  144. uart3_rts_n_pc0 {
  145. nvidia,pins = "uart3_rts_n_pc0";
  146. nvidia,function = "uartc";
  147. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  148. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  149. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  150. };
  151. uart2_txd_pc2 {
  152. nvidia,pins = "uart2_txd_pc2";
  153. nvidia,function = "irda";
  154. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  155. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  156. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  157. };
  158. uart2_rxd_pc3 {
  159. nvidia,pins = "uart2_rxd_pc3";
  160. nvidia,function = "irda";
  161. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  162. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  163. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  164. };
  165. gen1_i2c_scl_pc4 {
  166. nvidia,pins = "gen1_i2c_scl_pc4";
  167. nvidia,function = "i2c1";
  168. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  169. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  170. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  171. nvidia,open-drain = <TEGRA_PIN_ENABLE>;
  172. };
  173. gen1_i2c_sda_pc5 {
  174. nvidia,pins = "gen1_i2c_sda_pc5";
  175. nvidia,function = "i2c1";
  176. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  177. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  178. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  179. nvidia,open-drain = <TEGRA_PIN_ENABLE>;
  180. };
  181. pc7 {
  182. nvidia,pins = "pc7";
  183. nvidia,function = "rsvd1";
  184. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  185. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  186. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  187. };
  188. pg0 {
  189. nvidia,pins = "pg0";
  190. nvidia,function = "rsvd1";
  191. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  192. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  193. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  194. };
  195. pg1 {
  196. nvidia,pins = "pg1";
  197. nvidia,function = "rsvd1";
  198. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  199. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  200. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  201. };
  202. pg2 {
  203. nvidia,pins = "pg2";
  204. nvidia,function = "rsvd1";
  205. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  206. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  207. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  208. };
  209. pg3 {
  210. nvidia,pins = "pg3";
  211. nvidia,function = "rsvd1";
  212. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  213. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  214. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  215. };
  216. pg4 {
  217. nvidia,pins = "pg4";
  218. nvidia,function = "spi4";
  219. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  220. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  221. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  222. };
  223. pg5 {
  224. nvidia,pins = "pg5";
  225. nvidia,function = "spi4";
  226. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  227. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  228. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  229. };
  230. pg6 {
  231. nvidia,pins = "pg6";
  232. nvidia,function = "spi4";
  233. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  234. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  235. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  236. };
  237. pg7 {
  238. nvidia,pins = "pg7";
  239. nvidia,function = "spi4";
  240. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  241. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  242. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  243. };
  244. ph0 {
  245. nvidia,pins = "ph0";
  246. nvidia,function = "gmi";
  247. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  248. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  249. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  250. };
  251. ph1 {
  252. nvidia,pins = "ph1";
  253. nvidia,function = "pwm1";
  254. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  255. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  256. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  257. };
  258. ph2 {
  259. nvidia,pins = "ph2";
  260. nvidia,function = "gmi";
  261. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  262. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  263. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  264. };
  265. ph3 {
  266. nvidia,pins = "ph3";
  267. nvidia,function = "gmi";
  268. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  269. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  270. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  271. };
  272. ph4 {
  273. nvidia,pins = "ph4";
  274. nvidia,function = "rsvd2";
  275. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  276. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  277. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  278. };
  279. ph5 {
  280. nvidia,pins = "ph5";
  281. nvidia,function = "rsvd2";
  282. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  283. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  284. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  285. };
  286. ph6 {
  287. nvidia,pins = "ph6";
  288. nvidia,function = "gmi";
  289. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  290. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  291. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  292. };
  293. ph7 {
  294. nvidia,pins = "ph7";
  295. nvidia,function = "gmi";
  296. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  297. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  298. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  299. };
  300. pi0 {
  301. nvidia,pins = "pi0";
  302. nvidia,function = "rsvd1";
  303. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  304. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  305. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  306. };
  307. pi1 {
  308. nvidia,pins = "pi1";
  309. nvidia,function = "rsvd1";
  310. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  311. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  312. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  313. };
  314. pi2 {
  315. nvidia,pins = "pi2";
  316. nvidia,function = "rsvd4";
  317. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  318. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  319. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  320. };
  321. pi3 {
  322. nvidia,pins = "pi3";
  323. nvidia,function = "spi4";
  324. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  325. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  326. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  327. };
  328. pi4 {
  329. nvidia,pins = "pi4";
  330. nvidia,function = "gmi";
  331. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  332. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  333. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  334. };
  335. pi5 {
  336. nvidia,pins = "pi5";
  337. nvidia,function = "rsvd2";
  338. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  339. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  340. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  341. };
  342. pi6 {
  343. nvidia,pins = "pi6";
  344. nvidia,function = "rsvd1";
  345. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  346. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  347. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  348. };
  349. pi7 {
  350. nvidia,pins = "pi7";
  351. nvidia,function = "rsvd1";
  352. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  353. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  354. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  355. };
  356. pj0 {
  357. nvidia,pins = "pj0";
  358. nvidia,function = "rsvd1";
  359. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  360. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  361. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  362. };
  363. pj2 {
  364. nvidia,pins = "pj2";
  365. nvidia,function = "rsvd1";
  366. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  367. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  368. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  369. };
  370. uart2_cts_n_pj5 {
  371. nvidia,pins = "uart2_cts_n_pj5";
  372. nvidia,function = "uartb";
  373. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  374. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  375. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  376. };
  377. uart2_rts_n_pj6 {
  378. nvidia,pins = "uart2_rts_n_pj6";
  379. nvidia,function = "uartb";
  380. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  381. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  382. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  383. };
  384. pj7 {
  385. nvidia,pins = "pj7";
  386. nvidia,function = "uartd";
  387. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  388. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  389. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  390. };
  391. pk0 {
  392. nvidia,pins = "pk0";
  393. nvidia,function = "soc";
  394. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  395. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  396. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  397. };
  398. pk1 {
  399. nvidia,pins = "pk1";
  400. nvidia,function = "rsvd4";
  401. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  402. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  403. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  404. };
  405. pk2 {
  406. nvidia,pins = "pk2";
  407. nvidia,function = "rsvd1";
  408. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  409. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  410. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  411. };
  412. pk3 {
  413. nvidia,pins = "pk3";
  414. nvidia,function = "gmi";
  415. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  416. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  417. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  418. };
  419. pk4 {
  420. nvidia,pins = "pk4";
  421. nvidia,function = "rsvd2";
  422. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  423. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  424. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  425. };
  426. spdif_out_pk5 {
  427. nvidia,pins = "spdif_out_pk5";
  428. nvidia,function = "rsvd2";
  429. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  430. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  431. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  432. };
  433. spdif_in_pk6 {
  434. nvidia,pins = "spdif_in_pk6";
  435. nvidia,function = "rsvd2";
  436. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  437. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  438. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  439. };
  440. pk7 {
  441. nvidia,pins = "pk7";
  442. nvidia,function = "uartd";
  443. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  444. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  445. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  446. };
  447. dap1_fs_pn0 {
  448. nvidia,pins = "dap1_fs_pn0";
  449. nvidia,function = "i2s0";
  450. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  451. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  452. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  453. };
  454. dap1_din_pn1 {
  455. nvidia,pins = "dap1_din_pn1";
  456. nvidia,function = "i2s0";
  457. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  458. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  459. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  460. };
  461. dap1_dout_pn2 {
  462. nvidia,pins = "dap1_dout_pn2";
  463. nvidia,function = "sata";
  464. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  465. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  466. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  467. };
  468. dap1_sclk_pn3 {
  469. nvidia,pins = "dap1_sclk_pn3";
  470. nvidia,function = "i2s0";
  471. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  472. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  473. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  474. };
  475. usb_vbus_en0_pn4 {
  476. nvidia,pins = "usb_vbus_en0_pn4";
  477. nvidia,function = "usb";
  478. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  479. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  480. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  481. nvidia,open-drain = <TEGRA_PIN_ENABLE>;
  482. };
  483. usb_vbus_en1_pn5 {
  484. nvidia,pins = "usb_vbus_en1_pn5";
  485. nvidia,function = "usb";
  486. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  487. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  488. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  489. nvidia,open-drain = <TEGRA_PIN_ENABLE>;
  490. };
  491. hdmi_int_pn7 {
  492. nvidia,pins = "hdmi_int_pn7";
  493. nvidia,function = "rsvd1";
  494. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  495. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  496. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  497. nvidia,rcv-sel = <TEGRA_PIN_DISABLE>;
  498. };
  499. ulpi_data7_po0 {
  500. nvidia,pins = "ulpi_data7_po0";
  501. nvidia,function = "ulpi";
  502. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  503. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  504. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  505. };
  506. ulpi_data0_po1 {
  507. nvidia,pins = "ulpi_data0_po1";
  508. nvidia,function = "ulpi";
  509. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  510. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  511. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  512. };
  513. ulpi_data1_po2 {
  514. nvidia,pins = "ulpi_data1_po2";
  515. nvidia,function = "ulpi";
  516. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  517. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  518. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  519. };
  520. ulpi_data2_po3 {
  521. nvidia,pins = "ulpi_data2_po3";
  522. nvidia,function = "ulpi";
  523. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  524. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  525. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  526. };
  527. ulpi_data3_po4 {
  528. nvidia,pins = "ulpi_data3_po4";
  529. nvidia,function = "ulpi";
  530. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  531. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  532. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  533. };
  534. ulpi_data4_po5 {
  535. nvidia,pins = "ulpi_data4_po5";
  536. nvidia,function = "ulpi";
  537. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  538. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  539. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  540. };
  541. ulpi_data5_po6 {
  542. nvidia,pins = "ulpi_data5_po6";
  543. nvidia,function = "ulpi";
  544. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  545. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  546. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  547. };
  548. ulpi_data6_po7 {
  549. nvidia,pins = "ulpi_data6_po7";
  550. nvidia,function = "ulpi";
  551. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  552. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  553. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  554. };
  555. dap3_fs_pp0 {
  556. nvidia,pins = "dap3_fs_pp0";
  557. nvidia,function = "i2s2";
  558. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  559. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  560. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  561. };
  562. dap3_din_pp1 {
  563. nvidia,pins = "dap3_din_pp1";
  564. nvidia,function = "i2s2";
  565. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  566. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  567. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  568. };
  569. dap3_dout_pp2 {
  570. nvidia,pins = "dap3_dout_pp2";
  571. nvidia,function = "rsvd4";
  572. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  573. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  574. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  575. };
  576. dap3_sclk_pp3 {
  577. nvidia,pins = "dap3_sclk_pp3";
  578. nvidia,function = "rsvd3";
  579. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  580. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  581. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  582. };
  583. dap4_fs_pp4 {
  584. nvidia,pins = "dap4_fs_pp4";
  585. nvidia,function = "i2s3";
  586. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  587. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  588. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  589. };
  590. dap4_din_pp5 {
  591. nvidia,pins = "dap4_din_pp5";
  592. nvidia,function = "i2s3";
  593. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  594. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  595. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  596. };
  597. dap4_dout_pp6 {
  598. nvidia,pins = "dap4_dout_pp6";
  599. nvidia,function = "i2s3";
  600. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  601. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  602. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  603. };
  604. dap4_sclk_pp7 {
  605. nvidia,pins = "dap4_sclk_pp7";
  606. nvidia,function = "i2s3";
  607. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  608. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  609. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  610. };
  611. kb_col0_pq0 {
  612. nvidia,pins = "kb_col0_pq0";
  613. nvidia,function = "rsvd2";
  614. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  615. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  616. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  617. };
  618. kb_col1_pq1 {
  619. nvidia,pins = "kb_col1_pq1";
  620. nvidia,function = "rsvd2";
  621. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  622. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  623. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  624. };
  625. kb_col2_pq2 {
  626. nvidia,pins = "kb_col2_pq2";
  627. nvidia,function = "rsvd2";
  628. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  629. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  630. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  631. };
  632. kb_col3_pq3 {
  633. nvidia,pins = "kb_col3_pq3";
  634. nvidia,function = "kbc";
  635. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  636. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  637. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  638. };
  639. kb_col4_pq4 {
  640. nvidia,pins = "kb_col4_pq4";
  641. nvidia,function = "sdmmc3";
  642. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  643. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  644. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  645. };
  646. kb_col5_pq5 {
  647. nvidia,pins = "kb_col5_pq5";
  648. nvidia,function = "rsvd2";
  649. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  650. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  651. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  652. };
  653. kb_col6_pq6 {
  654. nvidia,pins = "kb_col6_pq6";
  655. nvidia,function = "rsvd2";
  656. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  657. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  658. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  659. };
  660. kb_col7_pq7 {
  661. nvidia,pins = "kb_col7_pq7";
  662. nvidia,function = "rsvd2";
  663. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  664. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  665. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  666. };
  667. kb_row0_pr0 {
  668. nvidia,pins = "kb_row0_pr0";
  669. nvidia,function = "rsvd2";
  670. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  671. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  672. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  673. };
  674. kb_row1_pr1 {
  675. nvidia,pins = "kb_row1_pr1";
  676. nvidia,function = "rsvd2";
  677. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  678. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  679. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  680. };
  681. kb_row2_pr2 {
  682. nvidia,pins = "kb_row2_pr2";
  683. nvidia,function = "rsvd2";
  684. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  685. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  686. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  687. };
  688. kb_row3_pr3 {
  689. nvidia,pins = "kb_row3_pr3";
  690. nvidia,function = "sys";
  691. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  692. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  693. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  694. };
  695. kb_row4_pr4 {
  696. nvidia,pins = "kb_row4_pr4";
  697. nvidia,function = "rsvd3";
  698. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  699. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  700. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  701. };
  702. kb_row5_pr5 {
  703. nvidia,pins = "kb_row5_pr5";
  704. nvidia,function = "rsvd3";
  705. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  706. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  707. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  708. };
  709. kb_row6_pr6 {
  710. nvidia,pins = "kb_row6_pr6";
  711. nvidia,function = "displaya_alt";
  712. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  713. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  714. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  715. };
  716. kb_row7_pr7 {
  717. nvidia,pins = "kb_row7_pr7";
  718. nvidia,function = "rsvd2";
  719. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  720. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  721. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  722. };
  723. kb_row8_ps0 {
  724. nvidia,pins = "kb_row8_ps0";
  725. nvidia,function = "rsvd2";
  726. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  727. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  728. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  729. };
  730. kb_row9_ps1 {
  731. nvidia,pins = "kb_row9_ps1";
  732. nvidia,function = "rsvd2";
  733. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  734. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  735. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  736. };
  737. kb_row10_ps2 {
  738. nvidia,pins = "kb_row10_ps2";
  739. nvidia,function = "rsvd2";
  740. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  741. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  742. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  743. };
  744. kb_row11_ps3 {
  745. nvidia,pins = "kb_row11_ps3";
  746. nvidia,function = "rsvd2";
  747. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  748. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  749. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  750. };
  751. kb_row12_ps4 {
  752. nvidia,pins = "kb_row12_ps4";
  753. nvidia,function = "rsvd2";
  754. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  755. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  756. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  757. };
  758. kb_row13_ps5 {
  759. nvidia,pins = "kb_row13_ps5";
  760. nvidia,function = "rsvd2";
  761. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  762. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  763. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  764. };
  765. kb_row14_ps6 {
  766. nvidia,pins = "kb_row14_ps6";
  767. nvidia,function = "rsvd2";
  768. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  769. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  770. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  771. };
  772. kb_row15_ps7 {
  773. nvidia,pins = "kb_row15_ps7";
  774. nvidia,function = "soc";
  775. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  776. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  777. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  778. };
  779. kb_row16_pt0 {
  780. nvidia,pins = "kb_row16_pt0";
  781. nvidia,function = "rsvd2";
  782. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  783. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  784. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  785. };
  786. kb_row17_pt1 {
  787. nvidia,pins = "kb_row17_pt1";
  788. nvidia,function = "rsvd2";
  789. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  790. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  791. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  792. };
  793. gen2_i2c_scl_pt5 {
  794. nvidia,pins = "gen2_i2c_scl_pt5";
  795. nvidia,function = "i2c2";
  796. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  797. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  798. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  799. nvidia,open-drain = <TEGRA_PIN_ENABLE>;
  800. };
  801. gen2_i2c_sda_pt6 {
  802. nvidia,pins = "gen2_i2c_sda_pt6";
  803. nvidia,function = "i2c2";
  804. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  805. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  806. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  807. nvidia,open-drain = <TEGRA_PIN_ENABLE>;
  808. };
  809. sdmmc4_cmd_pt7 {
  810. nvidia,pins = "sdmmc4_cmd_pt7";
  811. nvidia,function = "sdmmc4";
  812. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  813. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  814. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  815. };
  816. pu0 {
  817. nvidia,pins = "pu0";
  818. nvidia,function = "rsvd4";
  819. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  820. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  821. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  822. };
  823. pu1 {
  824. nvidia,pins = "pu1";
  825. nvidia,function = "rsvd1";
  826. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  827. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  828. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  829. };
  830. pu2 {
  831. nvidia,pins = "pu2";
  832. nvidia,function = "rsvd1";
  833. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  834. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  835. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  836. };
  837. pu3 {
  838. nvidia,pins = "pu3";
  839. nvidia,function = "gmi";
  840. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  841. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  842. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  843. };
  844. pu4 {
  845. nvidia,pins = "pu4";
  846. nvidia,function = "gmi";
  847. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  848. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  849. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  850. };
  851. pu5 {
  852. nvidia,pins = "pu5";
  853. nvidia,function = "gmi";
  854. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  855. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  856. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  857. };
  858. pu6 {
  859. nvidia,pins = "pu6";
  860. nvidia,function = "rsvd3";
  861. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  862. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  863. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  864. };
  865. pv0 {
  866. nvidia,pins = "pv0";
  867. nvidia,function = "rsvd1";
  868. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  869. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  870. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  871. };
  872. pv1 {
  873. nvidia,pins = "pv1";
  874. nvidia,function = "rsvd1";
  875. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  876. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  877. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  878. };
  879. sdmmc3_cd_n_pv2 {
  880. nvidia,pins = "sdmmc3_cd_n_pv2";
  881. nvidia,function = "sdmmc3";
  882. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  883. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  884. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  885. };
  886. sdmmc1_wp_n_pv3 {
  887. nvidia,pins = "sdmmc1_wp_n_pv3";
  888. nvidia,function = "sdmmc1";
  889. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  890. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  891. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  892. };
  893. ddc_scl_pv4 {
  894. nvidia,pins = "ddc_scl_pv4";
  895. nvidia,function = "i2c4";
  896. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  897. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  898. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  899. nvidia,rcv-sel = <TEGRA_PIN_DISABLE>;
  900. };
  901. ddc_sda_pv5 {
  902. nvidia,pins = "ddc_sda_pv5";
  903. nvidia,function = "i2c4";
  904. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  905. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  906. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  907. nvidia,rcv-sel = <TEGRA_PIN_DISABLE>;
  908. };
  909. gpio_w2_aud_pw2 {
  910. nvidia,pins = "gpio_w2_aud_pw2";
  911. nvidia,function = "rsvd2";
  912. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  913. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  914. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  915. };
  916. gpio_w3_aud_pw3 {
  917. nvidia,pins = "gpio_w3_aud_pw3";
  918. nvidia,function = "spi6";
  919. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  920. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  921. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  922. };
  923. dap_mclk1_pw4 {
  924. nvidia,pins = "dap_mclk1_pw4";
  925. nvidia,function = "extperiph1";
  926. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  927. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  928. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  929. };
  930. clk2_out_pw5 {
  931. nvidia,pins = "clk2_out_pw5";
  932. nvidia,function = "extperiph2";
  933. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  934. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  935. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  936. };
  937. uart3_txd_pw6 {
  938. nvidia,pins = "uart3_txd_pw6";
  939. nvidia,function = "uartc";
  940. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  941. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  942. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  943. };
  944. uart3_rxd_pw7 {
  945. nvidia,pins = "uart3_rxd_pw7";
  946. nvidia,function = "uartc";
  947. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  948. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  949. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  950. };
  951. dvfs_pwm_px0 {
  952. nvidia,pins = "dvfs_pwm_px0";
  953. nvidia,function = "cldvfs";
  954. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  955. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  956. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  957. };
  958. gpio_x1_aud_px1 {
  959. nvidia,pins = "gpio_x1_aud_px1";
  960. nvidia,function = "rsvd2";
  961. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  962. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  963. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  964. };
  965. dvfs_clk_px2 {
  966. nvidia,pins = "dvfs_clk_px2";
  967. nvidia,function = "cldvfs";
  968. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  969. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  970. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  971. };
  972. gpio_x3_aud_px3 {
  973. nvidia,pins = "gpio_x3_aud_px3";
  974. nvidia,function = "rsvd4";
  975. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  976. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  977. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  978. };
  979. gpio_x4_aud_px4 {
  980. nvidia,pins = "gpio_x4_aud_px4";
  981. nvidia,function = "gmi";
  982. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  983. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  984. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  985. };
  986. gpio_x5_aud_px5 {
  987. nvidia,pins = "gpio_x5_aud_px5";
  988. nvidia,function = "rsvd4";
  989. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  990. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  991. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  992. };
  993. gpio_x6_aud_px6 {
  994. nvidia,pins = "gpio_x6_aud_px6";
  995. nvidia,function = "gmi";
  996. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  997. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  998. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  999. };
  1000. gpio_x7_aud_px7 {
  1001. nvidia,pins = "gpio_x7_aud_px7";
  1002. nvidia,function = "rsvd1";
  1003. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  1004. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1005. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1006. };
  1007. ulpi_clk_py0 {
  1008. nvidia,pins = "ulpi_clk_py0";
  1009. nvidia,function = "spi1";
  1010. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  1011. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1012. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1013. };
  1014. ulpi_dir_py1 {
  1015. nvidia,pins = "ulpi_dir_py1";
  1016. nvidia,function = "spi1";
  1017. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  1018. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1019. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  1020. };
  1021. ulpi_nxt_py2 {
  1022. nvidia,pins = "ulpi_nxt_py2";
  1023. nvidia,function = "spi1";
  1024. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  1025. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1026. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1027. };
  1028. ulpi_stp_py3 {
  1029. nvidia,pins = "ulpi_stp_py3";
  1030. nvidia,function = "spi1";
  1031. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  1032. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1033. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1034. };
  1035. sdmmc1_dat3_py4 {
  1036. nvidia,pins = "sdmmc1_dat3_py4";
  1037. nvidia,function = "sdmmc1";
  1038. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  1039. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1040. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  1041. };
  1042. sdmmc1_dat2_py5 {
  1043. nvidia,pins = "sdmmc1_dat2_py5";
  1044. nvidia,function = "sdmmc1";
  1045. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  1046. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1047. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  1048. };
  1049. sdmmc1_dat1_py6 {
  1050. nvidia,pins = "sdmmc1_dat1_py6";
  1051. nvidia,function = "sdmmc1";
  1052. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  1053. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1054. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  1055. };
  1056. sdmmc1_dat0_py7 {
  1057. nvidia,pins = "sdmmc1_dat0_py7";
  1058. nvidia,function = "sdmmc1";
  1059. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  1060. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1061. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  1062. };
  1063. sdmmc1_clk_pz0 {
  1064. nvidia,pins = "sdmmc1_clk_pz0";
  1065. nvidia,function = "sdmmc1";
  1066. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  1067. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1068. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  1069. };
  1070. sdmmc1_cmd_pz1 {
  1071. nvidia,pins = "sdmmc1_cmd_pz1";
  1072. nvidia,function = "sdmmc1";
  1073. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  1074. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1075. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  1076. };
  1077. pwr_i2c_scl_pz6 {
  1078. nvidia,pins = "pwr_i2c_scl_pz6";
  1079. nvidia,function = "i2cpwr";
  1080. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  1081. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1082. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  1083. nvidia,open-drain = <TEGRA_PIN_ENABLE>;
  1084. };
  1085. pwr_i2c_sda_pz7 {
  1086. nvidia,pins = "pwr_i2c_sda_pz7";
  1087. nvidia,function = "i2cpwr";
  1088. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  1089. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1090. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  1091. nvidia,open-drain = <TEGRA_PIN_ENABLE>;
  1092. };
  1093. sdmmc4_dat0_paa0 {
  1094. nvidia,pins = "sdmmc4_dat0_paa0";
  1095. nvidia,function = "sdmmc4";
  1096. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  1097. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1098. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  1099. };
  1100. sdmmc4_dat1_paa1 {
  1101. nvidia,pins = "sdmmc4_dat1_paa1";
  1102. nvidia,function = "sdmmc4";
  1103. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  1104. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1105. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  1106. };
  1107. sdmmc4_dat2_paa2 {
  1108. nvidia,pins = "sdmmc4_dat2_paa2";
  1109. nvidia,function = "sdmmc4";
  1110. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  1111. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1112. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  1113. };
  1114. sdmmc4_dat3_paa3 {
  1115. nvidia,pins = "sdmmc4_dat3_paa3";
  1116. nvidia,function = "sdmmc4";
  1117. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  1118. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1119. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  1120. };
  1121. sdmmc4_dat4_paa4 {
  1122. nvidia,pins = "sdmmc4_dat4_paa4";
  1123. nvidia,function = "sdmmc4";
  1124. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  1125. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1126. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  1127. };
  1128. sdmmc4_dat5_paa5 {
  1129. nvidia,pins = "sdmmc4_dat5_paa5";
  1130. nvidia,function = "sdmmc4";
  1131. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  1132. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1133. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  1134. };
  1135. sdmmc4_dat6_paa6 {
  1136. nvidia,pins = "sdmmc4_dat6_paa6";
  1137. nvidia,function = "sdmmc4";
  1138. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  1139. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1140. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  1141. };
  1142. sdmmc4_dat7_paa7 {
  1143. nvidia,pins = "sdmmc4_dat7_paa7";
  1144. nvidia,function = "sdmmc4";
  1145. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  1146. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1147. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  1148. };
  1149. pbb0 {
  1150. nvidia,pins = "pbb0";
  1151. nvidia,function = "vimclk2_alt";
  1152. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  1153. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1154. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1155. };
  1156. cam_i2c_scl_pbb1 {
  1157. nvidia,pins = "cam_i2c_scl_pbb1";
  1158. nvidia,function = "i2c3";
  1159. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  1160. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1161. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  1162. nvidia,open-drain = <TEGRA_PIN_ENABLE>;
  1163. };
  1164. cam_i2c_sda_pbb2 {
  1165. nvidia,pins = "cam_i2c_sda_pbb2";
  1166. nvidia,function = "i2c3";
  1167. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  1168. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1169. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  1170. nvidia,open-drain = <TEGRA_PIN_ENABLE>;
  1171. };
  1172. pbb3 {
  1173. nvidia,pins = "pbb3";
  1174. nvidia,function = "vgp3";
  1175. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  1176. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1177. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1178. };
  1179. pbb4 {
  1180. nvidia,pins = "pbb4";
  1181. nvidia,function = "vgp4";
  1182. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  1183. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1184. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1185. };
  1186. pbb5 {
  1187. nvidia,pins = "pbb5";
  1188. nvidia,function = "rsvd3";
  1189. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  1190. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1191. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1192. };
  1193. pbb6 {
  1194. nvidia,pins = "pbb6";
  1195. nvidia,function = "rsvd2";
  1196. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  1197. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1198. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1199. };
  1200. pbb7 {
  1201. nvidia,pins = "pbb7";
  1202. nvidia,function = "rsvd2";
  1203. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  1204. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1205. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1206. };
  1207. cam_mclk_pcc0 {
  1208. nvidia,pins = "cam_mclk_pcc0";
  1209. nvidia,function = "vi_alt3";
  1210. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  1211. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1212. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1213. };
  1214. pcc1 {
  1215. nvidia,pins = "pcc1";
  1216. nvidia,function = "rsvd2";
  1217. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  1218. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1219. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  1220. };
  1221. pcc2 {
  1222. nvidia,pins = "pcc2";
  1223. nvidia,function = "rsvd2";
  1224. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  1225. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1226. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  1227. };
  1228. sdmmc4_clk_pcc4 {
  1229. nvidia,pins = "sdmmc4_clk_pcc4";
  1230. nvidia,function = "sdmmc4";
  1231. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  1232. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1233. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  1234. };
  1235. clk2_req_pcc5 {
  1236. nvidia,pins = "clk2_req_pcc5";
  1237. nvidia,function = "rsvd2";
  1238. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  1239. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1240. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1241. };
  1242. pex_l0_rst_n_pdd1 {
  1243. nvidia,pins = "pex_l0_rst_n_pdd1";
  1244. nvidia,function = "pe0";
  1245. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  1246. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1247. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1248. };
  1249. pex_l0_clkreq_n_pdd2 {
  1250. nvidia,pins = "pex_l0_clkreq_n_pdd2";
  1251. nvidia,function = "pe0";
  1252. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  1253. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1254. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  1255. };
  1256. pex_wake_n_pdd3 {
  1257. nvidia,pins = "pex_wake_n_pdd3";
  1258. nvidia,function = "pe";
  1259. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  1260. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1261. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  1262. };
  1263. pex_l1_rst_n_pdd5 {
  1264. nvidia,pins = "pex_l1_rst_n_pdd5";
  1265. nvidia,function = "pe1";
  1266. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  1267. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1268. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1269. };
  1270. pex_l1_clkreq_n_pdd6 {
  1271. nvidia,pins = "pex_l1_clkreq_n_pdd6";
  1272. nvidia,function = "pe1";
  1273. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  1274. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1275. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  1276. };
  1277. clk3_out_pee0 {
  1278. nvidia,pins = "clk3_out_pee0";
  1279. nvidia,function = "extperiph3";
  1280. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  1281. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1282. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1283. };
  1284. clk3_req_pee1 {
  1285. nvidia,pins = "clk3_req_pee1";
  1286. nvidia,function = "rsvd2";
  1287. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  1288. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1289. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1290. };
  1291. dap_mclk1_req_pee2 {
  1292. nvidia,pins = "dap_mclk1_req_pee2";
  1293. nvidia,function = "sata";
  1294. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  1295. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1296. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1297. };
  1298. hdmi_cec_pee3 {
  1299. nvidia,pins = "hdmi_cec_pee3";
  1300. nvidia,function = "cec";
  1301. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  1302. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1303. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  1304. nvidia,open-drain = <TEGRA_PIN_ENABLE>;
  1305. };
  1306. sdmmc3_clk_lb_out_pee4 {
  1307. nvidia,pins = "sdmmc3_clk_lb_out_pee4";
  1308. nvidia,function = "sdmmc3";
  1309. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  1310. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1311. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  1312. };
  1313. sdmmc3_clk_lb_in_pee5 {
  1314. nvidia,pins = "sdmmc3_clk_lb_in_pee5";
  1315. nvidia,function = "sdmmc3";
  1316. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  1317. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1318. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  1319. };
  1320. dp_hpd_pff0 {
  1321. nvidia,pins = "dp_hpd_pff0";
  1322. nvidia,function = "dp";
  1323. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  1324. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1325. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  1326. };
  1327. usb_vbus_en2_pff1 {
  1328. nvidia,pins = "usb_vbus_en2_pff1";
  1329. nvidia,function = "rsvd2";
  1330. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  1331. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1332. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1333. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  1334. };
  1335. pff2 {
  1336. nvidia,pins = "pff2";
  1337. nvidia,function = "rsvd2";
  1338. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  1339. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1340. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  1341. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  1342. };
  1343. core_pwr_req {
  1344. nvidia,pins = "core_pwr_req";
  1345. nvidia,function = "pwron";
  1346. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  1347. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1348. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1349. };
  1350. cpu_pwr_req {
  1351. nvidia,pins = "cpu_pwr_req";
  1352. nvidia,function = "rsvd2";
  1353. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  1354. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1355. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1356. };
  1357. pwr_int_n {
  1358. nvidia,pins = "pwr_int_n";
  1359. nvidia,function = "pmi";
  1360. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  1361. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1362. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  1363. };
  1364. reset_out_n {
  1365. nvidia,pins = "reset_out_n";
  1366. nvidia,function = "reset_out_n";
  1367. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  1368. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1369. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1370. };
  1371. owr {
  1372. nvidia,pins = "owr";
  1373. nvidia,function = "rsvd2";
  1374. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  1375. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  1376. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1377. nvidia,rcv-sel = <TEGRA_PIN_DISABLE>;
  1378. };
  1379. clk_32k_in {
  1380. nvidia,pins = "clk_32k_in";
  1381. nvidia,function = "rsvd2";
  1382. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  1383. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1384. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  1385. };
  1386. jtag_rtck {
  1387. nvidia,pins = "jtag_rtck";
  1388. nvidia,function = "rtck";
  1389. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  1390. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1391. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1392. };
  1393. };
  1394. };
  1395. /* DB9 serial port */
  1396. serial@0,70006300 {
  1397. status = "okay";
  1398. };
  1399. /* Expansion GEN1_I2C_*, mini-PCIe I2C, on-board components */
  1400. i2c@0,7000c000 {
  1401. status = "okay";
  1402. clock-frequency = <100000>;
  1403. rt5639: audio-codec@1c {
  1404. compatible = "realtek,rt5639";
  1405. reg = <0x1c>;
  1406. interrupt-parent = <&gpio>;
  1407. interrupts = <TEGRA_GPIO(H, 4) GPIO_ACTIVE_HIGH>;
  1408. realtek,ldo1-en-gpios =
  1409. <&gpio TEGRA_GPIO(R, 2) GPIO_ACTIVE_HIGH>;
  1410. };
  1411. temperature-sensor@4c {
  1412. compatible = "ti,tmp451";
  1413. reg = <0x4c>;
  1414. interrupt-parent = <&gpio>;
  1415. interrupts = <TEGRA_GPIO(I, 6) IRQ_TYPE_LEVEL_LOW>;
  1416. };
  1417. eeprom@56 {
  1418. compatible = "atmel,24c02";
  1419. reg = <0x56>;
  1420. pagesize = <8>;
  1421. };
  1422. };
  1423. /* Expansion GEN2_I2C_* */
  1424. i2c@0,7000c400 {
  1425. status = "okay";
  1426. clock-frequency = <100000>;
  1427. };
  1428. /* Expansion CAM_I2C_* */
  1429. i2c@0,7000c500 {
  1430. status = "okay";
  1431. clock-frequency = <100000>;
  1432. };
  1433. /* HDMI DDC */
  1434. hdmi_ddc: i2c@0,7000c700 {
  1435. status = "okay";
  1436. clock-frequency = <100000>;
  1437. };
  1438. /* Expansion PWR_I2C_*, on-board components */
  1439. i2c@0,7000d000 {
  1440. status = "okay";
  1441. clock-frequency = <400000>;
  1442. pmic: pmic@40 {
  1443. compatible = "ams,as3722";
  1444. reg = <0x40>;
  1445. interrupts = <0 86 IRQ_TYPE_LEVEL_HIGH>;
  1446. ams,system-power-controller;
  1447. #interrupt-cells = <2>;
  1448. interrupt-controller;
  1449. gpio-controller;
  1450. #gpio-cells = <2>;
  1451. pinctrl-names = "default";
  1452. pinctrl-0 = <&as3722_default>;
  1453. as3722_default: pinmux {
  1454. gpio0 {
  1455. pins = "gpio0";
  1456. function = "gpio";
  1457. bias-pull-down;
  1458. };
  1459. gpio1_2_4_7 {
  1460. pins = "gpio1", "gpio2", "gpio4", "gpio7";
  1461. function = "gpio";
  1462. bias-pull-up;
  1463. };
  1464. gpio3_5_6 {
  1465. pins = "gpio3", "gpio5", "gpio6";
  1466. bias-high-impedance;
  1467. };
  1468. };
  1469. regulators {
  1470. vsup-sd2-supply = <&vdd_5v0_sys>;
  1471. vsup-sd3-supply = <&vdd_5v0_sys>;
  1472. vsup-sd4-supply = <&vdd_5v0_sys>;
  1473. vsup-sd5-supply = <&vdd_5v0_sys>;
  1474. vin-ldo0-supply = <&vdd_1v35_lp0>;
  1475. vin-ldo1-6-supply = <&vdd_3v3_run>;
  1476. vin-ldo2-5-7-supply = <&vddio_1v8>;
  1477. vin-ldo3-4-supply = <&vdd_3v3_sys>;
  1478. vin-ldo9-10-supply = <&vdd_5v0_sys>;
  1479. vin-ldo11-supply = <&vdd_3v3_run>;
  1480. sd0 {
  1481. regulator-name = "+VDD_CPU_AP";
  1482. regulator-min-microvolt = <700000>;
  1483. regulator-max-microvolt = <1400000>;
  1484. regulator-min-microamp = <3500000>;
  1485. regulator-max-microamp = <3500000>;
  1486. regulator-always-on;
  1487. regulator-boot-on;
  1488. ams,ext-control = <2>;
  1489. };
  1490. sd1 {
  1491. regulator-name = "+VDD_CORE";
  1492. regulator-min-microvolt = <700000>;
  1493. regulator-max-microvolt = <1350000>;
  1494. regulator-min-microamp = <2500000>;
  1495. regulator-max-microamp = <2500000>;
  1496. regulator-always-on;
  1497. regulator-boot-on;
  1498. ams,ext-control = <1>;
  1499. };
  1500. vdd_1v35_lp0: sd2 {
  1501. regulator-name = "+1.35V_LP0(sd2)";
  1502. regulator-min-microvolt = <1350000>;
  1503. regulator-max-microvolt = <1350000>;
  1504. regulator-always-on;
  1505. regulator-boot-on;
  1506. };
  1507. sd3 {
  1508. regulator-name = "+1.35V_LP0(sd3)";
  1509. regulator-min-microvolt = <1350000>;
  1510. regulator-max-microvolt = <1350000>;
  1511. regulator-always-on;
  1512. regulator-boot-on;
  1513. };
  1514. vdd_1v05_run: sd4 {
  1515. regulator-name = "+1.05V_RUN";
  1516. regulator-min-microvolt = <1050000>;
  1517. regulator-max-microvolt = <1050000>;
  1518. };
  1519. vddio_1v8: sd5 {
  1520. regulator-name = "+1.8V_VDDIO";
  1521. regulator-min-microvolt = <1800000>;
  1522. regulator-max-microvolt = <1800000>;
  1523. regulator-boot-on;
  1524. regulator-always-on;
  1525. };
  1526. sd6 {
  1527. regulator-name = "+VDD_GPU_AP";
  1528. regulator-min-microvolt = <650000>;
  1529. regulator-max-microvolt = <1200000>;
  1530. regulator-min-microamp = <3500000>;
  1531. regulator-max-microamp = <3500000>;
  1532. regulator-boot-on;
  1533. regulator-always-on;
  1534. };
  1535. avdd_1v05_run: ldo0 {
  1536. regulator-name = "+1.05V_RUN_AVDD";
  1537. regulator-min-microvolt = <1050000>;
  1538. regulator-max-microvolt = <1050000>;
  1539. regulator-boot-on;
  1540. regulator-always-on;
  1541. ams,ext-control = <1>;
  1542. };
  1543. ldo1 {
  1544. regulator-name = "+1.8V_RUN_CAM";
  1545. regulator-min-microvolt = <1800000>;
  1546. regulator-max-microvolt = <1800000>;
  1547. };
  1548. ldo2 {
  1549. regulator-name = "+1.2V_GEN_AVDD";
  1550. regulator-min-microvolt = <1200000>;
  1551. regulator-max-microvolt = <1200000>;
  1552. regulator-boot-on;
  1553. regulator-always-on;
  1554. };
  1555. ldo3 {
  1556. regulator-name = "+1.05V_LP0_VDD_RTC";
  1557. regulator-min-microvolt = <1000000>;
  1558. regulator-max-microvolt = <1000000>;
  1559. regulator-boot-on;
  1560. regulator-always-on;
  1561. ams,enable-tracking;
  1562. };
  1563. ldo4 {
  1564. regulator-name = "+2.8V_RUN_CAM";
  1565. regulator-min-microvolt = <2800000>;
  1566. regulator-max-microvolt = <2800000>;
  1567. };
  1568. ldo5 {
  1569. regulator-name = "+1.2V_RUN_CAM_FRONT";
  1570. regulator-min-microvolt = <1200000>;
  1571. regulator-max-microvolt = <1200000>;
  1572. };
  1573. vddio_sdmmc3: ldo6 {
  1574. regulator-name = "+VDDIO_SDMMC3";
  1575. regulator-min-microvolt = <1800000>;
  1576. regulator-max-microvolt = <3300000>;
  1577. };
  1578. ldo7 {
  1579. regulator-name = "+1.05V_RUN_CAM_REAR";
  1580. regulator-min-microvolt = <1050000>;
  1581. regulator-max-microvolt = <1050000>;
  1582. };
  1583. ldo9 {
  1584. regulator-name = "+3.3V_RUN_TOUCH";
  1585. regulator-min-microvolt = <2800000>;
  1586. regulator-max-microvolt = <2800000>;
  1587. };
  1588. ldo10 {
  1589. regulator-name = "+2.8V_RUN_CAM_AF";
  1590. regulator-min-microvolt = <2800000>;
  1591. regulator-max-microvolt = <2800000>;
  1592. };
  1593. ldo11 {
  1594. regulator-name = "+1.8V_RUN_VPP_FUSE";
  1595. regulator-min-microvolt = <1800000>;
  1596. regulator-max-microvolt = <1800000>;
  1597. };
  1598. };
  1599. };
  1600. };
  1601. /* Expansion TS_SPI_* */
  1602. spi@0,7000d400 {
  1603. status = "okay";
  1604. };
  1605. /* Internal SPI */
  1606. spi@0,7000da00 {
  1607. status = "okay";
  1608. spi-max-frequency = <25000000>;
  1609. spi-flash@0 {
  1610. compatible = "winbond,w25q32dw";
  1611. reg = <0>;
  1612. spi-max-frequency = <20000000>;
  1613. };
  1614. };
  1615. pmc@0,7000e400 {
  1616. nvidia,invert-interrupt;
  1617. nvidia,suspend-mode = <1>;
  1618. nvidia,cpu-pwr-good-time = <500>;
  1619. nvidia,cpu-pwr-off-time = <300>;
  1620. nvidia,core-pwr-good-time = <641 3845>;
  1621. nvidia,core-pwr-off-time = <61036>;
  1622. nvidia,core-power-req-active-high;
  1623. nvidia,sys-clock-req-active-high;
  1624. };
  1625. /* Serial ATA */
  1626. sata@0,70020000 {
  1627. status = "okay";
  1628. hvdd-supply = <&vdd_3v3_lp0>;
  1629. vddio-supply = <&vdd_1v05_run>;
  1630. avdd-supply = <&vdd_1v05_run>;
  1631. target-5v-supply = <&vdd_5v0_sata>;
  1632. target-12v-supply = <&vdd_12v0_sata>;
  1633. };
  1634. padctl@0,7009f000 {
  1635. pinctrl-0 = <&padctl_default>;
  1636. pinctrl-names = "default";
  1637. padctl_default: pinmux {
  1638. usb3 {
  1639. nvidia,lanes = "pcie-0", "pcie-1";
  1640. nvidia,function = "usb3";
  1641. nvidia,iddq = <0>;
  1642. };
  1643. pcie {
  1644. nvidia,lanes = "pcie-2", "pcie-3",
  1645. "pcie-4";
  1646. nvidia,function = "pcie";
  1647. nvidia,iddq = <0>;
  1648. };
  1649. sata {
  1650. nvidia,lanes = "sata-0";
  1651. nvidia,function = "sata";
  1652. nvidia,iddq = <0>;
  1653. };
  1654. };
  1655. };
  1656. /* SD card */
  1657. sdhci@0,700b0400 {
  1658. status = "okay";
  1659. cd-gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_LOW>;
  1660. power-gpios = <&gpio TEGRA_GPIO(R, 0) GPIO_ACTIVE_HIGH>;
  1661. wp-gpios = <&gpio TEGRA_GPIO(Q, 4) GPIO_ACTIVE_HIGH>;
  1662. bus-width = <4>;
  1663. vqmmc-supply = <&vddio_sdmmc3>;
  1664. };
  1665. /* eMMC */
  1666. sdhci@0,700b0600 {
  1667. status = "okay";
  1668. bus-width = <8>;
  1669. non-removable;
  1670. };
  1671. ahub@0,70300000 {
  1672. i2s@0,70301100 {
  1673. status = "okay";
  1674. };
  1675. };
  1676. /* mini-PCIe USB */
  1677. usb@0,7d004000 {
  1678. status = "okay";
  1679. };
  1680. usb-phy@0,7d004000 {
  1681. status = "okay";
  1682. };
  1683. /* USB A connector */
  1684. usb@0,7d008000 {
  1685. status = "okay";
  1686. };
  1687. usb-phy@0,7d008000 {
  1688. status = "okay";
  1689. vbus-supply = <&vdd_usb3_vbus>;
  1690. };
  1691. clocks {
  1692. compatible = "simple-bus";
  1693. #address-cells = <1>;
  1694. #size-cells = <0>;
  1695. clk32k_in: clock@0 {
  1696. compatible = "fixed-clock";
  1697. reg = <0>;
  1698. #clock-cells = <0>;
  1699. clock-frequency = <32768>;
  1700. };
  1701. };
  1702. gpio-keys {
  1703. compatible = "gpio-keys";
  1704. power {
  1705. label = "Power";
  1706. gpios = <&gpio TEGRA_GPIO(Q, 0) GPIO_ACTIVE_LOW>;
  1707. linux,code = <KEY_POWER>;
  1708. debounce-interval = <10>;
  1709. gpio-key,wakeup;
  1710. };
  1711. };
  1712. regulators {
  1713. compatible = "simple-bus";
  1714. #address-cells = <1>;
  1715. #size-cells = <0>;
  1716. vdd_mux: regulator@0 {
  1717. compatible = "regulator-fixed";
  1718. reg = <0>;
  1719. regulator-name = "+VDD_MUX";
  1720. regulator-min-microvolt = <12000000>;
  1721. regulator-max-microvolt = <12000000>;
  1722. regulator-always-on;
  1723. regulator-boot-on;
  1724. };
  1725. vdd_5v0_sys: regulator@1 {
  1726. compatible = "regulator-fixed";
  1727. reg = <1>;
  1728. regulator-name = "+5V_SYS";
  1729. regulator-min-microvolt = <5000000>;
  1730. regulator-max-microvolt = <5000000>;
  1731. regulator-always-on;
  1732. regulator-boot-on;
  1733. vin-supply = <&vdd_mux>;
  1734. };
  1735. vdd_3v3_sys: regulator@2 {
  1736. compatible = "regulator-fixed";
  1737. reg = <2>;
  1738. regulator-name = "+3.3V_SYS";
  1739. regulator-min-microvolt = <3300000>;
  1740. regulator-max-microvolt = <3300000>;
  1741. regulator-always-on;
  1742. regulator-boot-on;
  1743. vin-supply = <&vdd_mux>;
  1744. };
  1745. vdd_3v3_run: regulator@3 {
  1746. compatible = "regulator-fixed";
  1747. reg = <3>;
  1748. regulator-name = "+3.3V_RUN";
  1749. regulator-min-microvolt = <3300000>;
  1750. regulator-max-microvolt = <3300000>;
  1751. regulator-always-on;
  1752. regulator-boot-on;
  1753. gpio = <&pmic 1 GPIO_ACTIVE_HIGH>;
  1754. enable-active-high;
  1755. vin-supply = <&vdd_3v3_sys>;
  1756. };
  1757. vdd_3v3_hdmi: regulator@4 {
  1758. compatible = "regulator-fixed";
  1759. reg = <4>;
  1760. regulator-name = "+3.3V_AVDD_HDMI_AP_GATED";
  1761. regulator-min-microvolt = <3300000>;
  1762. regulator-max-microvolt = <3300000>;
  1763. vin-supply = <&vdd_3v3_run>;
  1764. };
  1765. vdd_usb1_vbus: regulator@7 {
  1766. compatible = "regulator-fixed";
  1767. reg = <7>;
  1768. regulator-name = "+USB0_VBUS_SW";
  1769. regulator-min-microvolt = <5000000>;
  1770. regulator-max-microvolt = <5000000>;
  1771. gpio = <&gpio TEGRA_GPIO(N, 4) GPIO_ACTIVE_HIGH>;
  1772. enable-active-high;
  1773. gpio-open-drain;
  1774. vin-supply = <&vdd_5v0_sys>;
  1775. };
  1776. vdd_usb3_vbus: regulator@8 {
  1777. compatible = "regulator-fixed";
  1778. reg = <8>;
  1779. regulator-name = "+5V_USB_HS";
  1780. regulator-min-microvolt = <5000000>;
  1781. regulator-max-microvolt = <5000000>;
  1782. gpio = <&gpio TEGRA_GPIO(N, 5) GPIO_ACTIVE_HIGH>;
  1783. enable-active-high;
  1784. gpio-open-drain;
  1785. vin-supply = <&vdd_5v0_sys>;
  1786. };
  1787. vdd_3v3_lp0: regulator@10 {
  1788. compatible = "regulator-fixed";
  1789. reg = <10>;
  1790. regulator-name = "+3.3V_LP0";
  1791. regulator-min-microvolt = <3300000>;
  1792. regulator-max-microvolt = <3300000>;
  1793. regulator-always-on;
  1794. regulator-boot-on;
  1795. gpio = <&pmic 2 GPIO_ACTIVE_HIGH>;
  1796. enable-active-high;
  1797. vin-supply = <&vdd_3v3_sys>;
  1798. };
  1799. vdd_hdmi_pll: regulator@11 {
  1800. compatible = "regulator-fixed";
  1801. reg = <11>;
  1802. regulator-name = "+1.05V_RUN_AVDD_HDMI_PLL";
  1803. regulator-min-microvolt = <1050000>;
  1804. regulator-max-microvolt = <1050000>;
  1805. gpio = <&gpio TEGRA_GPIO(H, 7) GPIO_ACTIVE_LOW>;
  1806. vin-supply = <&vdd_1v05_run>;
  1807. };
  1808. vdd_5v0_hdmi: regulator@12 {
  1809. compatible = "regulator-fixed";
  1810. reg = <12>;
  1811. regulator-name = "+5V_HDMI_CON";
  1812. regulator-min-microvolt = <5000000>;
  1813. regulator-max-microvolt = <5000000>;
  1814. gpio = <&gpio TEGRA_GPIO(K, 6) GPIO_ACTIVE_HIGH>;
  1815. enable-active-high;
  1816. vin-supply = <&vdd_5v0_sys>;
  1817. };
  1818. /* Molex power connector */
  1819. vdd_5v0_sata: regulator@13 {
  1820. compatible = "regulator-fixed";
  1821. reg = <13>;
  1822. regulator-name = "+5V_SATA";
  1823. regulator-min-microvolt = <5000000>;
  1824. regulator-max-microvolt = <5000000>;
  1825. gpio = <&gpio TEGRA_GPIO(EE, 2) GPIO_ACTIVE_HIGH>;
  1826. enable-active-high;
  1827. vin-supply = <&vdd_5v0_sys>;
  1828. };
  1829. vdd_12v0_sata: regulator@14 {
  1830. compatible = "regulator-fixed";
  1831. reg = <14>;
  1832. regulator-name = "+12V_SATA";
  1833. regulator-min-microvolt = <12000000>;
  1834. regulator-max-microvolt = <12000000>;
  1835. gpio = <&gpio TEGRA_GPIO(EE, 2) GPIO_ACTIVE_HIGH>;
  1836. enable-active-high;
  1837. vin-supply = <&vdd_mux>;
  1838. };
  1839. };
  1840. sound {
  1841. compatible = "nvidia,tegra-audio-rt5640-jetson-tk1",
  1842. "nvidia,tegra-audio-rt5640";
  1843. nvidia,model = "NVIDIA Tegra Jetson TK1";
  1844. nvidia,audio-routing =
  1845. "Headphones", "HPOR",
  1846. "Headphones", "HPOL",
  1847. "Mic Jack", "MICBIAS1",
  1848. "IN2P", "Mic Jack";
  1849. nvidia,i2s-controller = <&tegra_i2s1>;
  1850. nvidia,audio-codec = <&rt5639>;
  1851. nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(R, 7) GPIO_ACTIVE_LOW>;
  1852. clocks = <&tegra_car TEGRA124_CLK_PLL_A>,
  1853. <&tegra_car TEGRA124_CLK_PLL_A_OUT0>,
  1854. <&tegra_car TEGRA124_CLK_EXTERN1>;
  1855. clock-names = "pll_a", "pll_a_out0", "mclk";
  1856. };
  1857. };