tegra124-nyan-big.dts 29 KB

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  1. /dts-v1/;
  2. #include <dt-bindings/input/input.h>
  3. #include "tegra124.dtsi"
  4. / {
  5. model = "Acer Chromebook 13 CB5-311";
  6. compatible = "google,nyan-big", "nvidia,tegra124";
  7. aliases {
  8. rtc0 = "/i2c@0,7000d000/pmic@40";
  9. rtc1 = "/rtc@0,7000e000";
  10. serial0 = &uarta;
  11. };
  12. memory {
  13. reg = <0x0 0x80000000 0x0 0x80000000>;
  14. };
  15. host1x@0,50000000 {
  16. hdmi@0,54280000 {
  17. status = "okay";
  18. vdd-supply = <&vdd_3v3_hdmi>;
  19. pll-supply = <&vdd_hdmi_pll>;
  20. hdmi-supply = <&vdd_5v0_hdmi>;
  21. nvidia,ddc-i2c-bus = <&hdmi_ddc>;
  22. nvidia,hpd-gpio =
  23. <&gpio TEGRA_GPIO(N, 7) GPIO_ACTIVE_HIGH>;
  24. };
  25. sor@0,54540000 {
  26. status = "okay";
  27. nvidia,dpaux = <&dpaux>;
  28. nvidia,panel = <&panel>;
  29. };
  30. dpaux@0,545c0000 {
  31. vdd-supply = <&vdd_3v3_panel>;
  32. status = "okay";
  33. };
  34. };
  35. pinmux@0,70000868 {
  36. pinctrl-names = "default";
  37. pinctrl-0 = <&pinmux_default>;
  38. pinmux_default: common {
  39. dap_mclk1_pw4 {
  40. nvidia,pins = "dap_mclk1_pw4";
  41. nvidia,function = "extperiph1";
  42. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  43. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  44. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  45. };
  46. dap2_din_pa4 {
  47. nvidia,pins = "dap2_din_pa4";
  48. nvidia,function = "i2s1";
  49. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  50. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  51. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  52. };
  53. dap2_dout_pa5 {
  54. nvidia,pins = "dap2_dout_pa5",
  55. "dap2_fs_pa2",
  56. "dap2_sclk_pa3";
  57. nvidia,function = "i2s1";
  58. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  59. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  60. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  61. };
  62. dvfs_pwm_px0 {
  63. nvidia,pins = "dvfs_pwm_px0",
  64. "dvfs_clk_px2";
  65. nvidia,function = "cldvfs";
  66. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  67. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  68. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  69. };
  70. ulpi_clk_py0 {
  71. nvidia,pins = "ulpi_clk_py0",
  72. "ulpi_nxt_py2",
  73. "ulpi_stp_py3";
  74. nvidia,function = "spi1";
  75. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  76. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  77. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  78. };
  79. ulpi_dir_py1 {
  80. nvidia,pins = "ulpi_dir_py1";
  81. nvidia,function = "spi1";
  82. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  83. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  84. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  85. };
  86. cam_i2c_scl_pbb1 {
  87. nvidia,pins = "cam_i2c_scl_pbb1",
  88. "cam_i2c_sda_pbb2";
  89. nvidia,function = "i2c3";
  90. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  91. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  92. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  93. nvidia,lock = <TEGRA_PIN_DISABLE>;
  94. nvidia,open-drain = <TEGRA_PIN_ENABLE>;
  95. };
  96. gen2_i2c_scl_pt5 {
  97. nvidia,pins = "gen2_i2c_scl_pt5",
  98. "gen2_i2c_sda_pt6";
  99. nvidia,function = "i2c2";
  100. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  101. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  102. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  103. nvidia,lock = <TEGRA_PIN_DISABLE>;
  104. nvidia,open-drain = <TEGRA_PIN_ENABLE>;
  105. };
  106. pg4 {
  107. nvidia,pins = "pg4",
  108. "pg5",
  109. "pg6",
  110. "pi3";
  111. nvidia,function = "spi4";
  112. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  113. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  114. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  115. };
  116. pg7 {
  117. nvidia,pins = "pg7";
  118. nvidia,function = "spi4";
  119. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  120. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  121. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  122. };
  123. ph1 {
  124. nvidia,pins = "ph1";
  125. nvidia,function = "pwm1";
  126. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  127. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  128. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  129. };
  130. pk0 {
  131. nvidia,pins = "pk0",
  132. "kb_row15_ps7",
  133. "clk_32k_out_pa0";
  134. nvidia,function = "soc";
  135. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  136. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  137. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  138. };
  139. sdmmc1_clk_pz0 {
  140. nvidia,pins = "sdmmc1_clk_pz0";
  141. nvidia,function = "sdmmc1";
  142. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  143. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  144. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  145. };
  146. sdmmc1_cmd_pz1 {
  147. nvidia,pins = "sdmmc1_cmd_pz1",
  148. "sdmmc1_dat0_py7",
  149. "sdmmc1_dat1_py6",
  150. "sdmmc1_dat2_py5",
  151. "sdmmc1_dat3_py4";
  152. nvidia,function = "sdmmc1";
  153. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  154. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  155. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  156. };
  157. sdmmc3_clk_pa6 {
  158. nvidia,pins = "sdmmc3_clk_pa6";
  159. nvidia,function = "sdmmc3";
  160. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  161. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  162. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  163. };
  164. sdmmc3_cmd_pa7 {
  165. nvidia,pins = "sdmmc3_cmd_pa7",
  166. "sdmmc3_dat0_pb7",
  167. "sdmmc3_dat1_pb6",
  168. "sdmmc3_dat2_pb5",
  169. "sdmmc3_dat3_pb4",
  170. "kb_col4_pq4",
  171. "sdmmc3_clk_lb_out_pee4",
  172. "sdmmc3_clk_lb_in_pee5",
  173. "sdmmc3_cd_n_pv2";
  174. nvidia,function = "sdmmc3";
  175. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  176. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  177. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  178. };
  179. sdmmc4_clk_pcc4 {
  180. nvidia,pins = "sdmmc4_clk_pcc4";
  181. nvidia,function = "sdmmc4";
  182. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  183. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  184. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  185. };
  186. sdmmc4_cmd_pt7 {
  187. nvidia,pins = "sdmmc4_cmd_pt7",
  188. "sdmmc4_dat0_paa0",
  189. "sdmmc4_dat1_paa1",
  190. "sdmmc4_dat2_paa2",
  191. "sdmmc4_dat3_paa3",
  192. "sdmmc4_dat4_paa4",
  193. "sdmmc4_dat5_paa5",
  194. "sdmmc4_dat6_paa6",
  195. "sdmmc4_dat7_paa7";
  196. nvidia,function = "sdmmc4";
  197. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  198. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  199. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  200. };
  201. pwr_i2c_scl_pz6 {
  202. nvidia,pins = "pwr_i2c_scl_pz6",
  203. "pwr_i2c_sda_pz7";
  204. nvidia,function = "i2cpwr";
  205. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  206. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  207. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  208. nvidia,lock = <TEGRA_PIN_DISABLE>;
  209. nvidia,open-drain = <TEGRA_PIN_ENABLE>;
  210. };
  211. jtag_rtck {
  212. nvidia,pins = "jtag_rtck";
  213. nvidia,function = "rtck";
  214. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  215. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  216. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  217. };
  218. clk_32k_in {
  219. nvidia,pins = "clk_32k_in";
  220. nvidia,function = "clk";
  221. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  222. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  223. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  224. };
  225. core_pwr_req {
  226. nvidia,pins = "core_pwr_req";
  227. nvidia,function = "pwron";
  228. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  229. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  230. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  231. };
  232. cpu_pwr_req {
  233. nvidia,pins = "cpu_pwr_req";
  234. nvidia,function = "cpu";
  235. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  236. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  237. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  238. };
  239. pwr_int_n {
  240. nvidia,pins = "pwr_int_n";
  241. nvidia,function = "pmi";
  242. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  243. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  244. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  245. };
  246. reset_out_n {
  247. nvidia,pins = "reset_out_n";
  248. nvidia,function = "reset_out_n";
  249. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  250. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  251. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  252. };
  253. clk3_out_pee0 {
  254. nvidia,pins = "clk3_out_pee0";
  255. nvidia,function = "extperiph3";
  256. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  257. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  258. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  259. };
  260. gen1_i2c_sda_pc5 {
  261. nvidia,pins = "gen1_i2c_sda_pc5",
  262. "gen1_i2c_scl_pc4";
  263. nvidia,function = "i2c1";
  264. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  265. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  266. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  267. nvidia,lock = <TEGRA_PIN_DISABLE>;
  268. nvidia,open-drain = <TEGRA_PIN_ENABLE>;
  269. };
  270. hdmi_cec_pee3 {
  271. nvidia,pins = "hdmi_cec_pee3";
  272. nvidia,function = "cec";
  273. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  274. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  275. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  276. nvidia,lock = <TEGRA_PIN_DISABLE>;
  277. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  278. };
  279. hdmi_int_pn7 {
  280. nvidia,pins = "hdmi_int_pn7";
  281. nvidia,function = "rsvd1";
  282. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  283. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  284. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  285. };
  286. ddc_scl_pv4 {
  287. nvidia,pins = "ddc_scl_pv4",
  288. "ddc_sda_pv5";
  289. nvidia,function = "i2c4";
  290. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  291. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  292. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  293. nvidia,lock = <TEGRA_PIN_DISABLE>;
  294. nvidia,rcv-sel = <TEGRA_PIN_ENABLE>;
  295. };
  296. kb_row10_ps2 {
  297. nvidia,pins = "kb_row10_ps2";
  298. nvidia,function = "uarta";
  299. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  300. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  301. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  302. };
  303. kb_row9_ps1 {
  304. nvidia,pins = "kb_row9_ps1";
  305. nvidia,function = "uarta";
  306. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  307. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  308. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  309. };
  310. usb_vbus_en0_pn4 {
  311. nvidia,pins = "usb_vbus_en0_pn4",
  312. "usb_vbus_en1_pn5";
  313. nvidia,function = "usb";
  314. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  315. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  316. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  317. nvidia,lock = <TEGRA_PIN_DISABLE>;
  318. nvidia,open-drain = <TEGRA_PIN_ENABLE>;
  319. };
  320. drive_sdio1 {
  321. nvidia,pins = "drive_sdio1";
  322. nvidia,high-speed-mode = <TEGRA_PIN_ENABLE>;
  323. nvidia,schmitt = <TEGRA_PIN_DISABLE>;
  324. nvidia,pull-down-strength = <36>;
  325. nvidia,pull-up-strength = <20>;
  326. nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_SLOW>;
  327. nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_SLOW>;
  328. };
  329. drive_sdio3 {
  330. nvidia,pins = "drive_sdio3";
  331. nvidia,high-speed-mode = <TEGRA_PIN_ENABLE>;
  332. nvidia,schmitt = <TEGRA_PIN_DISABLE>;
  333. nvidia,pull-down-strength = <22>;
  334. nvidia,pull-up-strength = <36>;
  335. nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_FASTEST>;
  336. nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_FASTEST>;
  337. };
  338. drive_gma {
  339. nvidia,pins = "drive_gma";
  340. nvidia,high-speed-mode = <TEGRA_PIN_ENABLE>;
  341. nvidia,schmitt = <TEGRA_PIN_DISABLE>;
  342. nvidia,pull-down-strength = <2>;
  343. nvidia,pull-up-strength = <1>;
  344. nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_FASTEST>;
  345. nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_FASTEST>;
  346. nvidia,drive-type = <1>;
  347. };
  348. codec_irq_l {
  349. nvidia,pins = "ph4";
  350. nvidia,function = "gmi";
  351. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  352. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  353. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  354. };
  355. lcd_bl_en {
  356. nvidia,pins = "ph2";
  357. nvidia,function = "gmi";
  358. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  359. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  360. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  361. };
  362. touch_irq_l {
  363. nvidia,pins = "gpio_w3_aud_pw3";
  364. nvidia,function = "spi6";
  365. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  366. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  367. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  368. };
  369. tpm_davint_l {
  370. nvidia,pins = "ph6";
  371. nvidia,function = "gmi";
  372. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  373. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  374. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  375. };
  376. ts_irq_l {
  377. nvidia,pins = "pk2";
  378. nvidia,function = "gmi";
  379. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  380. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  381. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  382. };
  383. ts_reset_l {
  384. nvidia,pins = "pk4";
  385. nvidia,function = "gmi";
  386. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  387. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  388. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  389. };
  390. ts_shdn_l {
  391. nvidia,pins = "pk1";
  392. nvidia,function = "gmi";
  393. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  394. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  395. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  396. };
  397. ph7 {
  398. nvidia,pins = "ph7";
  399. nvidia,function = "gmi";
  400. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  401. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  402. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  403. };
  404. kb_col0_ap {
  405. nvidia,pins = "kb_col0_pq0";
  406. nvidia,function = "rsvd4";
  407. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  408. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  409. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  410. };
  411. lid_open {
  412. nvidia,pins = "kb_row4_pr4";
  413. nvidia,function = "rsvd3";
  414. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  415. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  416. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  417. };
  418. en_vdd_sd {
  419. nvidia,pins = "kb_row0_pr0";
  420. nvidia,function = "rsvd4";
  421. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  422. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  423. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  424. };
  425. ac_ok {
  426. nvidia,pins = "pj0";
  427. nvidia,function = "gmi";
  428. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  429. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  430. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  431. };
  432. sensor_irq_l {
  433. nvidia,pins = "pi6";
  434. nvidia,function = "gmi";
  435. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  436. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  437. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  438. };
  439. wifi_en {
  440. nvidia,pins = "gpio_x7_aud_px7";
  441. nvidia,function = "rsvd4";
  442. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  443. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  444. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  445. };
  446. en_vdd_bl {
  447. nvidia,pins = "dap3_dout_pp2";
  448. nvidia,function = "i2s2";
  449. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  450. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  451. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  452. };
  453. en_vdd_hdmi {
  454. nvidia,pins = "spdif_in_pk6";
  455. nvidia,function = "spdif";
  456. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  457. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  458. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  459. };
  460. soc_warm_reset_l {
  461. nvidia,pins = "pi5";
  462. nvidia,function = "gmi";
  463. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  464. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  465. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  466. };
  467. hp_det_l {
  468. nvidia,pins = "pi7";
  469. nvidia,function = "rsvd1";
  470. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  471. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  472. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  473. };
  474. mic_det_l {
  475. nvidia,pins = "kb_row7_pr7";
  476. nvidia,function = "rsvd2";
  477. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  478. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  479. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  480. };
  481. };
  482. };
  483. serial@0,70006000 {
  484. /* Debug connector on the bottom of the board near SD card. */
  485. status = "okay";
  486. };
  487. pwm@0,7000a000 {
  488. status = "okay";
  489. };
  490. i2c@0,7000c000 {
  491. status = "okay";
  492. clock-frequency = <100000>;
  493. acodec: audio-codec@10 {
  494. compatible = "maxim,max98090";
  495. reg = <0x10>;
  496. interrupt-parent = <&gpio>;
  497. interrupts = <TEGRA_GPIO(H, 4) GPIO_ACTIVE_HIGH>;
  498. };
  499. temperature-sensor@4c {
  500. compatible = "ti,tmp451";
  501. reg = <0x4c>;
  502. interrupt-parent = <&gpio>;
  503. interrupts = <TEGRA_GPIO(I, 6) IRQ_TYPE_LEVEL_LOW>;
  504. #thermal-sensor-cells = <1>;
  505. };
  506. };
  507. i2c@0,7000c400 {
  508. status = "okay";
  509. clock-frequency = <100000>;
  510. };
  511. i2c@0,7000c500 {
  512. status = "okay";
  513. clock-frequency = <400000>;
  514. tpm@20 {
  515. compatible = "infineon,slb9645tt";
  516. reg = <0x20>;
  517. };
  518. };
  519. hdmi_ddc: i2c@0,7000c700 {
  520. status = "okay";
  521. clock-frequency = <100000>;
  522. };
  523. i2c@0,7000d000 {
  524. status = "okay";
  525. clock-frequency = <400000>;
  526. pmic: pmic@40 {
  527. compatible = "ams,as3722";
  528. reg = <0x40>;
  529. interrupts = <0 86 IRQ_TYPE_LEVEL_HIGH>;
  530. ams,system-power-controller;
  531. #interrupt-cells = <2>;
  532. interrupt-controller;
  533. gpio-controller;
  534. #gpio-cells = <2>;
  535. pinctrl-names = "default";
  536. pinctrl-0 = <&as3722_default>;
  537. as3722_default: pinmux {
  538. gpio0 {
  539. pins = "gpio0";
  540. function = "gpio";
  541. bias-pull-down;
  542. };
  543. gpio1 {
  544. pins = "gpio1";
  545. function = "gpio";
  546. bias-pull-up;
  547. };
  548. gpio2_4_7 {
  549. pins = "gpio2", "gpio4", "gpio7";
  550. function = "gpio";
  551. bias-pull-up;
  552. };
  553. gpio3_6 {
  554. pins = "gpio3", "gpio6";
  555. bias-high-impedance;
  556. };
  557. gpio5 {
  558. pins = "gpio5";
  559. function = "clk32k-out";
  560. bias-pull-down;
  561. };
  562. };
  563. regulators {
  564. vsup-sd2-supply = <&vdd_5v0_sys>;
  565. vsup-sd3-supply = <&vdd_5v0_sys>;
  566. vsup-sd4-supply = <&vdd_5v0_sys>;
  567. vsup-sd5-supply = <&vdd_5v0_sys>;
  568. vin-ldo0-supply = <&vdd_1v35_lp0>;
  569. vin-ldo1-6-supply = <&vdd_3v3_run>;
  570. vin-ldo2-5-7-supply = <&vddio_1v8>;
  571. vin-ldo3-4-supply = <&vdd_3v3_sys>;
  572. vin-ldo9-10-supply = <&vdd_5v0_sys>;
  573. vin-ldo11-supply = <&vdd_3v3_run>;
  574. sd0 {
  575. regulator-name = "+VDD_CPU_AP";
  576. regulator-min-microvolt = <700000>;
  577. regulator-max-microvolt = <1350000>;
  578. regulator-min-microamp = <3500000>;
  579. regulator-max-microamp = <3500000>;
  580. regulator-always-on;
  581. regulator-boot-on;
  582. ams,ext-control = <2>;
  583. };
  584. sd1 {
  585. regulator-name = "+VDD_CORE";
  586. regulator-min-microvolt = <700000>;
  587. regulator-max-microvolt = <1350000>;
  588. regulator-min-microamp = <2500000>;
  589. regulator-max-microamp = <4000000>;
  590. regulator-always-on;
  591. regulator-boot-on;
  592. ams,ext-control = <1>;
  593. };
  594. vdd_1v35_lp0: sd2 {
  595. regulator-name = "+1.35V_LP0(sd2)";
  596. regulator-min-microvolt = <1350000>;
  597. regulator-max-microvolt = <1350000>;
  598. regulator-always-on;
  599. regulator-boot-on;
  600. };
  601. sd3 {
  602. regulator-name = "+1.35V_LP0(sd3)";
  603. regulator-min-microvolt = <1350000>;
  604. regulator-max-microvolt = <1350000>;
  605. regulator-always-on;
  606. regulator-boot-on;
  607. };
  608. vdd_1v05_run: sd4 {
  609. regulator-name = "+1.05V_RUN";
  610. regulator-min-microvolt = <1050000>;
  611. regulator-max-microvolt = <1050000>;
  612. };
  613. vddio_1v8: sd5 {
  614. regulator-name = "+1.8V_VDDIO";
  615. regulator-min-microvolt = <1800000>;
  616. regulator-max-microvolt = <1800000>;
  617. regulator-boot-on;
  618. regulator-always-on;
  619. };
  620. sd6 {
  621. regulator-name = "+VDD_GPU_AP";
  622. regulator-min-microvolt = <650000>;
  623. regulator-max-microvolt = <1200000>;
  624. regulator-min-microamp = <3500000>;
  625. regulator-max-microamp = <3500000>;
  626. regulator-boot-on;
  627. regulator-always-on;
  628. };
  629. ldo0 {
  630. regulator-name = "+1.05V_RUN_AVDD";
  631. regulator-min-microvolt = <1050000>;
  632. regulator-max-microvolt = <1050000>;
  633. regulator-boot-on;
  634. regulator-always-on;
  635. ams,ext-control = <1>;
  636. };
  637. ldo1 {
  638. regulator-name = "+1.8V_RUN_CAM";
  639. regulator-min-microvolt = <1800000>;
  640. regulator-max-microvolt = <1800000>;
  641. };
  642. ldo2 {
  643. regulator-name = "+1.2V_GEN_AVDD";
  644. regulator-min-microvolt = <1200000>;
  645. regulator-max-microvolt = <1200000>;
  646. regulator-boot-on;
  647. regulator-always-on;
  648. };
  649. ldo3 {
  650. regulator-name = "+1.00V_LP0_VDD_RTC";
  651. regulator-min-microvolt = <1000000>;
  652. regulator-max-microvolt = <1000000>;
  653. regulator-boot-on;
  654. regulator-always-on;
  655. ams,enable-tracking;
  656. };
  657. vdd_run_cam: ldo4 {
  658. regulator-name = "+3.3V_RUN_CAM";
  659. regulator-min-microvolt = <2800000>;
  660. regulator-max-microvolt = <2800000>;
  661. };
  662. ldo5 {
  663. regulator-name = "+1.2V_RUN_CAM_FRONT";
  664. regulator-min-microvolt = <1200000>;
  665. regulator-max-microvolt = <1200000>;
  666. };
  667. vddio_sdmmc3: ldo6 {
  668. regulator-name = "+VDDIO_SDMMC3";
  669. regulator-min-microvolt = <1800000>;
  670. regulator-max-microvolt = <3300000>;
  671. };
  672. ldo7 {
  673. regulator-name = "+1.05V_RUN_CAM_REAR";
  674. regulator-min-microvolt = <1050000>;
  675. regulator-max-microvolt = <1050000>;
  676. };
  677. ldo9 {
  678. regulator-name = "+2.8V_RUN_TOUCH";
  679. regulator-min-microvolt = <2800000>;
  680. regulator-max-microvolt = <2800000>;
  681. };
  682. ldo10 {
  683. regulator-name = "+2.8V_RUN_CAM_AF";
  684. regulator-min-microvolt = <2800000>;
  685. regulator-max-microvolt = <2800000>;
  686. };
  687. ldo11 {
  688. regulator-name = "+1.8V_RUN_VPP_FUSE";
  689. regulator-min-microvolt = <1800000>;
  690. regulator-max-microvolt = <1800000>;
  691. };
  692. };
  693. };
  694. };
  695. spi@0,7000d400 {
  696. status = "okay";
  697. cros_ec: cros-ec@0 {
  698. compatible = "google,cros-ec-spi";
  699. spi-max-frequency = <3000000>;
  700. interrupt-parent = <&gpio>;
  701. interrupts = <TEGRA_GPIO(C, 7) IRQ_TYPE_LEVEL_LOW>;
  702. reg = <0>;
  703. google,cros-ec-spi-msg-delay = <2000>;
  704. i2c-tunnel {
  705. compatible = "google,cros-ec-i2c-tunnel";
  706. #address-cells = <1>;
  707. #size-cells = <0>;
  708. google,remote-bus = <0>;
  709. charger: bq24735@9 {
  710. compatible = "ti,bq24735";
  711. reg = <0x9>;
  712. interrupt-parent = <&gpio>;
  713. interrupts = <TEGRA_GPIO(J, 0)
  714. GPIO_ACTIVE_HIGH>;
  715. ti,ac-detect-gpios = <&gpio
  716. TEGRA_GPIO(J, 0)
  717. GPIO_ACTIVE_HIGH>;
  718. };
  719. battery: sbs-battery@b {
  720. compatible = "sbs,sbs-battery";
  721. reg = <0xb>;
  722. sbs,i2c-retry-count = <2>;
  723. sbs,poll-retry-count = <10>;
  724. power-supplies = <&charger>;
  725. };
  726. };
  727. };
  728. };
  729. spi@0,7000da00 {
  730. status = "okay";
  731. spi-max-frequency = <25000000>;
  732. flash@0 {
  733. compatible = "winbond,w25q32dw";
  734. reg = <0>;
  735. };
  736. };
  737. pmc@0,7000e400 {
  738. nvidia,invert-interrupt;
  739. nvidia,suspend-mode = <0>;
  740. nvidia,cpu-pwr-good-time = <500>;
  741. nvidia,cpu-pwr-off-time = <300>;
  742. nvidia,core-pwr-good-time = <641 3845>;
  743. nvidia,core-pwr-off-time = <61036>;
  744. nvidia,core-power-req-active-high;
  745. nvidia,sys-clock-req-active-high;
  746. };
  747. hda@0,70030000 {
  748. status = "okay";
  749. };
  750. sdhci@0,700b0000 { /* WiFi/BT on this bus */
  751. status = "okay";
  752. power-gpios = <&gpio TEGRA_GPIO(X, 7) GPIO_ACTIVE_HIGH>;
  753. bus-width = <4>;
  754. no-1-8-v;
  755. non-removable;
  756. };
  757. sdhci@0,700b0400 { /* SD Card on this bus */
  758. status = "okay";
  759. cd-gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_LOW>;
  760. power-gpios = <&gpio TEGRA_GPIO(R, 0) GPIO_ACTIVE_HIGH>;
  761. wp-gpios = <&gpio TEGRA_GPIO(Q, 4) GPIO_ACTIVE_LOW>;
  762. bus-width = <4>;
  763. no-1-8-v;
  764. vqmmc-supply = <&vddio_sdmmc3>;
  765. };
  766. sdhci@0,700b0600 { /* eMMC on this bus */
  767. status = "okay";
  768. bus-width = <8>;
  769. no-1-8-v;
  770. non-removable;
  771. };
  772. ahub@0,70300000 {
  773. i2s@0,70301100 {
  774. status = "okay";
  775. };
  776. };
  777. usb@0,7d000000 { /* Rear external USB port. */
  778. status = "okay";
  779. };
  780. usb-phy@0,7d000000 {
  781. status = "okay";
  782. vbus-supply = <&vdd_usb1_vbus>;
  783. };
  784. usb@0,7d004000 { /* Internal webcam. */
  785. status = "okay";
  786. };
  787. usb-phy@0,7d004000 {
  788. status = "okay";
  789. vbus-supply = <&vdd_run_cam>;
  790. };
  791. usb@0,7d008000 { /* Left external USB port. */
  792. status = "okay";
  793. };
  794. usb-phy@0,7d008000 {
  795. status = "okay";
  796. vbus-supply = <&vdd_usb3_vbus>;
  797. };
  798. backlight: backlight {
  799. compatible = "pwm-backlight";
  800. enable-gpios = <&gpio TEGRA_GPIO(H, 2) GPIO_ACTIVE_HIGH>;
  801. power-supply = <&vdd_led>;
  802. pwms = <&pwm 1 1000000>;
  803. default-brightness-level = <224>;
  804. brightness-levels =
  805. < 0 1 2 3 4 5 6 7
  806. 8 9 10 11 12 13 14 15
  807. 16 17 18 19 20 21 22 23
  808. 24 25 26 27 28 29 30 31
  809. 32 33 34 35 36 37 38 39
  810. 40 41 42 43 44 45 46 47
  811. 48 49 50 51 52 53 54 55
  812. 56 57 58 59 60 61 62 63
  813. 64 65 66 67 68 69 70 71
  814. 72 73 74 75 76 77 78 79
  815. 80 81 82 83 84 85 86 87
  816. 88 89 90 91 92 93 94 95
  817. 96 97 98 99 100 101 102 103
  818. 104 105 106 107 108 109 110 111
  819. 112 113 114 115 116 117 118 119
  820. 120 121 122 123 124 125 126 127
  821. 128 129 130 131 132 133 134 135
  822. 136 137 138 139 140 141 142 143
  823. 144 145 146 147 148 149 150 151
  824. 152 153 154 155 156 157 158 159
  825. 160 161 162 163 164 165 166 167
  826. 168 169 170 171 172 173 174 175
  827. 176 177 178 179 180 181 182 183
  828. 184 185 186 187 188 189 190 191
  829. 192 193 194 195 196 197 198 199
  830. 200 201 202 203 204 205 206 207
  831. 208 209 210 211 212 213 214 215
  832. 216 217 218 219 220 221 222 223
  833. 224 225 226 227 228 229 230 231
  834. 232 233 234 235 236 237 238 239
  835. 240 241 242 243 244 245 246 247
  836. 248 249 250 251 252 253 254 255
  837. 256>;
  838. };
  839. clocks {
  840. compatible = "simple-bus";
  841. #address-cells = <1>;
  842. #size-cells = <0>;
  843. clk32k_in: clock@0 {
  844. compatible = "fixed-clock";
  845. reg = <0>;
  846. #clock-cells = <0>;
  847. clock-frequency = <32768>;
  848. };
  849. };
  850. gpio-keys {
  851. compatible = "gpio-keys";
  852. lid {
  853. label = "Lid";
  854. gpios = <&gpio TEGRA_GPIO(R, 4) GPIO_ACTIVE_LOW>;
  855. linux,input-type = <5>;
  856. linux,code = <KEY_RESERVED>;
  857. debounce-interval = <1>;
  858. gpio-key,wakeup;
  859. };
  860. power {
  861. label = "Power";
  862. gpios = <&gpio TEGRA_GPIO(Q, 0) GPIO_ACTIVE_LOW>;
  863. linux,code = <KEY_POWER>;
  864. debounce-interval = <30>;
  865. gpio-key,wakeup;
  866. };
  867. };
  868. panel: panel {
  869. compatible = "auo,b133xtn01";
  870. backlight = <&backlight>;
  871. ddc-i2c-bus = <&dpaux>;
  872. };
  873. regulators {
  874. compatible = "simple-bus";
  875. #address-cells = <1>;
  876. #size-cells = <0>;
  877. vdd_mux: regulator@0 {
  878. compatible = "regulator-fixed";
  879. reg = <0>;
  880. regulator-name = "+VDD_MUX";
  881. regulator-min-microvolt = <12000000>;
  882. regulator-max-microvolt = <12000000>;
  883. regulator-always-on;
  884. regulator-boot-on;
  885. };
  886. vdd_5v0_sys: regulator@1 {
  887. compatible = "regulator-fixed";
  888. reg = <1>;
  889. regulator-name = "+5V_SYS";
  890. regulator-min-microvolt = <5000000>;
  891. regulator-max-microvolt = <5000000>;
  892. regulator-always-on;
  893. regulator-boot-on;
  894. vin-supply = <&vdd_mux>;
  895. };
  896. vdd_3v3_sys: regulator@2 {
  897. compatible = "regulator-fixed";
  898. reg = <2>;
  899. regulator-name = "+3.3V_SYS";
  900. regulator-min-microvolt = <3300000>;
  901. regulator-max-microvolt = <3300000>;
  902. regulator-always-on;
  903. regulator-boot-on;
  904. vin-supply = <&vdd_mux>;
  905. };
  906. vdd_3v3_run: regulator@3 {
  907. compatible = "regulator-fixed";
  908. reg = <3>;
  909. regulator-name = "+3.3V_RUN";
  910. regulator-min-microvolt = <3300000>;
  911. regulator-max-microvolt = <3300000>;
  912. regulator-always-on;
  913. regulator-boot-on;
  914. gpio = <&pmic 1 GPIO_ACTIVE_HIGH>;
  915. enable-active-high;
  916. vin-supply = <&vdd_3v3_sys>;
  917. };
  918. vdd_3v3_hdmi: regulator@4 {
  919. compatible = "regulator-fixed";
  920. reg = <4>;
  921. regulator-name = "+3.3V_AVDD_HDMI_AP_GATED";
  922. regulator-min-microvolt = <3300000>;
  923. regulator-max-microvolt = <3300000>;
  924. vin-supply = <&vdd_3v3_run>;
  925. };
  926. vdd_led: regulator@5 {
  927. compatible = "regulator-fixed";
  928. reg = <5>;
  929. regulator-name = "+VDD_LED";
  930. gpio = <&gpio TEGRA_GPIO(P, 2) GPIO_ACTIVE_HIGH>;
  931. enable-active-high;
  932. vin-supply = <&vdd_mux>;
  933. };
  934. vdd_5v0_ts: regulator@6 {
  935. compatible = "regulator-fixed";
  936. reg = <6>;
  937. regulator-name = "+5V_VDD_TS_SW";
  938. regulator-min-microvolt = <5000000>;
  939. regulator-max-microvolt = <5000000>;
  940. regulator-boot-on;
  941. gpio = <&gpio TEGRA_GPIO(K, 1) GPIO_ACTIVE_HIGH>;
  942. enable-active-high;
  943. vin-supply = <&vdd_5v0_sys>;
  944. };
  945. vdd_usb1_vbus: regulator@7 {
  946. compatible = "regulator-fixed";
  947. reg = <7>;
  948. regulator-name = "+5V_USB_HS";
  949. regulator-min-microvolt = <5000000>;
  950. regulator-max-microvolt = <5000000>;
  951. gpio = <&gpio TEGRA_GPIO(N, 4) GPIO_ACTIVE_HIGH>;
  952. enable-active-high;
  953. gpio-open-drain;
  954. vin-supply = <&vdd_5v0_sys>;
  955. };
  956. vdd_usb3_vbus: regulator@8 {
  957. compatible = "regulator-fixed";
  958. reg = <8>;
  959. regulator-name = "+5V_USB_SS";
  960. regulator-min-microvolt = <5000000>;
  961. regulator-max-microvolt = <5000000>;
  962. gpio = <&gpio TEGRA_GPIO(N, 5) GPIO_ACTIVE_HIGH>;
  963. enable-active-high;
  964. gpio-open-drain;
  965. vin-supply = <&vdd_5v0_sys>;
  966. };
  967. vdd_3v3_panel: regulator@9 {
  968. compatible = "regulator-fixed";
  969. reg = <9>;
  970. regulator-name = "+3.3V_PANEL";
  971. regulator-min-microvolt = <3300000>;
  972. regulator-max-microvolt = <3300000>;
  973. gpio = <&pmic 4 GPIO_ACTIVE_HIGH>;
  974. enable-active-high;
  975. vin-supply = <&vdd_3v3_run>;
  976. };
  977. vdd_3v3_lp0: regulator@10 {
  978. compatible = "regulator-fixed";
  979. reg = <10>;
  980. regulator-name = "+3.3V_LP0";
  981. regulator-min-microvolt = <3300000>;
  982. regulator-max-microvolt = <3300000>;
  983. /*
  984. * TODO: find a way to wire this up with the USB EHCI
  985. * controllers so that it can be enabled on demand.
  986. */
  987. regulator-always-on;
  988. gpio = <&pmic 2 GPIO_ACTIVE_HIGH>;
  989. enable-active-high;
  990. vin-supply = <&vdd_3v3_sys>;
  991. };
  992. vdd_hdmi_pll: regulator@11 {
  993. compatible = "regulator-fixed";
  994. reg = <11>;
  995. regulator-name = "+1.05V_RUN_AVDD_HDMI_PLL";
  996. regulator-min-microvolt = <1050000>;
  997. regulator-max-microvolt = <1050000>;
  998. gpio = <&gpio TEGRA_GPIO(H, 7) GPIO_ACTIVE_LOW>;
  999. vin-supply = <&vdd_1v05_run>;
  1000. };
  1001. vdd_5v0_hdmi: regulator@12 {
  1002. compatible = "regulator-fixed";
  1003. reg = <12>;
  1004. regulator-name = "+5V_HDMI_CON";
  1005. regulator-min-microvolt = <5000000>;
  1006. regulator-max-microvolt = <5000000>;
  1007. gpio = <&gpio TEGRA_GPIO(K, 6) GPIO_ACTIVE_HIGH>;
  1008. enable-active-high;
  1009. vin-supply = <&vdd_5v0_sys>;
  1010. };
  1011. };
  1012. sound {
  1013. compatible = "nvidia,tegra-audio-max98090-nyan-big",
  1014. "nvidia,tegra-audio-max98090";
  1015. nvidia,model = "Acer Chromebook 13";
  1016. nvidia,audio-routing =
  1017. "Headphones", "HPR",
  1018. "Headphones", "HPL",
  1019. "Speakers", "SPKR",
  1020. "Speakers", "SPKL",
  1021. "Mic Jack", "MICBIAS",
  1022. "DMICL", "Int Mic",
  1023. "DMICR", "Int Mic",
  1024. "IN34", "Mic Jack";
  1025. nvidia,i2s-controller = <&tegra_i2s1>;
  1026. nvidia,audio-codec = <&acodec>;
  1027. clocks = <&tegra_car TEGRA124_CLK_PLL_A>,
  1028. <&tegra_car TEGRA124_CLK_PLL_A_OUT0>,
  1029. <&tegra_car TEGRA124_CLK_EXTERN1>;
  1030. clock-names = "pll_a", "pll_a_out0", "mclk";
  1031. nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(I, 7) GPIO_ACTIVE_HIGH>;
  1032. };
  1033. };
  1034. #include "cros-ec-keyboard.dtsi"