tegra124-venice2.dts 30 KB

1234567891011121314151617181920212223242526272829303132333435363738394041424344454647484950515253545556575859606162636465666768697071727374757677787980818283848586878889909192939495969798991001011021031041051061071081091101111121131141151161171181191201211221231241251261271281291301311321331341351361371381391401411421431441451461471481491501511521531541551561571581591601611621631641651661671681691701711721731741751761771781791801811821831841851861871881891901911921931941951961971981992002012022032042052062072082092102112122132142152162172182192202212222232242252262272282292302312322332342352362372382392402412422432442452462472482492502512522532542552562572582592602612622632642652662672682692702712722732742752762772782792802812822832842852862872882892902912922932942952962972982993003013023033043053063073083093103113123133143153163173183193203213223233243253263273283293303313323333343353363373383393403413423433443453463473483493503513523533543553563573583593603613623633643653663673683693703713723733743753763773783793803813823833843853863873883893903913923933943953963973983994004014024034044054064074084094104114124134144154164174184194204214224234244254264274284294304314324334344354364374384394404414424434444454464474484494504514524534544554564574584594604614624634644654664674684694704714724734744754764774784794804814824834844854864874884894904914924934944954964974984995005015025035045055065075085095105115125135145155165175185195205215225235245255265275285295305315325335345355365375385395405415425435445455465475485495505515525535545555565575585595605615625635645655665675685695705715725735745755765775785795805815825835845855865875885895905915925935945955965975985996006016026036046056066076086096106116126136146156166176186196206216226236246256266276286296306316326336346356366376386396406416426436446456466476486496506516526536546556566576586596606616626636646656666676686696706716726736746756766776786796806816826836846856866876886896906916926936946956966976986997007017027037047057067077087097107117127137147157167177187197207217227237247257267277287297307317327337347357367377387397407417427437447457467477487497507517527537547557567577587597607617627637647657667677687697707717727737747757767777787797807817827837847857867877887897907917927937947957967977987998008018028038048058068078088098108118128138148158168178188198208218228238248258268278288298308318328338348358368378388398408418428438448458468478488498508518528538548558568578588598608618628638648658668678688698708718728738748758768778788798808818828838848858868878888898908918928938948958968978988999009019029039049059069079089099109119129139149159169179189199209219229239249259269279289299309319329339349359369379389399409419429439449459469479489499509519529539549559569579589599609619629639649659669679689699709719729739749759769779789799809819829839849859869879889899909919929939949959969979989991000100110021003100410051006100710081009101010111012101310141015101610171018101910201021102210231024102510261027102810291030103110321033103410351036103710381039104010411042104310441045104610471048104910501051105210531054105510561057105810591060106110621063106410651066106710681069107010711072107310741075107610771078107910801081108210831084108510861087108810891090109110921093109410951096109710981099110011011102110311041105110611071108110911101111111211131114111511161117111811191120112111221123112411251126112711281129113011311132113311341135113611371138113911401141114211431144114511461147114811491150115111521153115411551156
  1. /dts-v1/;
  2. #include <dt-bindings/input/input.h>
  3. #include "tegra124.dtsi"
  4. / {
  5. model = "NVIDIA Tegra124 Venice2";
  6. compatible = "nvidia,venice2", "nvidia,tegra124";
  7. aliases {
  8. rtc0 = "/i2c@0,7000d000/pmic@40";
  9. rtc1 = "/rtc@0,7000e000";
  10. serial0 = &uarta;
  11. };
  12. memory {
  13. reg = <0x0 0x80000000 0x0 0x80000000>;
  14. };
  15. host1x@0,50000000 {
  16. hdmi@0,54280000 {
  17. status = "okay";
  18. vdd-supply = <&vdd_3v3_hdmi>;
  19. pll-supply = <&vdd_hdmi_pll>;
  20. hdmi-supply = <&vdd_5v0_hdmi>;
  21. nvidia,ddc-i2c-bus = <&hdmi_ddc>;
  22. nvidia,hpd-gpio =
  23. <&gpio TEGRA_GPIO(N, 7) GPIO_ACTIVE_HIGH>;
  24. };
  25. sor@0,54540000 {
  26. status = "okay";
  27. nvidia,dpaux = <&dpaux>;
  28. nvidia,panel = <&panel>;
  29. };
  30. dpaux@0,545c0000 {
  31. vdd-supply = <&vdd_3v3_panel>;
  32. status = "okay";
  33. };
  34. };
  35. pinmux: pinmux@0,70000868 {
  36. pinctrl-names = "boot";
  37. pinctrl-0 = <&pinmux_boot>;
  38. pinmux_boot: common {
  39. dap_mclk1_pw4 {
  40. nvidia,pins = "dap_mclk1_pw4";
  41. nvidia,function = "extperiph1";
  42. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  43. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  44. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  45. };
  46. dap1_din_pn1 {
  47. nvidia,pins = "dap1_din_pn1";
  48. nvidia,function = "i2s0";
  49. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  50. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  51. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  52. };
  53. dap1_dout_pn2 {
  54. nvidia,pins = "dap1_dout_pn2",
  55. "dap1_fs_pn0",
  56. "dap1_sclk_pn3";
  57. nvidia,function = "i2s0";
  58. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  59. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  60. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  61. };
  62. dap2_din_pa4 {
  63. nvidia,pins = "dap2_din_pa4";
  64. nvidia,function = "i2s1";
  65. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  66. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  67. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  68. };
  69. dap2_dout_pa5 {
  70. nvidia,pins = "dap2_dout_pa5",
  71. "dap2_fs_pa2",
  72. "dap2_sclk_pa3";
  73. nvidia,function = "i2s1";
  74. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  75. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  76. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  77. };
  78. dvfs_pwm_px0 {
  79. nvidia,pins = "dvfs_pwm_px0",
  80. "dvfs_clk_px2";
  81. nvidia,function = "cldvfs";
  82. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  83. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  84. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  85. };
  86. ulpi_clk_py0 {
  87. nvidia,pins = "ulpi_clk_py0",
  88. "ulpi_nxt_py2",
  89. "ulpi_stp_py3";
  90. nvidia,function = "spi1";
  91. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  92. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  93. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  94. };
  95. ulpi_dir_py1 {
  96. nvidia,pins = "ulpi_dir_py1";
  97. nvidia,function = "spi1";
  98. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  99. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  100. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  101. };
  102. cam_i2c_scl_pbb1 {
  103. nvidia,pins = "cam_i2c_scl_pbb1",
  104. "cam_i2c_sda_pbb2";
  105. nvidia,function = "i2c3";
  106. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  107. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  108. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  109. nvidia,lock = <TEGRA_PIN_DISABLE>;
  110. nvidia,open-drain = <TEGRA_PIN_ENABLE>;
  111. };
  112. gen2_i2c_scl_pt5 {
  113. nvidia,pins = "gen2_i2c_scl_pt5",
  114. "gen2_i2c_sda_pt6";
  115. nvidia,function = "i2c2";
  116. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  117. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  118. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  119. nvidia,lock = <TEGRA_PIN_DISABLE>;
  120. nvidia,open-drain = <TEGRA_PIN_ENABLE>;
  121. };
  122. pg4 {
  123. nvidia,pins = "pg4",
  124. "pg5",
  125. "pg6",
  126. "pi3";
  127. nvidia,function = "spi4";
  128. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  129. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  130. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  131. };
  132. pg7 {
  133. nvidia,pins = "pg7";
  134. nvidia,function = "spi4";
  135. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  136. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  137. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  138. };
  139. ph1 {
  140. nvidia,pins = "ph1";
  141. nvidia,function = "pwm1";
  142. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  143. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  144. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  145. };
  146. pk0 {
  147. nvidia,pins = "pk0",
  148. "kb_row15_ps7",
  149. "clk_32k_out_pa0";
  150. nvidia,function = "soc";
  151. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  152. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  153. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  154. };
  155. sdmmc1_clk_pz0 {
  156. nvidia,pins = "sdmmc1_clk_pz0";
  157. nvidia,function = "sdmmc1";
  158. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  159. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  160. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  161. };
  162. sdmmc1_cmd_pz1 {
  163. nvidia,pins = "sdmmc1_cmd_pz1",
  164. "sdmmc1_dat0_py7",
  165. "sdmmc1_dat1_py6",
  166. "sdmmc1_dat2_py5",
  167. "sdmmc1_dat3_py4";
  168. nvidia,function = "sdmmc1";
  169. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  170. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  171. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  172. };
  173. sdmmc3_clk_pa6 {
  174. nvidia,pins = "sdmmc3_clk_pa6";
  175. nvidia,function = "sdmmc3";
  176. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  177. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  178. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  179. };
  180. sdmmc3_cmd_pa7 {
  181. nvidia,pins = "sdmmc3_cmd_pa7",
  182. "sdmmc3_dat0_pb7",
  183. "sdmmc3_dat1_pb6",
  184. "sdmmc3_dat2_pb5",
  185. "sdmmc3_dat3_pb4",
  186. "sdmmc3_clk_lb_out_pee4",
  187. "sdmmc3_clk_lb_in_pee5";
  188. nvidia,function = "sdmmc3";
  189. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  190. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  191. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  192. };
  193. sdmmc4_clk_pcc4 {
  194. nvidia,pins = "sdmmc4_clk_pcc4";
  195. nvidia,function = "sdmmc4";
  196. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  197. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  198. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  199. };
  200. sdmmc4_cmd_pt7 {
  201. nvidia,pins = "sdmmc4_cmd_pt7",
  202. "sdmmc4_dat0_paa0",
  203. "sdmmc4_dat1_paa1",
  204. "sdmmc4_dat2_paa2",
  205. "sdmmc4_dat3_paa3",
  206. "sdmmc4_dat4_paa4",
  207. "sdmmc4_dat5_paa5",
  208. "sdmmc4_dat6_paa6",
  209. "sdmmc4_dat7_paa7";
  210. nvidia,function = "sdmmc4";
  211. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  212. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  213. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  214. };
  215. pwr_i2c_scl_pz6 {
  216. nvidia,pins = "pwr_i2c_scl_pz6",
  217. "pwr_i2c_sda_pz7";
  218. nvidia,function = "i2cpwr";
  219. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  220. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  221. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  222. nvidia,lock = <TEGRA_PIN_DISABLE>;
  223. nvidia,open-drain = <TEGRA_PIN_ENABLE>;
  224. };
  225. jtag_rtck {
  226. nvidia,pins = "jtag_rtck";
  227. nvidia,function = "rtck";
  228. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  229. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  230. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  231. };
  232. clk_32k_in {
  233. nvidia,pins = "clk_32k_in";
  234. nvidia,function = "clk";
  235. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  236. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  237. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  238. };
  239. core_pwr_req {
  240. nvidia,pins = "core_pwr_req";
  241. nvidia,function = "pwron";
  242. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  243. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  244. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  245. };
  246. cpu_pwr_req {
  247. nvidia,pins = "cpu_pwr_req";
  248. nvidia,function = "cpu";
  249. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  250. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  251. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  252. };
  253. pwr_int_n {
  254. nvidia,pins = "pwr_int_n";
  255. nvidia,function = "pmi";
  256. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  257. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  258. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  259. };
  260. reset_out_n {
  261. nvidia,pins = "reset_out_n";
  262. nvidia,function = "reset_out_n";
  263. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  264. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  265. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  266. };
  267. clk3_out_pee0 {
  268. nvidia,pins = "clk3_out_pee0";
  269. nvidia,function = "extperiph3";
  270. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  271. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  272. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  273. };
  274. dap4_din_pp5 {
  275. nvidia,pins = "dap4_din_pp5";
  276. nvidia,function = "i2s3";
  277. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  278. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  279. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  280. };
  281. dap4_dout_pp6 {
  282. nvidia,pins = "dap4_dout_pp6",
  283. "dap4_fs_pp4",
  284. "dap4_sclk_pp7";
  285. nvidia,function = "i2s3";
  286. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  287. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  288. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  289. };
  290. gen1_i2c_sda_pc5 {
  291. nvidia,pins = "gen1_i2c_sda_pc5",
  292. "gen1_i2c_scl_pc4";
  293. nvidia,function = "i2c1";
  294. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  295. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  296. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  297. nvidia,lock = <TEGRA_PIN_DISABLE>;
  298. nvidia,open-drain = <TEGRA_PIN_ENABLE>;
  299. };
  300. uart2_cts_n_pj5 {
  301. nvidia,pins = "uart2_cts_n_pj5";
  302. nvidia,function = "uartb";
  303. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  304. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  305. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  306. };
  307. uart2_rts_n_pj6 {
  308. nvidia,pins = "uart2_rts_n_pj6";
  309. nvidia,function = "uartb";
  310. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  311. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  312. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  313. };
  314. uart2_rxd_pc3 {
  315. nvidia,pins = "uart2_rxd_pc3";
  316. nvidia,function = "irda";
  317. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  318. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  319. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  320. };
  321. uart2_txd_pc2 {
  322. nvidia,pins = "uart2_txd_pc2";
  323. nvidia,function = "irda";
  324. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  325. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  326. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  327. };
  328. uart3_cts_n_pa1 {
  329. nvidia,pins = "uart3_cts_n_pa1",
  330. "uart3_rxd_pw7";
  331. nvidia,function = "uartc";
  332. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  333. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  334. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  335. };
  336. uart3_rts_n_pc0 {
  337. nvidia,pins = "uart3_rts_n_pc0",
  338. "uart3_txd_pw6";
  339. nvidia,function = "uartc";
  340. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  341. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  342. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  343. };
  344. hdmi_cec_pee3 {
  345. nvidia,pins = "hdmi_cec_pee3";
  346. nvidia,function = "cec";
  347. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  348. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  349. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  350. nvidia,lock = <TEGRA_PIN_DISABLE>;
  351. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  352. };
  353. hdmi_int_pn7 {
  354. nvidia,pins = "hdmi_int_pn7";
  355. nvidia,function = "rsvd1";
  356. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  357. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  358. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  359. };
  360. ddc_scl_pv4 {
  361. nvidia,pins = "ddc_scl_pv4",
  362. "ddc_sda_pv5";
  363. nvidia,function = "i2c4";
  364. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  365. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  366. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  367. nvidia,lock = <TEGRA_PIN_DISABLE>;
  368. nvidia,rcv-sel = <TEGRA_PIN_ENABLE>;
  369. };
  370. pj7 {
  371. nvidia,pins = "pj7",
  372. "pk7";
  373. nvidia,function = "uartd";
  374. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  375. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  376. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  377. };
  378. pb0 {
  379. nvidia,pins = "pb0",
  380. "pb1";
  381. nvidia,function = "uartd";
  382. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  383. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  384. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  385. };
  386. ph0 {
  387. nvidia,pins = "ph0";
  388. nvidia,function = "pwm0";
  389. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  390. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  391. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  392. };
  393. kb_row10_ps2 {
  394. nvidia,pins = "kb_row10_ps2";
  395. nvidia,function = "uarta";
  396. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  397. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  398. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  399. };
  400. kb_row9_ps1 {
  401. nvidia,pins = "kb_row9_ps1";
  402. nvidia,function = "uarta";
  403. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  404. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  405. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  406. };
  407. kb_row6_pr6 {
  408. nvidia,pins = "kb_row6_pr6";
  409. nvidia,function = "displaya_alt";
  410. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  411. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  412. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  413. };
  414. usb_vbus_en0_pn4 {
  415. nvidia,pins = "usb_vbus_en0_pn4",
  416. "usb_vbus_en1_pn5";
  417. nvidia,function = "usb";
  418. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  419. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  420. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  421. nvidia,lock = <TEGRA_PIN_DISABLE>;
  422. nvidia,open-drain = <TEGRA_PIN_ENABLE>;
  423. };
  424. drive_sdio1 {
  425. nvidia,pins = "drive_sdio1";
  426. nvidia,high-speed-mode = <TEGRA_PIN_ENABLE>;
  427. nvidia,schmitt = <TEGRA_PIN_DISABLE>;
  428. nvidia,pull-down-strength = <32>;
  429. nvidia,pull-up-strength = <42>;
  430. nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_FASTEST>;
  431. nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_FASTEST>;
  432. };
  433. drive_sdio3 {
  434. nvidia,pins = "drive_sdio3";
  435. nvidia,high-speed-mode = <TEGRA_PIN_ENABLE>;
  436. nvidia,schmitt = <TEGRA_PIN_DISABLE>;
  437. nvidia,pull-down-strength = <20>;
  438. nvidia,pull-up-strength = <36>;
  439. nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_FASTEST>;
  440. nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_FASTEST>;
  441. };
  442. drive_gma {
  443. nvidia,pins = "drive_gma";
  444. nvidia,high-speed-mode = <TEGRA_PIN_ENABLE>;
  445. nvidia,schmitt = <TEGRA_PIN_DISABLE>;
  446. nvidia,low-power-mode = <TEGRA_PIN_LP_DRIVE_DIV_1>;
  447. nvidia,pull-down-strength = <1>;
  448. nvidia,pull-up-strength = <2>;
  449. nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_FASTEST>;
  450. nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_FASTEST>;
  451. nvidia,drive-type = <1>;
  452. };
  453. als_irq_l {
  454. nvidia,pins = "gpio_x3_aud_px3";
  455. nvidia,function = "gmi";
  456. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  457. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  458. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  459. };
  460. codec_irq_l {
  461. nvidia,pins = "ph4";
  462. nvidia,function = "gmi";
  463. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  464. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  465. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  466. };
  467. lcd_bl_en {
  468. nvidia,pins = "ph2";
  469. nvidia,function = "gmi";
  470. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  471. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  472. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  473. };
  474. touch_irq_l {
  475. nvidia,pins = "gpio_w3_aud_pw3";
  476. nvidia,function = "spi6";
  477. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  478. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  479. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  480. };
  481. tpm_davint_l {
  482. nvidia,pins = "ph6";
  483. nvidia,function = "gmi";
  484. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  485. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  486. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  487. };
  488. ts_irq_l {
  489. nvidia,pins = "pk2";
  490. nvidia,function = "gmi";
  491. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  492. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  493. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  494. };
  495. ts_reset_l {
  496. nvidia,pins = "pk4";
  497. nvidia,function = "gmi";
  498. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  499. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  500. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  501. };
  502. ts_shdn_l {
  503. nvidia,pins = "pk1";
  504. nvidia,function = "gmi";
  505. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  506. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  507. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  508. };
  509. ph7 {
  510. nvidia,pins = "ph7";
  511. nvidia,function = "gmi";
  512. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  513. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  514. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  515. };
  516. kb_col0_ap {
  517. nvidia,pins = "kb_col0_pq0";
  518. nvidia,function = "rsvd4";
  519. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  520. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  521. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  522. };
  523. lid_open {
  524. nvidia,pins = "kb_row4_pr4";
  525. nvidia,function = "rsvd3";
  526. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  527. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  528. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  529. };
  530. en_vdd_sd {
  531. nvidia,pins = "kb_row0_pr0";
  532. nvidia,function = "rsvd4";
  533. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  534. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  535. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  536. };
  537. ac_ok {
  538. nvidia,pins = "pj0";
  539. nvidia,function = "gmi";
  540. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  541. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  542. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  543. };
  544. sensor_irq_l {
  545. nvidia,pins = "pi6";
  546. nvidia,function = "gmi";
  547. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  548. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  549. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  550. };
  551. wifi_en {
  552. nvidia,pins = "gpio_x7_aud_px7";
  553. nvidia,function = "rsvd4";
  554. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  555. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  556. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  557. };
  558. wifi_rst_l {
  559. nvidia,pins = "clk2_req_pcc5";
  560. nvidia,function = "dap";
  561. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  562. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  563. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  564. };
  565. hp_det_l {
  566. nvidia,pins = "ulpi_data1_po2";
  567. nvidia,function = "spi3";
  568. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  569. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  570. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  571. };
  572. };
  573. };
  574. serial@0,70006000 {
  575. status = "okay";
  576. };
  577. pwm@0,7000a000 {
  578. status = "okay";
  579. };
  580. i2c@0,7000c000 {
  581. status = "okay";
  582. clock-frequency = <100000>;
  583. acodec: audio-codec@10 {
  584. compatible = "maxim,max98090";
  585. reg = <0x10>;
  586. interrupt-parent = <&gpio>;
  587. interrupts = <TEGRA_GPIO(H, 4) GPIO_ACTIVE_HIGH>;
  588. };
  589. };
  590. i2c@0,7000c400 {
  591. status = "okay";
  592. clock-frequency = <100000>;
  593. trackpad@4b {
  594. compatible = "atmel,maxtouch";
  595. reg = <0x4b>;
  596. interrupt-parent = <&gpio>;
  597. interrupts = <TEGRA_GPIO(W, 3) IRQ_TYPE_LEVEL_LOW>;
  598. linux,gpio-keymap = <0 0 0 BTN_LEFT>;
  599. };
  600. };
  601. i2c@0,7000c500 {
  602. status = "okay";
  603. clock-frequency = <100000>;
  604. };
  605. hdmi_ddc: i2c@0,7000c700 {
  606. status = "okay";
  607. clock-frequency = <100000>;
  608. };
  609. i2c@0,7000d000 {
  610. status = "okay";
  611. clock-frequency = <400000>;
  612. pmic: pmic@40 {
  613. compatible = "ams,as3722";
  614. reg = <0x40>;
  615. interrupts = <0 86 IRQ_TYPE_LEVEL_HIGH>;
  616. ams,system-power-controller;
  617. #interrupt-cells = <2>;
  618. interrupt-controller;
  619. gpio-controller;
  620. #gpio-cells = <2>;
  621. pinctrl-names = "default";
  622. pinctrl-0 = <&as3722_default>;
  623. as3722_default: pinmux {
  624. gpio0 {
  625. pins = "gpio0";
  626. function = "gpio";
  627. bias-pull-down;
  628. };
  629. gpio1_2_4_7 {
  630. pins = "gpio1", "gpio2", "gpio4", "gpio7";
  631. function = "gpio";
  632. bias-pull-up;
  633. };
  634. gpio3_6 {
  635. pins = "gpio3", "gpio6";
  636. bias-high-impedance;
  637. };
  638. gpio5 {
  639. pins = "gpio5";
  640. function = "clk32k-out";
  641. };
  642. };
  643. regulators {
  644. vsup-sd2-supply = <&vdd_5v0_sys>;
  645. vsup-sd3-supply = <&vdd_5v0_sys>;
  646. vsup-sd4-supply = <&vdd_5v0_sys>;
  647. vsup-sd5-supply = <&vdd_5v0_sys>;
  648. vin-ldo0-supply = <&vdd_1v35_lp0>;
  649. vin-ldo1-6-supply = <&vdd_3v3_run>;
  650. vin-ldo2-5-7-supply = <&vddio_1v8>;
  651. vin-ldo3-4-supply = <&vdd_3v3_sys>;
  652. vin-ldo9-10-supply = <&vdd_5v0_sys>;
  653. vin-ldo11-supply = <&vdd_3v3_run>;
  654. sd0 {
  655. regulator-name = "+VDD_CPU_AP";
  656. regulator-min-microvolt = <700000>;
  657. regulator-max-microvolt = <1400000>;
  658. regulator-min-microamp = <3500000>;
  659. regulator-max-microamp = <3500000>;
  660. regulator-always-on;
  661. regulator-boot-on;
  662. ams,ext-control = <2>;
  663. };
  664. sd1 {
  665. regulator-name = "+VDD_CORE";
  666. regulator-min-microvolt = <700000>;
  667. regulator-max-microvolt = <1350000>;
  668. regulator-min-microamp = <2500000>;
  669. regulator-max-microamp = <2500000>;
  670. regulator-always-on;
  671. regulator-boot-on;
  672. ams,ext-control = <1>;
  673. };
  674. vdd_1v35_lp0: sd2 {
  675. regulator-name = "+1.35V_LP0(sd2)";
  676. regulator-min-microvolt = <1350000>;
  677. regulator-max-microvolt = <1350000>;
  678. regulator-always-on;
  679. regulator-boot-on;
  680. };
  681. sd3 {
  682. regulator-name = "+1.35V_LP0(sd3)";
  683. regulator-min-microvolt = <1350000>;
  684. regulator-max-microvolt = <1350000>;
  685. regulator-always-on;
  686. regulator-boot-on;
  687. };
  688. vdd_1v05_run: sd4 {
  689. regulator-name = "+1.05V_RUN";
  690. regulator-min-microvolt = <1050000>;
  691. regulator-max-microvolt = <1050000>;
  692. };
  693. vddio_1v8: sd5 {
  694. regulator-name = "+1.8V_VDDIO";
  695. regulator-min-microvolt = <1800000>;
  696. regulator-max-microvolt = <1800000>;
  697. regulator-boot-on;
  698. regulator-always-on;
  699. };
  700. sd6 {
  701. regulator-name = "+VDD_GPU_AP";
  702. regulator-min-microvolt = <650000>;
  703. regulator-max-microvolt = <1200000>;
  704. regulator-min-microamp = <3500000>;
  705. regulator-max-microamp = <3500000>;
  706. regulator-boot-on;
  707. regulator-always-on;
  708. };
  709. ldo0 {
  710. regulator-name = "+1.05V_RUN_AVDD";
  711. regulator-min-microvolt = <1050000>;
  712. regulator-max-microvolt = <1050000>;
  713. regulator-boot-on;
  714. regulator-always-on;
  715. ams,ext-control = <1>;
  716. };
  717. ldo1 {
  718. regulator-name = "+1.8V_RUN_CAM";
  719. regulator-min-microvolt = <1800000>;
  720. regulator-max-microvolt = <1800000>;
  721. };
  722. ldo2 {
  723. regulator-name = "+1.2V_GEN_AVDD";
  724. regulator-min-microvolt = <1200000>;
  725. regulator-max-microvolt = <1200000>;
  726. regulator-boot-on;
  727. regulator-always-on;
  728. };
  729. ldo3 {
  730. regulator-name = "+1.00V_LP0_VDD_RTC";
  731. regulator-min-microvolt = <1000000>;
  732. regulator-max-microvolt = <1000000>;
  733. regulator-boot-on;
  734. regulator-always-on;
  735. ams,enable-tracking;
  736. };
  737. vdd_run_cam: ldo4 {
  738. regulator-name = "+3.3V_RUN_CAM";
  739. regulator-min-microvolt = <2800000>;
  740. regulator-max-microvolt = <2800000>;
  741. };
  742. ldo5 {
  743. regulator-name = "+1.2V_RUN_CAM_FRONT";
  744. regulator-min-microvolt = <1200000>;
  745. regulator-max-microvolt = <1200000>;
  746. };
  747. vddio_sdmmc3: ldo6 {
  748. regulator-name = "+VDDIO_SDMMC3";
  749. regulator-min-microvolt = <1800000>;
  750. regulator-max-microvolt = <3300000>;
  751. };
  752. ldo7 {
  753. regulator-name = "+1.05V_RUN_CAM_REAR";
  754. regulator-min-microvolt = <1050000>;
  755. regulator-max-microvolt = <1050000>;
  756. };
  757. ldo9 {
  758. regulator-name = "+2.8V_RUN_TOUCH";
  759. regulator-min-microvolt = <2800000>;
  760. regulator-max-microvolt = <2800000>;
  761. };
  762. ldo10 {
  763. regulator-name = "+2.8V_RUN_CAM_AF";
  764. regulator-min-microvolt = <2800000>;
  765. regulator-max-microvolt = <2800000>;
  766. };
  767. ldo11 {
  768. regulator-name = "+1.8V_RUN_VPP_FUSE";
  769. regulator-min-microvolt = <1800000>;
  770. regulator-max-microvolt = <1800000>;
  771. };
  772. };
  773. };
  774. };
  775. spi@0,7000d400 {
  776. status = "okay";
  777. cros_ec: cros-ec@0 {
  778. compatible = "google,cros-ec-spi";
  779. spi-max-frequency = <4000000>;
  780. interrupt-parent = <&gpio>;
  781. interrupts = <TEGRA_GPIO(C, 7) IRQ_TYPE_LEVEL_LOW>;
  782. reg = <0>;
  783. google,cros-ec-spi-msg-delay = <2000>;
  784. i2c-tunnel {
  785. compatible = "google,cros-ec-i2c-tunnel";
  786. #address-cells = <1>;
  787. #size-cells = <0>;
  788. google,remote-bus = <0>;
  789. charger: bq24735@9 {
  790. compatible = "ti,bq24735";
  791. reg = <0x9>;
  792. interrupt-parent = <&gpio>;
  793. interrupts = <TEGRA_GPIO(J, 0)
  794. GPIO_ACTIVE_HIGH>;
  795. ti,ac-detect-gpios = <&gpio
  796. TEGRA_GPIO(J, 0)
  797. GPIO_ACTIVE_HIGH>;
  798. };
  799. battery: sbs-battery@b {
  800. compatible = "sbs,sbs-battery";
  801. reg = <0xb>;
  802. sbs,i2c-retry-count = <2>;
  803. sbs,poll-retry-count = <1>;
  804. };
  805. };
  806. };
  807. };
  808. spi@0,7000da00 {
  809. status = "okay";
  810. spi-max-frequency = <25000000>;
  811. spi-flash@0 {
  812. compatible = "winbond,w25q32dw";
  813. reg = <0>;
  814. spi-max-frequency = <20000000>;
  815. };
  816. };
  817. pmc@0,7000e400 {
  818. nvidia,invert-interrupt;
  819. nvidia,suspend-mode = <1>;
  820. nvidia,cpu-pwr-good-time = <500>;
  821. nvidia,cpu-pwr-off-time = <300>;
  822. nvidia,core-pwr-good-time = <641 3845>;
  823. nvidia,core-pwr-off-time = <61036>;
  824. nvidia,core-power-req-active-high;
  825. nvidia,sys-clock-req-active-high;
  826. };
  827. hda@0,70030000 {
  828. status = "okay";
  829. };
  830. sdhci@0,700b0400 {
  831. cd-gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_HIGH>;
  832. power-gpios = <&gpio TEGRA_GPIO(R, 0) GPIO_ACTIVE_HIGH>;
  833. wp-gpios = <&gpio TEGRA_GPIO(Q, 4) GPIO_ACTIVE_LOW>;
  834. status = "okay";
  835. bus-width = <4>;
  836. vqmmc-supply = <&vddio_sdmmc3>;
  837. };
  838. sdhci@0,700b0600 {
  839. status = "okay";
  840. bus-width = <8>;
  841. };
  842. ahub@0,70300000 {
  843. i2s@0,70301100 {
  844. status = "okay";
  845. };
  846. };
  847. usb@0,7d000000 {
  848. status = "okay";
  849. };
  850. usb-phy@0,7d000000 {
  851. status = "okay";
  852. vbus-supply = <&vdd_usb1_vbus>;
  853. };
  854. usb@0,7d004000 {
  855. status = "okay";
  856. };
  857. usb-phy@0,7d004000 {
  858. status = "okay";
  859. vbus-supply = <&vdd_run_cam>;
  860. };
  861. usb@0,7d008000 {
  862. status = "okay";
  863. };
  864. usb-phy@0,7d008000 {
  865. status = "okay";
  866. vbus-supply = <&vdd_usb3_vbus>;
  867. };
  868. backlight: backlight {
  869. compatible = "pwm-backlight";
  870. enable-gpios = <&gpio TEGRA_GPIO(H, 2) GPIO_ACTIVE_HIGH>;
  871. power-supply = <&vdd_led>;
  872. pwms = <&pwm 1 1000000>;
  873. brightness-levels = <0 4 8 16 32 64 128 255>;
  874. default-brightness-level = <6>;
  875. };
  876. clocks {
  877. compatible = "simple-bus";
  878. #address-cells = <1>;
  879. #size-cells = <0>;
  880. clk32k_in: clock@0 {
  881. compatible = "fixed-clock";
  882. reg = <0>;
  883. #clock-cells = <0>;
  884. clock-frequency = <32768>;
  885. };
  886. };
  887. gpio-keys {
  888. compatible = "gpio-keys";
  889. power {
  890. label = "Power";
  891. gpios = <&gpio TEGRA_GPIO(Q, 0) GPIO_ACTIVE_LOW>;
  892. linux,code = <KEY_POWER>;
  893. debounce-interval = <10>;
  894. gpio-key,wakeup;
  895. };
  896. };
  897. panel: panel {
  898. compatible = "lg,lp129qe", "simple-panel";
  899. backlight = <&backlight>;
  900. ddc-i2c-bus = <&dpaux>;
  901. };
  902. regulators {
  903. compatible = "simple-bus";
  904. #address-cells = <1>;
  905. #size-cells = <0>;
  906. vdd_mux: regulator@0 {
  907. compatible = "regulator-fixed";
  908. reg = <0>;
  909. regulator-name = "+VDD_MUX";
  910. regulator-min-microvolt = <12000000>;
  911. regulator-max-microvolt = <12000000>;
  912. regulator-always-on;
  913. regulator-boot-on;
  914. };
  915. vdd_5v0_sys: regulator@1 {
  916. compatible = "regulator-fixed";
  917. reg = <1>;
  918. regulator-name = "+5V_SYS";
  919. regulator-min-microvolt = <5000000>;
  920. regulator-max-microvolt = <5000000>;
  921. regulator-always-on;
  922. regulator-boot-on;
  923. vin-supply = <&vdd_mux>;
  924. };
  925. vdd_3v3_sys: regulator@2 {
  926. compatible = "regulator-fixed";
  927. reg = <2>;
  928. regulator-name = "+3.3V_SYS";
  929. regulator-min-microvolt = <3300000>;
  930. regulator-max-microvolt = <3300000>;
  931. regulator-always-on;
  932. regulator-boot-on;
  933. vin-supply = <&vdd_mux>;
  934. };
  935. vdd_3v3_run: regulator@3 {
  936. compatible = "regulator-fixed";
  937. reg = <3>;
  938. regulator-name = "+3.3V_RUN";
  939. regulator-min-microvolt = <3300000>;
  940. regulator-max-microvolt = <3300000>;
  941. regulator-always-on;
  942. regulator-boot-on;
  943. gpio = <&pmic 1 GPIO_ACTIVE_HIGH>;
  944. enable-active-high;
  945. vin-supply = <&vdd_3v3_sys>;
  946. };
  947. vdd_3v3_hdmi: regulator@4 {
  948. compatible = "regulator-fixed";
  949. reg = <4>;
  950. regulator-name = "+3.3V_AVDD_HDMI_AP_GATED";
  951. regulator-min-microvolt = <3300000>;
  952. regulator-max-microvolt = <3300000>;
  953. vin-supply = <&vdd_3v3_run>;
  954. };
  955. vdd_led: regulator@5 {
  956. compatible = "regulator-fixed";
  957. reg = <5>;
  958. regulator-name = "+VDD_LED";
  959. gpio = <&gpio TEGRA_GPIO(P, 2) GPIO_ACTIVE_HIGH>;
  960. enable-active-high;
  961. vin-supply = <&vdd_mux>;
  962. };
  963. vdd_5v0_ts: regulator@6 {
  964. compatible = "regulator-fixed";
  965. reg = <6>;
  966. regulator-name = "+5V_VDD_TS_SW";
  967. regulator-min-microvolt = <5000000>;
  968. regulator-max-microvolt = <5000000>;
  969. regulator-boot-on;
  970. gpio = <&gpio TEGRA_GPIO(K, 1) GPIO_ACTIVE_HIGH>;
  971. enable-active-high;
  972. vin-supply = <&vdd_5v0_sys>;
  973. };
  974. vdd_usb1_vbus: regulator@7 {
  975. compatible = "regulator-fixed";
  976. reg = <7>;
  977. regulator-name = "+5V_USB_HS";
  978. regulator-min-microvolt = <5000000>;
  979. regulator-max-microvolt = <5000000>;
  980. gpio = <&gpio TEGRA_GPIO(N, 4) GPIO_ACTIVE_HIGH>;
  981. enable-active-high;
  982. gpio-open-drain;
  983. vin-supply = <&vdd_5v0_sys>;
  984. };
  985. vdd_usb3_vbus: regulator@8 {
  986. compatible = "regulator-fixed";
  987. reg = <8>;
  988. regulator-name = "+5V_USB_SS";
  989. regulator-min-microvolt = <5000000>;
  990. regulator-max-microvolt = <5000000>;
  991. gpio = <&gpio TEGRA_GPIO(N, 5) GPIO_ACTIVE_HIGH>;
  992. enable-active-high;
  993. gpio-open-drain;
  994. vin-supply = <&vdd_5v0_sys>;
  995. };
  996. vdd_3v3_panel: regulator@9 {
  997. compatible = "regulator-fixed";
  998. reg = <9>;
  999. regulator-name = "+3.3V_PANEL";
  1000. regulator-min-microvolt = <3300000>;
  1001. regulator-max-microvolt = <3300000>;
  1002. gpio = <&pmic 4 GPIO_ACTIVE_HIGH>;
  1003. enable-active-high;
  1004. vin-supply = <&vdd_3v3_run>;
  1005. };
  1006. vdd_3v3_lp0: regulator@10 {
  1007. compatible = "regulator-fixed";
  1008. reg = <10>;
  1009. regulator-name = "+3.3V_LP0";
  1010. regulator-min-microvolt = <3300000>;
  1011. regulator-max-microvolt = <3300000>;
  1012. /*
  1013. * TODO: find a way to wire this up with the USB EHCI
  1014. * controllers so that it can be enabled on demand.
  1015. */
  1016. regulator-always-on;
  1017. gpio = <&pmic 2 GPIO_ACTIVE_HIGH>;
  1018. enable-active-high;
  1019. vin-supply = <&vdd_3v3_sys>;
  1020. };
  1021. vdd_hdmi_pll: regulator@11 {
  1022. compatible = "regulator-fixed";
  1023. reg = <11>;
  1024. regulator-name = "+1.05V_RUN_AVDD_HDMI_PLL";
  1025. regulator-min-microvolt = <1050000>;
  1026. regulator-max-microvolt = <1050000>;
  1027. gpio = <&gpio TEGRA_GPIO(H, 7) GPIO_ACTIVE_LOW>;
  1028. vin-supply = <&vdd_1v05_run>;
  1029. };
  1030. vdd_5v0_hdmi: regulator@12 {
  1031. compatible = "regulator-fixed";
  1032. reg = <12>;
  1033. regulator-name = "+5V_HDMI_CON";
  1034. regulator-min-microvolt = <5000000>;
  1035. regulator-max-microvolt = <5000000>;
  1036. gpio = <&gpio TEGRA_GPIO(K, 6) GPIO_ACTIVE_HIGH>;
  1037. enable-active-high;
  1038. vin-supply = <&vdd_5v0_sys>;
  1039. };
  1040. };
  1041. sound {
  1042. compatible = "nvidia,tegra-audio-max98090-venice2",
  1043. "nvidia,tegra-audio-max98090";
  1044. nvidia,model = "NVIDIA Tegra Venice2";
  1045. nvidia,audio-routing =
  1046. "Headphones", "HPR",
  1047. "Headphones", "HPL",
  1048. "Speakers", "SPKR",
  1049. "Speakers", "SPKL",
  1050. "Mic Jack", "MICBIAS",
  1051. "IN34", "Mic Jack";
  1052. nvidia,i2s-controller = <&tegra_i2s1>;
  1053. nvidia,audio-codec = <&acodec>;
  1054. clocks = <&tegra_car TEGRA124_CLK_PLL_A>,
  1055. <&tegra_car TEGRA124_CLK_PLL_A_OUT0>,
  1056. <&tegra_car TEGRA124_CLK_EXTERN1>;
  1057. clock-names = "pll_a", "pll_a_out0", "mclk";
  1058. };
  1059. };
  1060. #include "cros-ec-keyboard.dtsi"