tegra20-colibri-512.dtsi 14 KB

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  1. #include "tegra20.dtsi"
  2. / {
  3. model = "Toradex Colibri T20 512MB";
  4. compatible = "toradex,colibri_t20-512", "nvidia,tegra20";
  5. aliases {
  6. rtc0 = "/i2c@7000d000/tps6586x@34";
  7. rtc1 = "/rtc@7000e000";
  8. };
  9. memory {
  10. reg = <0x00000000 0x20000000>;
  11. };
  12. host1x@50000000 {
  13. hdmi@54280000 {
  14. vdd-supply = <&hdmi_vdd_reg>;
  15. pll-supply = <&hdmi_pll_reg>;
  16. nvidia,ddc-i2c-bus = <&i2c_ddc>;
  17. nvidia,hpd-gpio = <&gpio TEGRA_GPIO(N, 7)
  18. GPIO_ACTIVE_HIGH>;
  19. };
  20. };
  21. pinmux@70000014 {
  22. pinctrl-names = "default";
  23. pinctrl-0 = <&state_default>;
  24. state_default: pinmux {
  25. audio_refclk {
  26. nvidia,pins = "cdev1";
  27. nvidia,function = "plla_out";
  28. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  29. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  30. };
  31. crt {
  32. nvidia,pins = "crtp";
  33. nvidia,function = "crt";
  34. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  35. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  36. };
  37. dap3 {
  38. nvidia,pins = "dap3";
  39. nvidia,function = "dap3";
  40. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  41. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  42. };
  43. displaya {
  44. nvidia,pins = "ld0", "ld1", "ld2", "ld3",
  45. "ld4", "ld5", "ld6", "ld7", "ld8",
  46. "ld9", "ld10", "ld11", "ld12", "ld13",
  47. "ld14", "ld15", "ld16", "ld17",
  48. "lhs", "lpw0", "lpw2", "lsc0",
  49. "lsc1", "lsck", "lsda", "lspi", "lvs";
  50. nvidia,function = "displaya";
  51. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  52. };
  53. gpio_dte {
  54. nvidia,pins = "dte";
  55. nvidia,function = "rsvd1";
  56. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  57. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  58. };
  59. gpio_gmi {
  60. nvidia,pins = "ata", "atc", "atd", "ate",
  61. "dap1", "dap2", "dap4", "gpu", "irrx",
  62. "irtx", "spia", "spib", "spic";
  63. nvidia,function = "gmi";
  64. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  65. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  66. };
  67. gpio_pta {
  68. nvidia,pins = "pta";
  69. nvidia,function = "rsvd4";
  70. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  71. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  72. };
  73. gpio_uac {
  74. nvidia,pins = "uac";
  75. nvidia,function = "rsvd2";
  76. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  77. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  78. };
  79. hdint {
  80. nvidia,pins = "hdint";
  81. nvidia,function = "hdmi";
  82. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  83. };
  84. i2c1 {
  85. nvidia,pins = "rm";
  86. nvidia,function = "i2c1";
  87. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  88. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  89. };
  90. i2c3 {
  91. nvidia,pins = "dtf";
  92. nvidia,function = "i2c3";
  93. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  94. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  95. };
  96. i2cddc {
  97. nvidia,pins = "ddc";
  98. nvidia,function = "i2c2";
  99. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  100. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  101. };
  102. i2cp {
  103. nvidia,pins = "i2cp";
  104. nvidia,function = "i2cp";
  105. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  106. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  107. };
  108. irda {
  109. nvidia,pins = "uad";
  110. nvidia,function = "irda";
  111. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  112. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  113. };
  114. nand {
  115. nvidia,pins = "kbca", "kbcc", "kbcd",
  116. "kbce", "kbcf";
  117. nvidia,function = "nand";
  118. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  119. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  120. };
  121. owc {
  122. nvidia,pins = "owc";
  123. nvidia,function = "owr";
  124. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  125. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  126. };
  127. pmc {
  128. nvidia,pins = "pmc";
  129. nvidia,function = "pwr_on";
  130. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  131. };
  132. pwm {
  133. nvidia,pins = "sdb", "sdc", "sdd";
  134. nvidia,function = "pwm";
  135. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  136. };
  137. sdio4 {
  138. nvidia,pins = "atb", "gma", "gme";
  139. nvidia,function = "sdio4";
  140. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  141. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  142. };
  143. spi1 {
  144. nvidia,pins = "spid", "spie", "spif";
  145. nvidia,function = "spi1";
  146. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  147. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  148. };
  149. spi4 {
  150. nvidia,pins = "slxa", "slxc", "slxd", "slxk";
  151. nvidia,function = "spi4";
  152. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  153. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  154. };
  155. uarta {
  156. nvidia,pins = "sdio1";
  157. nvidia,function = "uarta";
  158. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  159. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  160. };
  161. uartd {
  162. nvidia,pins = "gmc";
  163. nvidia,function = "uartd";
  164. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  165. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  166. };
  167. ulpi {
  168. nvidia,pins = "uaa", "uab", "uda";
  169. nvidia,function = "ulpi";
  170. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  171. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  172. };
  173. ulpi_refclk {
  174. nvidia,pins = "cdev2";
  175. nvidia,function = "pllp_out4";
  176. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  177. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  178. };
  179. usb_gpio {
  180. nvidia,pins = "spig", "spih";
  181. nvidia,function = "spi2_alt";
  182. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  183. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  184. };
  185. vi {
  186. nvidia,pins = "dta", "dtb", "dtc", "dtd";
  187. nvidia,function = "vi";
  188. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  189. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  190. };
  191. vi_sc {
  192. nvidia,pins = "csus";
  193. nvidia,function = "vi_sensor_clk";
  194. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  195. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  196. };
  197. };
  198. };
  199. ac97: ac97@70002000 {
  200. status = "okay";
  201. nvidia,codec-reset-gpio = <&gpio TEGRA_GPIO(V, 0)
  202. GPIO_ACTIVE_HIGH>;
  203. nvidia,codec-sync-gpio = <&gpio TEGRA_GPIO(P, 0)
  204. GPIO_ACTIVE_HIGH>;
  205. };
  206. i2c@7000c000 {
  207. clock-frequency = <400000>;
  208. };
  209. i2c_ddc: i2c@7000c400 {
  210. clock-frequency = <100000>;
  211. };
  212. i2c@7000c500 {
  213. clock-frequency = <400000>;
  214. };
  215. i2c@7000d000 {
  216. status = "okay";
  217. clock-frequency = <400000>;
  218. pmic: tps6586x@34 {
  219. compatible = "ti,tps6586x";
  220. reg = <0x34>;
  221. interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
  222. ti,system-power-controller;
  223. #gpio-cells = <2>;
  224. gpio-controller;
  225. sys-supply = <&vdd_3v3_reg>;
  226. vin-sm0-supply = <&sys_reg>;
  227. vin-sm1-supply = <&sys_reg>;
  228. vin-sm2-supply = <&sys_reg>;
  229. vinldo01-supply = <&sm2_reg>;
  230. vinldo23-supply = <&vdd_3v3_reg>;
  231. vinldo4-supply = <&vdd_3v3_reg>;
  232. vinldo678-supply = <&vdd_3v3_reg>;
  233. vinldo9-supply = <&vdd_3v3_reg>;
  234. regulators {
  235. #address-cells = <1>;
  236. #size-cells = <0>;
  237. sys_reg: regulator@0 {
  238. reg = <0>;
  239. regulator-compatible = "sys";
  240. regulator-name = "vdd_sys";
  241. regulator-always-on;
  242. };
  243. regulator@1 {
  244. reg = <1>;
  245. regulator-compatible = "sm0";
  246. regulator-name = "vdd_sm0,vdd_core";
  247. regulator-min-microvolt = <1200000>;
  248. regulator-max-microvolt = <1200000>;
  249. regulator-always-on;
  250. };
  251. regulator@2 {
  252. reg = <2>;
  253. regulator-compatible = "sm1";
  254. regulator-name = "vdd_sm1,vdd_cpu";
  255. regulator-min-microvolt = <1000000>;
  256. regulator-max-microvolt = <1000000>;
  257. regulator-always-on;
  258. };
  259. sm2_reg: regulator@3 {
  260. reg = <3>;
  261. regulator-compatible = "sm2";
  262. regulator-name = "vdd_sm2,vin_ldo*";
  263. regulator-min-microvolt = <1800000>;
  264. regulator-max-microvolt = <1800000>;
  265. regulator-always-on;
  266. };
  267. /* LDO0 is not connected to anything */
  268. regulator@5 {
  269. reg = <5>;
  270. regulator-compatible = "ldo1";
  271. regulator-name = "vdd_ldo1,avdd_pll*";
  272. regulator-min-microvolt = <1100000>;
  273. regulator-max-microvolt = <1100000>;
  274. regulator-always-on;
  275. };
  276. regulator@6 {
  277. reg = <6>;
  278. regulator-compatible = "ldo2";
  279. regulator-name = "vdd_ldo2,vdd_rtc";
  280. regulator-min-microvolt = <1200000>;
  281. regulator-max-microvolt = <1200000>;
  282. };
  283. /* LDO3 is not connected to anything */
  284. regulator@8 {
  285. reg = <8>;
  286. regulator-compatible = "ldo4";
  287. regulator-name = "vdd_ldo4,avdd_osc,vddio_sys";
  288. regulator-min-microvolt = <1800000>;
  289. regulator-max-microvolt = <1800000>;
  290. regulator-always-on;
  291. };
  292. ldo5_reg: regulator@9 {
  293. reg = <9>;
  294. regulator-compatible = "ldo5";
  295. regulator-name = "vdd_ldo5,vdd_fuse";
  296. regulator-min-microvolt = <3300000>;
  297. regulator-max-microvolt = <3300000>;
  298. regulator-always-on;
  299. };
  300. regulator@10 {
  301. reg = <10>;
  302. regulator-compatible = "ldo6";
  303. regulator-name = "vdd_ldo6,avdd_vdac,vddio_vi,vddio_cam";
  304. regulator-min-microvolt = <2850000>;
  305. regulator-max-microvolt = <2850000>;
  306. };
  307. hdmi_vdd_reg: regulator@11 {
  308. reg = <11>;
  309. regulator-compatible = "ldo7";
  310. regulator-name = "vdd_ldo7,avdd_hdmi";
  311. regulator-min-microvolt = <3300000>;
  312. regulator-max-microvolt = <3300000>;
  313. };
  314. hdmi_pll_reg: regulator@12 {
  315. reg = <12>;
  316. regulator-compatible = "ldo8";
  317. regulator-name = "vdd_ldo8,avdd_hdmi_pll";
  318. regulator-min-microvolt = <1800000>;
  319. regulator-max-microvolt = <1800000>;
  320. };
  321. regulator@13 {
  322. reg = <13>;
  323. regulator-compatible = "ldo9";
  324. regulator-name = "vdd_ldo9,avdd_2v85,vdd_ddr_rx";
  325. regulator-min-microvolt = <2850000>;
  326. regulator-max-microvolt = <2850000>;
  327. regulator-always-on;
  328. };
  329. regulator@14 {
  330. reg = <14>;
  331. regulator-compatible = "ldo_rtc";
  332. regulator-name = "vdd_rtc_out,vdd_cell";
  333. regulator-min-microvolt = <3300000>;
  334. regulator-max-microvolt = <3300000>;
  335. regulator-always-on;
  336. };
  337. };
  338. };
  339. temperature-sensor@4c {
  340. compatible = "national,lm95245";
  341. reg = <0x4c>;
  342. };
  343. };
  344. pmc@7000e400 {
  345. nvidia,suspend-mode = <1>;
  346. nvidia,cpu-pwr-good-time = <5000>;
  347. nvidia,cpu-pwr-off-time = <5000>;
  348. nvidia,core-pwr-good-time = <3845 3845>;
  349. nvidia,core-pwr-off-time = <3875>;
  350. nvidia,sys-clock-req-active-high;
  351. };
  352. memory-controller@7000f400 {
  353. emc-table@83250 {
  354. reg = <83250>;
  355. compatible = "nvidia,tegra20-emc-table";
  356. clock-frequency = <83250>;
  357. nvidia,emc-registers = <0x00000005 0x00000011
  358. 0x00000004 0x00000002 0x00000004 0x00000004
  359. 0x00000001 0x0000000a 0x00000002 0x00000002
  360. 0x00000001 0x00000001 0x00000003 0x00000004
  361. 0x00000003 0x00000009 0x0000000c 0x0000025f
  362. 0x00000000 0x00000003 0x00000003 0x00000002
  363. 0x00000002 0x00000001 0x00000008 0x000000c8
  364. 0x00000003 0x00000005 0x00000003 0x0000000c
  365. 0x00000002 0x00000000 0x00000000 0x00000002
  366. 0x00000000 0x00000000 0x00000083 0x00520006
  367. 0x00000010 0x00000008 0x00000000 0x00000000
  368. 0x00000000 0x00000000 0x00000000 0x00000000>;
  369. };
  370. emc-table@133200 {
  371. reg = <133200>;
  372. compatible = "nvidia,tegra20-emc-table";
  373. clock-frequency = <133200>;
  374. nvidia,emc-registers = <0x00000008 0x00000019
  375. 0x00000006 0x00000002 0x00000004 0x00000004
  376. 0x00000001 0x0000000a 0x00000002 0x00000002
  377. 0x00000002 0x00000001 0x00000003 0x00000004
  378. 0x00000003 0x00000009 0x0000000c 0x0000039f
  379. 0x00000000 0x00000003 0x00000003 0x00000002
  380. 0x00000002 0x00000001 0x00000008 0x000000c8
  381. 0x00000003 0x00000007 0x00000003 0x0000000c
  382. 0x00000002 0x00000000 0x00000000 0x00000002
  383. 0x00000000 0x00000000 0x00000083 0x00510006
  384. 0x00000010 0x00000008 0x00000000 0x00000000
  385. 0x00000000 0x00000000 0x00000000 0x00000000>;
  386. };
  387. emc-table@166500 {
  388. reg = <166500>;
  389. compatible = "nvidia,tegra20-emc-table";
  390. clock-frequency = <166500>;
  391. nvidia,emc-registers = <0x0000000a 0x00000021
  392. 0x00000008 0x00000003 0x00000004 0x00000004
  393. 0x00000002 0x0000000a 0x00000003 0x00000003
  394. 0x00000002 0x00000001 0x00000003 0x00000004
  395. 0x00000003 0x00000009 0x0000000c 0x000004df
  396. 0x00000000 0x00000003 0x00000003 0x00000003
  397. 0x00000003 0x00000001 0x00000009 0x000000c8
  398. 0x00000003 0x00000009 0x00000004 0x0000000c
  399. 0x00000002 0x00000000 0x00000000 0x00000002
  400. 0x00000000 0x00000000 0x00000083 0x004f0006
  401. 0x00000010 0x00000008 0x00000000 0x00000000
  402. 0x00000000 0x00000000 0x00000000 0x00000000>;
  403. };
  404. emc-table@333000 {
  405. reg = <333000>;
  406. compatible = "nvidia,tegra20-emc-table";
  407. clock-frequency = <333000>;
  408. nvidia,emc-registers = <0x00000014 0x00000041
  409. 0x0000000f 0x00000005 0x00000004 0x00000005
  410. 0x00000003 0x0000000a 0x00000005 0x00000005
  411. 0x00000004 0x00000001 0x00000003 0x00000004
  412. 0x00000003 0x00000009 0x0000000c 0x000009ff
  413. 0x00000000 0x00000003 0x00000003 0x00000005
  414. 0x00000005 0x00000001 0x0000000e 0x000000c8
  415. 0x00000003 0x00000011 0x00000006 0x0000000c
  416. 0x00000002 0x00000000 0x00000000 0x00000002
  417. 0x00000000 0x00000000 0x00000083 0x00380006
  418. 0x00000010 0x00000008 0x00000000 0x00000000
  419. 0x00000000 0x00000000 0x00000000 0x00000000>;
  420. };
  421. };
  422. usb@c5004000 {
  423. status = "okay";
  424. nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 1)
  425. GPIO_ACTIVE_LOW>;
  426. };
  427. usb-phy@c5004000 {
  428. status = "okay";
  429. nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 1)
  430. GPIO_ACTIVE_LOW>;
  431. };
  432. sdhci@c8000600 {
  433. cd-gpios = <&gpio TEGRA_GPIO(C, 7) GPIO_ACTIVE_LOW>;
  434. };
  435. clocks {
  436. compatible = "simple-bus";
  437. #address-cells = <1>;
  438. #size-cells = <0>;
  439. clk32k_in: clock@0 {
  440. compatible = "fixed-clock";
  441. reg=<0>;
  442. #clock-cells = <0>;
  443. clock-frequency = <32768>;
  444. };
  445. };
  446. regulators {
  447. compatible = "simple-bus";
  448. #address-cells = <1>;
  449. #size-cells = <0>;
  450. vdd_3v3_reg: regulator@100 {
  451. compatible = "regulator-fixed";
  452. reg = <100>;
  453. regulator-name = "vdd_3v3";
  454. regulator-min-microvolt = <3300000>;
  455. regulator-max-microvolt = <3300000>;
  456. regulator-always-on;
  457. };
  458. regulator@101 {
  459. compatible = "regulator-fixed";
  460. reg = <101>;
  461. regulator-name = "internal_usb";
  462. regulator-min-microvolt = <5000000>;
  463. regulator-max-microvolt = <5000000>;
  464. enable-active-high;
  465. regulator-boot-on;
  466. regulator-always-on;
  467. gpio = <&gpio TEGRA_GPIO(BB, 1) GPIO_ACTIVE_HIGH>;
  468. };
  469. };
  470. sound {
  471. compatible = "nvidia,tegra-audio-wm9712-colibri_t20",
  472. "nvidia,tegra-audio-wm9712";
  473. nvidia,model = "Colibri T20 AC97 Audio";
  474. nvidia,audio-routing =
  475. "Headphone", "HPOUTL",
  476. "Headphone", "HPOUTR",
  477. "LineIn", "LINEINL",
  478. "LineIn", "LINEINR",
  479. "Mic", "MIC1";
  480. nvidia,ac97-controller = <&ac97>;
  481. clocks = <&tegra_car TEGRA20_CLK_PLL_A>,
  482. <&tegra_car TEGRA20_CLK_PLL_A_OUT0>,
  483. <&tegra_car TEGRA20_CLK_CDEV1>;
  484. clock-names = "pll_a", "pll_a_out0", "mclk";
  485. };
  486. };