tegra20-harmony.dts 19 KB

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  1. /dts-v1/;
  2. #include <dt-bindings/input/input.h>
  3. #include "tegra20.dtsi"
  4. / {
  5. model = "NVIDIA Tegra20 Harmony evaluation board";
  6. compatible = "nvidia,harmony", "nvidia,tegra20";
  7. aliases {
  8. rtc0 = "/i2c@7000d000/tps6586x@34";
  9. rtc1 = "/rtc@7000e000";
  10. serial0 = &uartd;
  11. };
  12. memory {
  13. reg = <0x00000000 0x40000000>;
  14. };
  15. host1x@50000000 {
  16. dc@54200000 {
  17. rgb {
  18. status = "okay";
  19. nvidia,panel = <&panel>;
  20. };
  21. };
  22. hdmi@54280000 {
  23. status = "okay";
  24. hdmi-supply = <&vdd_5v0_hdmi>;
  25. vdd-supply = <&hdmi_vdd_reg>;
  26. pll-supply = <&hdmi_pll_reg>;
  27. nvidia,ddc-i2c-bus = <&hdmi_ddc>;
  28. nvidia,hpd-gpio = <&gpio TEGRA_GPIO(N, 7)
  29. GPIO_ACTIVE_HIGH>;
  30. };
  31. };
  32. pinmux@70000014 {
  33. pinctrl-names = "default";
  34. pinctrl-0 = <&state_default>;
  35. state_default: pinmux {
  36. ata {
  37. nvidia,pins = "ata";
  38. nvidia,function = "ide";
  39. };
  40. atb {
  41. nvidia,pins = "atb", "gma", "gme";
  42. nvidia,function = "sdio4";
  43. };
  44. atc {
  45. nvidia,pins = "atc";
  46. nvidia,function = "nand";
  47. };
  48. atd {
  49. nvidia,pins = "atd", "ate", "gmb", "gmd", "gpu",
  50. "spia", "spib", "spic";
  51. nvidia,function = "gmi";
  52. };
  53. cdev1 {
  54. nvidia,pins = "cdev1";
  55. nvidia,function = "plla_out";
  56. };
  57. cdev2 {
  58. nvidia,pins = "cdev2";
  59. nvidia,function = "pllp_out4";
  60. };
  61. crtp {
  62. nvidia,pins = "crtp";
  63. nvidia,function = "crt";
  64. };
  65. csus {
  66. nvidia,pins = "csus";
  67. nvidia,function = "vi_sensor_clk";
  68. };
  69. dap1 {
  70. nvidia,pins = "dap1";
  71. nvidia,function = "dap1";
  72. };
  73. dap2 {
  74. nvidia,pins = "dap2";
  75. nvidia,function = "dap2";
  76. };
  77. dap3 {
  78. nvidia,pins = "dap3";
  79. nvidia,function = "dap3";
  80. };
  81. dap4 {
  82. nvidia,pins = "dap4";
  83. nvidia,function = "dap4";
  84. };
  85. ddc {
  86. nvidia,pins = "ddc";
  87. nvidia,function = "i2c2";
  88. };
  89. dta {
  90. nvidia,pins = "dta", "dtd";
  91. nvidia,function = "sdio2";
  92. };
  93. dtb {
  94. nvidia,pins = "dtb", "dtc", "dte";
  95. nvidia,function = "rsvd1";
  96. };
  97. dtf {
  98. nvidia,pins = "dtf";
  99. nvidia,function = "i2c3";
  100. };
  101. gmc {
  102. nvidia,pins = "gmc";
  103. nvidia,function = "uartd";
  104. };
  105. gpu7 {
  106. nvidia,pins = "gpu7";
  107. nvidia,function = "rtck";
  108. };
  109. gpv {
  110. nvidia,pins = "gpv", "slxa", "slxk";
  111. nvidia,function = "pcie";
  112. };
  113. hdint {
  114. nvidia,pins = "hdint", "pta";
  115. nvidia,function = "hdmi";
  116. };
  117. i2cp {
  118. nvidia,pins = "i2cp";
  119. nvidia,function = "i2cp";
  120. };
  121. irrx {
  122. nvidia,pins = "irrx", "irtx";
  123. nvidia,function = "uarta";
  124. };
  125. kbca {
  126. nvidia,pins = "kbca", "kbcb", "kbcc", "kbcd",
  127. "kbce", "kbcf";
  128. nvidia,function = "kbc";
  129. };
  130. lcsn {
  131. nvidia,pins = "lcsn", "ld0", "ld1", "ld2",
  132. "ld3", "ld4", "ld5", "ld6", "ld7",
  133. "ld8", "ld9", "ld10", "ld11", "ld12",
  134. "ld13", "ld14", "ld15", "ld16", "ld17",
  135. "ldc", "ldi", "lhp0", "lhp1", "lhp2",
  136. "lhs", "lm0", "lm1", "lpp", "lpw0",
  137. "lpw1", "lpw2", "lsc0", "lsc1", "lsck",
  138. "lsda", "lsdi", "lspi", "lvp0", "lvp1",
  139. "lvs";
  140. nvidia,function = "displaya";
  141. };
  142. owc {
  143. nvidia,pins = "owc", "spdi", "spdo", "uac";
  144. nvidia,function = "rsvd2";
  145. };
  146. pmc {
  147. nvidia,pins = "pmc";
  148. nvidia,function = "pwr_on";
  149. };
  150. rm {
  151. nvidia,pins = "rm";
  152. nvidia,function = "i2c1";
  153. };
  154. sdb {
  155. nvidia,pins = "sdb", "sdc", "sdd";
  156. nvidia,function = "pwm";
  157. };
  158. sdio1 {
  159. nvidia,pins = "sdio1";
  160. nvidia,function = "sdio1";
  161. };
  162. slxc {
  163. nvidia,pins = "slxc", "slxd";
  164. nvidia,function = "spdif";
  165. };
  166. spid {
  167. nvidia,pins = "spid", "spie", "spif";
  168. nvidia,function = "spi1";
  169. };
  170. spig {
  171. nvidia,pins = "spig", "spih";
  172. nvidia,function = "spi2_alt";
  173. };
  174. uaa {
  175. nvidia,pins = "uaa", "uab", "uda";
  176. nvidia,function = "ulpi";
  177. };
  178. uad {
  179. nvidia,pins = "uad";
  180. nvidia,function = "irda";
  181. };
  182. uca {
  183. nvidia,pins = "uca", "ucb";
  184. nvidia,function = "uartc";
  185. };
  186. conf_ata {
  187. nvidia,pins = "ata", "atb", "atc", "atd", "ate",
  188. "cdev1", "cdev2", "dap1", "dtb", "gma",
  189. "gmb", "gmc", "gmd", "gme", "gpu7",
  190. "gpv", "i2cp", "pta", "rm", "slxa",
  191. "slxk", "spia", "spib", "uac";
  192. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  193. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  194. };
  195. conf_ck32 {
  196. nvidia,pins = "ck32", "ddrc", "pmca", "pmcb",
  197. "pmcc", "pmcd", "pmce", "xm2c", "xm2d";
  198. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  199. };
  200. conf_csus {
  201. nvidia,pins = "csus", "spid", "spif";
  202. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  203. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  204. };
  205. conf_crtp {
  206. nvidia,pins = "crtp", "dap2", "dap3", "dap4",
  207. "dtc", "dte", "dtf", "gpu", "sdio1",
  208. "slxc", "slxd", "spdi", "spdo", "spig",
  209. "uda";
  210. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  211. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  212. };
  213. conf_ddc {
  214. nvidia,pins = "ddc", "dta", "dtd", "kbca",
  215. "kbcb", "kbcc", "kbcd", "kbce", "kbcf",
  216. "sdc";
  217. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  218. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  219. };
  220. conf_hdint {
  221. nvidia,pins = "hdint", "lcsn", "ldc", "lm1",
  222. "lpw1", "lsc1", "lsck", "lsda", "lsdi",
  223. "lvp0", "owc", "sdb";
  224. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  225. };
  226. conf_irrx {
  227. nvidia,pins = "irrx", "irtx", "sdd", "spic",
  228. "spie", "spih", "uaa", "uab", "uad",
  229. "uca", "ucb";
  230. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  231. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  232. };
  233. conf_lc {
  234. nvidia,pins = "lc", "ls";
  235. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  236. };
  237. conf_ld0 {
  238. nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4",
  239. "ld5", "ld6", "ld7", "ld8", "ld9",
  240. "ld10", "ld11", "ld12", "ld13", "ld14",
  241. "ld15", "ld16", "ld17", "ldi", "lhp0",
  242. "lhp1", "lhp2", "lhs", "lm0", "lpp",
  243. "lpw0", "lpw2", "lsc0", "lspi", "lvp1",
  244. "lvs", "pmc";
  245. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  246. };
  247. conf_ld17_0 {
  248. nvidia,pins = "ld17_0", "ld19_18", "ld21_20",
  249. "ld23_22";
  250. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  251. };
  252. };
  253. };
  254. i2s@70002800 {
  255. status = "okay";
  256. };
  257. serial@70006300 {
  258. status = "okay";
  259. };
  260. pwm: pwm@7000a000 {
  261. status = "okay";
  262. };
  263. i2c@7000c000 {
  264. status = "okay";
  265. clock-frequency = <400000>;
  266. wm8903: wm8903@1a {
  267. compatible = "wlf,wm8903";
  268. reg = <0x1a>;
  269. interrupt-parent = <&gpio>;
  270. interrupts = <TEGRA_GPIO(X, 3) IRQ_TYPE_LEVEL_HIGH>;
  271. gpio-controller;
  272. #gpio-cells = <2>;
  273. micdet-cfg = <0>;
  274. micdet-delay = <100>;
  275. gpio-cfg = <0xffffffff 0xffffffff 0 0xffffffff 0xffffffff>;
  276. };
  277. };
  278. hdmi_ddc: i2c@7000c400 {
  279. status = "okay";
  280. clock-frequency = <100000>;
  281. };
  282. i2c@7000c500 {
  283. status = "okay";
  284. clock-frequency = <400000>;
  285. };
  286. i2c@7000d000 {
  287. status = "okay";
  288. clock-frequency = <400000>;
  289. pmic: tps6586x@34 {
  290. compatible = "ti,tps6586x";
  291. reg = <0x34>;
  292. interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
  293. ti,system-power-controller;
  294. #gpio-cells = <2>;
  295. gpio-controller;
  296. sys-supply = <&vdd_5v0_reg>;
  297. vin-sm0-supply = <&sys_reg>;
  298. vin-sm1-supply = <&sys_reg>;
  299. vin-sm2-supply = <&sys_reg>;
  300. vinldo01-supply = <&sm2_reg>;
  301. vinldo23-supply = <&sm2_reg>;
  302. vinldo4-supply = <&sm2_reg>;
  303. vinldo678-supply = <&sm2_reg>;
  304. vinldo9-supply = <&sm2_reg>;
  305. regulators {
  306. sys_reg: sys {
  307. regulator-name = "vdd_sys";
  308. regulator-always-on;
  309. };
  310. sm0 {
  311. regulator-name = "vdd_sm0,vdd_core";
  312. regulator-min-microvolt = <1200000>;
  313. regulator-max-microvolt = <1200000>;
  314. regulator-always-on;
  315. };
  316. sm1 {
  317. regulator-name = "vdd_sm1,vdd_cpu";
  318. regulator-min-microvolt = <1000000>;
  319. regulator-max-microvolt = <1000000>;
  320. regulator-always-on;
  321. };
  322. sm2_reg: sm2 {
  323. regulator-name = "vdd_sm2,vin_ldo*";
  324. regulator-min-microvolt = <3700000>;
  325. regulator-max-microvolt = <3700000>;
  326. regulator-always-on;
  327. };
  328. pci_clk_reg: ldo0 {
  329. regulator-name = "vdd_ldo0,vddio_pex_clk";
  330. regulator-min-microvolt = <3300000>;
  331. regulator-max-microvolt = <3300000>;
  332. };
  333. ldo1 {
  334. regulator-name = "vdd_ldo1,avdd_pll*";
  335. regulator-min-microvolt = <1100000>;
  336. regulator-max-microvolt = <1100000>;
  337. regulator-always-on;
  338. };
  339. ldo2 {
  340. regulator-name = "vdd_ldo2,vdd_rtc";
  341. regulator-min-microvolt = <1200000>;
  342. regulator-max-microvolt = <1200000>;
  343. };
  344. ldo3 {
  345. regulator-name = "vdd_ldo3,avdd_usb*";
  346. regulator-min-microvolt = <3300000>;
  347. regulator-max-microvolt = <3300000>;
  348. regulator-always-on;
  349. };
  350. ldo4 {
  351. regulator-name = "vdd_ldo4,avdd_osc,vddio_sys";
  352. regulator-min-microvolt = <1800000>;
  353. regulator-max-microvolt = <1800000>;
  354. regulator-always-on;
  355. };
  356. ldo5 {
  357. regulator-name = "vdd_ldo5,vcore_mmc";
  358. regulator-min-microvolt = <2850000>;
  359. regulator-max-microvolt = <2850000>;
  360. regulator-always-on;
  361. };
  362. ldo6 {
  363. regulator-name = "vdd_ldo6,avdd_vdac";
  364. regulator-min-microvolt = <1800000>;
  365. regulator-max-microvolt = <1800000>;
  366. };
  367. hdmi_vdd_reg: ldo7 {
  368. regulator-name = "vdd_ldo7,avdd_hdmi";
  369. regulator-min-microvolt = <3300000>;
  370. regulator-max-microvolt = <3300000>;
  371. };
  372. hdmi_pll_reg: ldo8 {
  373. regulator-name = "vdd_ldo8,avdd_hdmi_pll";
  374. regulator-min-microvolt = <1800000>;
  375. regulator-max-microvolt = <1800000>;
  376. };
  377. ldo9 {
  378. regulator-name = "vdd_ldo9,avdd_2v85,vdd_ddr_rx";
  379. regulator-min-microvolt = <2850000>;
  380. regulator-max-microvolt = <2850000>;
  381. regulator-always-on;
  382. };
  383. ldo_rtc {
  384. regulator-name = "vdd_rtc_out,vdd_cell";
  385. regulator-min-microvolt = <3300000>;
  386. regulator-max-microvolt = <3300000>;
  387. regulator-always-on;
  388. };
  389. };
  390. };
  391. temperature-sensor@4c {
  392. compatible = "adi,adt7461";
  393. reg = <0x4c>;
  394. };
  395. };
  396. kbc@7000e200 {
  397. status = "okay";
  398. nvidia,debounce-delay-ms = <2>;
  399. nvidia,repeat-delay-ms = <160>;
  400. nvidia,kbc-row-pins = <0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15>;
  401. nvidia,kbc-col-pins = <16 17 18 19 20 21 22 23>;
  402. linux,keymap = <MATRIX_KEY(0x00, 0x02, KEY_W)
  403. MATRIX_KEY(0x00, 0x03, KEY_S)
  404. MATRIX_KEY(0x00, 0x04, KEY_A)
  405. MATRIX_KEY(0x00, 0x05, KEY_Z)
  406. MATRIX_KEY(0x00, 0x07, KEY_FN)
  407. MATRIX_KEY(0x01, 0x07, KEY_MENU)
  408. MATRIX_KEY(0x02, 0x06, KEY_LEFTALT)
  409. MATRIX_KEY(0x02, 0x07, KEY_RIGHTALT)
  410. MATRIX_KEY(0x03, 0x00, KEY_5)
  411. MATRIX_KEY(0x03, 0x01, KEY_4)
  412. MATRIX_KEY(0x03, 0x02, KEY_R)
  413. MATRIX_KEY(0x03, 0x03, KEY_E)
  414. MATRIX_KEY(0x03, 0x04, KEY_F)
  415. MATRIX_KEY(0x03, 0x05, KEY_D)
  416. MATRIX_KEY(0x03, 0x06, KEY_X)
  417. MATRIX_KEY(0x04, 0x00, KEY_7)
  418. MATRIX_KEY(0x04, 0x01, KEY_6)
  419. MATRIX_KEY(0x04, 0x02, KEY_T)
  420. MATRIX_KEY(0x04, 0x03, KEY_H)
  421. MATRIX_KEY(0x04, 0x04, KEY_G)
  422. MATRIX_KEY(0x04, 0x05, KEY_V)
  423. MATRIX_KEY(0x04, 0x06, KEY_C)
  424. MATRIX_KEY(0x04, 0x07, KEY_SPACE)
  425. MATRIX_KEY(0x05, 0x00, KEY_9)
  426. MATRIX_KEY(0x05, 0x01, KEY_8)
  427. MATRIX_KEY(0x05, 0x02, KEY_U)
  428. MATRIX_KEY(0x05, 0x03, KEY_Y)
  429. MATRIX_KEY(0x05, 0x04, KEY_J)
  430. MATRIX_KEY(0x05, 0x05, KEY_N)
  431. MATRIX_KEY(0x05, 0x06, KEY_B)
  432. MATRIX_KEY(0x05, 0x07, KEY_BACKSLASH)
  433. MATRIX_KEY(0x06, 0x00, KEY_MINUS)
  434. MATRIX_KEY(0x06, 0x01, KEY_0)
  435. MATRIX_KEY(0x06, 0x02, KEY_O)
  436. MATRIX_KEY(0x06, 0x03, KEY_I)
  437. MATRIX_KEY(0x06, 0x04, KEY_L)
  438. MATRIX_KEY(0x06, 0x05, KEY_K)
  439. MATRIX_KEY(0x06, 0x06, KEY_COMMA)
  440. MATRIX_KEY(0x06, 0x07, KEY_M)
  441. MATRIX_KEY(0x07, 0x01, KEY_EQUAL)
  442. MATRIX_KEY(0x07, 0x02, KEY_RIGHTBRACE)
  443. MATRIX_KEY(0x07, 0x03, KEY_ENTER)
  444. MATRIX_KEY(0x07, 0x07, KEY_MENU)
  445. MATRIX_KEY(0x08, 0x04, KEY_LEFTSHIFT)
  446. MATRIX_KEY(0x08, 0x05, KEY_RIGHTSHIFT)
  447. MATRIX_KEY(0x09, 0x05, KEY_LEFTCTRL)
  448. MATRIX_KEY(0x09, 0x07, KEY_RIGHTCTRL)
  449. MATRIX_KEY(0x0B, 0x00, KEY_LEFTBRACE)
  450. MATRIX_KEY(0x0B, 0x01, KEY_P)
  451. MATRIX_KEY(0x0B, 0x02, KEY_APOSTROPHE)
  452. MATRIX_KEY(0x0B, 0x03, KEY_SEMICOLON)
  453. MATRIX_KEY(0x0B, 0x04, KEY_SLASH)
  454. MATRIX_KEY(0x0B, 0x05, KEY_DOT)
  455. MATRIX_KEY(0x0C, 0x00, KEY_F10)
  456. MATRIX_KEY(0x0C, 0x01, KEY_F9)
  457. MATRIX_KEY(0x0C, 0x02, KEY_BACKSPACE)
  458. MATRIX_KEY(0x0C, 0x03, KEY_3)
  459. MATRIX_KEY(0x0C, 0x04, KEY_2)
  460. MATRIX_KEY(0x0C, 0x05, KEY_UP)
  461. MATRIX_KEY(0x0C, 0x06, KEY_PRINT)
  462. MATRIX_KEY(0x0C, 0x07, KEY_PAUSE)
  463. MATRIX_KEY(0x0D, 0x00, KEY_INSERT)
  464. MATRIX_KEY(0x0D, 0x01, KEY_DELETE)
  465. MATRIX_KEY(0x0D, 0x03, KEY_PAGEUP )
  466. MATRIX_KEY(0x0D, 0x04, KEY_PAGEDOWN)
  467. MATRIX_KEY(0x0D, 0x05, KEY_RIGHT)
  468. MATRIX_KEY(0x0D, 0x06, KEY_DOWN)
  469. MATRIX_KEY(0x0D, 0x07, KEY_LEFT)
  470. MATRIX_KEY(0x0E, 0x00, KEY_F11)
  471. MATRIX_KEY(0x0E, 0x01, KEY_F12)
  472. MATRIX_KEY(0x0E, 0x02, KEY_F8)
  473. MATRIX_KEY(0x0E, 0x03, KEY_Q)
  474. MATRIX_KEY(0x0E, 0x04, KEY_F4)
  475. MATRIX_KEY(0x0E, 0x05, KEY_F3)
  476. MATRIX_KEY(0x0E, 0x06, KEY_1)
  477. MATRIX_KEY(0x0E, 0x07, KEY_F7)
  478. MATRIX_KEY(0x0F, 0x00, KEY_ESC)
  479. MATRIX_KEY(0x0F, 0x01, KEY_GRAVE)
  480. MATRIX_KEY(0x0F, 0x02, KEY_F5)
  481. MATRIX_KEY(0x0F, 0x03, KEY_TAB)
  482. MATRIX_KEY(0x0F, 0x04, KEY_F1)
  483. MATRIX_KEY(0x0F, 0x05, KEY_F2)
  484. MATRIX_KEY(0x0F, 0x06, KEY_CAPSLOCK)
  485. MATRIX_KEY(0x0F, 0x07, KEY_F6)
  486. MATRIX_KEY(0x14, 0x00, KEY_KP7)
  487. MATRIX_KEY(0x15, 0x00, KEY_KP9)
  488. MATRIX_KEY(0x15, 0x01, KEY_KP8)
  489. MATRIX_KEY(0x15, 0x02, KEY_KP4)
  490. MATRIX_KEY(0x15, 0x04, KEY_KP1)
  491. MATRIX_KEY(0x16, 0x01, KEY_KPSLASH)
  492. MATRIX_KEY(0x16, 0x02, KEY_KP6)
  493. MATRIX_KEY(0x16, 0x03, KEY_KP5)
  494. MATRIX_KEY(0x16, 0x04, KEY_KP3)
  495. MATRIX_KEY(0x16, 0x05, KEY_KP2)
  496. MATRIX_KEY(0x16, 0x07, KEY_KP0)
  497. MATRIX_KEY(0x1B, 0x01, KEY_KPASTERISK)
  498. MATRIX_KEY(0x1B, 0x03, KEY_KPMINUS)
  499. MATRIX_KEY(0x1B, 0x04, KEY_KPPLUS)
  500. MATRIX_KEY(0x1B, 0x05, KEY_KPDOT)
  501. MATRIX_KEY(0x1C, 0x05, KEY_VOLUMEUP)
  502. MATRIX_KEY(0x1D, 0x03, KEY_HOME)
  503. MATRIX_KEY(0x1D, 0x04, KEY_END)
  504. MATRIX_KEY(0x1D, 0x05, KEY_BRIGHTNESSUP)
  505. MATRIX_KEY(0x1D, 0x06, KEY_VOLUMEDOWN)
  506. MATRIX_KEY(0x1D, 0x07, KEY_BRIGHTNESSDOWN)
  507. MATRIX_KEY(0x1E, 0x00, KEY_NUMLOCK)
  508. MATRIX_KEY(0x1E, 0x01, KEY_SCROLLLOCK)
  509. MATRIX_KEY(0x1E, 0x02, KEY_MUTE)
  510. MATRIX_KEY(0x1F, 0x04, KEY_QUESTION)>;
  511. };
  512. pmc@7000e400 {
  513. nvidia,invert-interrupt;
  514. nvidia,suspend-mode = <1>;
  515. nvidia,cpu-pwr-good-time = <5000>;
  516. nvidia,cpu-pwr-off-time = <5000>;
  517. nvidia,core-pwr-good-time = <3845 3845>;
  518. nvidia,core-pwr-off-time = <3875>;
  519. nvidia,sys-clock-req-active-high;
  520. };
  521. pcie-controller@80003000 {
  522. status = "okay";
  523. avdd-pex-supply = <&pci_vdd_reg>;
  524. vdd-pex-supply = <&pci_vdd_reg>;
  525. avdd-pex-pll-supply = <&pci_vdd_reg>;
  526. avdd-plle-supply = <&pci_vdd_reg>;
  527. vddio-pex-clk-supply = <&pci_clk_reg>;
  528. pci@1,0 {
  529. status = "okay";
  530. };
  531. pci@2,0 {
  532. status = "okay";
  533. };
  534. };
  535. usb@c5000000 {
  536. status = "okay";
  537. };
  538. usb-phy@c5000000 {
  539. status = "okay";
  540. };
  541. usb@c5004000 {
  542. status = "okay";
  543. nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 1)
  544. GPIO_ACTIVE_LOW>;
  545. };
  546. usb-phy@c5004000 {
  547. status = "okay";
  548. nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 1)
  549. GPIO_ACTIVE_LOW>;
  550. };
  551. usb@c5008000 {
  552. status = "okay";
  553. };
  554. usb-phy@c5008000 {
  555. status = "okay";
  556. };
  557. sdhci@c8000200 {
  558. status = "okay";
  559. cd-gpios = <&gpio TEGRA_GPIO(I, 5) GPIO_ACTIVE_LOW>;
  560. wp-gpios = <&gpio TEGRA_GPIO(H, 1) GPIO_ACTIVE_HIGH>;
  561. power-gpios = <&gpio TEGRA_GPIO(T, 3) GPIO_ACTIVE_HIGH>;
  562. bus-width = <4>;
  563. };
  564. sdhci@c8000600 {
  565. status = "okay";
  566. cd-gpios = <&gpio TEGRA_GPIO(H, 2) GPIO_ACTIVE_LOW>;
  567. wp-gpios = <&gpio TEGRA_GPIO(H, 3) GPIO_ACTIVE_HIGH>;
  568. power-gpios = <&gpio TEGRA_GPIO(I, 6) GPIO_ACTIVE_HIGH>;
  569. bus-width = <8>;
  570. };
  571. backlight: backlight {
  572. compatible = "pwm-backlight";
  573. enable-gpios = <&gpio TEGRA_GPIO(B, 5) GPIO_ACTIVE_HIGH>;
  574. power-supply = <&vdd_bl_reg>;
  575. pwms = <&pwm 0 5000000>;
  576. brightness-levels = <0 4 8 16 32 64 128 255>;
  577. default-brightness-level = <6>;
  578. };
  579. clocks {
  580. compatible = "simple-bus";
  581. #address-cells = <1>;
  582. #size-cells = <0>;
  583. clk32k_in: clock@0 {
  584. compatible = "fixed-clock";
  585. reg=<0>;
  586. #clock-cells = <0>;
  587. clock-frequency = <32768>;
  588. };
  589. };
  590. gpio-keys {
  591. compatible = "gpio-keys";
  592. power {
  593. label = "Power";
  594. gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_LOW>;
  595. linux,code = <KEY_POWER>;
  596. gpio-key,wakeup;
  597. };
  598. };
  599. panel: panel {
  600. compatible = "auo,b101aw03", "simple-panel";
  601. power-supply = <&vdd_pnl_reg>;
  602. enable-gpios = <&gpio TEGRA_GPIO(B, 2) GPIO_ACTIVE_HIGH>;
  603. backlight = <&backlight>;
  604. };
  605. regulators {
  606. compatible = "simple-bus";
  607. #address-cells = <1>;
  608. #size-cells = <0>;
  609. vdd_5v0_reg: regulator@0 {
  610. compatible = "regulator-fixed";
  611. reg = <0>;
  612. regulator-name = "vdd_5v0";
  613. regulator-min-microvolt = <5000000>;
  614. regulator-max-microvolt = <5000000>;
  615. regulator-always-on;
  616. };
  617. regulator@1 {
  618. compatible = "regulator-fixed";
  619. reg = <1>;
  620. regulator-name = "vdd_1v5";
  621. regulator-min-microvolt = <1500000>;
  622. regulator-max-microvolt = <1500000>;
  623. gpio = <&pmic 0 GPIO_ACTIVE_HIGH>;
  624. };
  625. regulator@2 {
  626. compatible = "regulator-fixed";
  627. reg = <2>;
  628. regulator-name = "vdd_1v2";
  629. regulator-min-microvolt = <1200000>;
  630. regulator-max-microvolt = <1200000>;
  631. gpio = <&pmic 1 GPIO_ACTIVE_HIGH>;
  632. enable-active-high;
  633. };
  634. pci_vdd_reg: regulator@3 {
  635. compatible = "regulator-fixed";
  636. reg = <3>;
  637. regulator-name = "vdd_1v05";
  638. regulator-min-microvolt = <1050000>;
  639. regulator-max-microvolt = <1050000>;
  640. gpio = <&pmic 2 GPIO_ACTIVE_HIGH>;
  641. enable-active-high;
  642. };
  643. vdd_pnl_reg: regulator@4 {
  644. compatible = "regulator-fixed";
  645. reg = <4>;
  646. regulator-name = "vdd_pnl";
  647. regulator-min-microvolt = <2800000>;
  648. regulator-max-microvolt = <2800000>;
  649. gpio = <&gpio TEGRA_GPIO(C, 6) GPIO_ACTIVE_HIGH>;
  650. enable-active-high;
  651. };
  652. vdd_bl_reg: regulator@5 {
  653. compatible = "regulator-fixed";
  654. reg = <5>;
  655. regulator-name = "vdd_bl";
  656. regulator-min-microvolt = <2800000>;
  657. regulator-max-microvolt = <2800000>;
  658. gpio = <&gpio TEGRA_GPIO(W, 0) GPIO_ACTIVE_HIGH>;
  659. enable-active-high;
  660. };
  661. vdd_5v0_hdmi: regulator@6 {
  662. compatible = "regulator-fixed";
  663. reg = <6>;
  664. regulator-name = "VDDIO_HDMI";
  665. regulator-min-microvolt = <5000000>;
  666. regulator-max-microvolt = <5000000>;
  667. gpio = <&gpio TEGRA_GPIO(T, 2) GPIO_ACTIVE_HIGH>;
  668. enable-active-high;
  669. vin-supply = <&vdd_5v0_reg>;
  670. };
  671. };
  672. sound {
  673. compatible = "nvidia,tegra-audio-wm8903-harmony",
  674. "nvidia,tegra-audio-wm8903";
  675. nvidia,model = "NVIDIA Tegra Harmony";
  676. nvidia,audio-routing =
  677. "Headphone Jack", "HPOUTR",
  678. "Headphone Jack", "HPOUTL",
  679. "Int Spk", "ROP",
  680. "Int Spk", "RON",
  681. "Int Spk", "LOP",
  682. "Int Spk", "LON",
  683. "Mic Jack", "MICBIAS",
  684. "IN1L", "Mic Jack";
  685. nvidia,i2s-controller = <&tegra_i2s1>;
  686. nvidia,audio-codec = <&wm8903>;
  687. nvidia,spkr-en-gpios = <&wm8903 2 GPIO_ACTIVE_HIGH>;
  688. nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(W, 2)
  689. GPIO_ACTIVE_HIGH>;
  690. nvidia,int-mic-en-gpios = <&gpio TEGRA_GPIO(X, 0)
  691. GPIO_ACTIVE_HIGH>;
  692. nvidia,ext-mic-en-gpios = <&gpio TEGRA_GPIO(X, 1)
  693. GPIO_ACTIVE_HIGH>;
  694. clocks = <&tegra_car TEGRA20_CLK_PLL_A>,
  695. <&tegra_car TEGRA20_CLK_PLL_A_OUT0>,
  696. <&tegra_car TEGRA20_CLK_CDEV1>;
  697. clock-names = "pll_a", "pll_a_out0", "mclk";
  698. };
  699. };