tegra20-paz00.dts 13 KB

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  1. /dts-v1/;
  2. #include <dt-bindings/input/input.h>
  3. #include "tegra20.dtsi"
  4. / {
  5. model = "Toshiba AC100 / Dynabook AZ";
  6. compatible = "compal,paz00", "nvidia,tegra20";
  7. aliases {
  8. rtc0 = "/i2c@7000d000/tps6586x@34";
  9. rtc1 = "/rtc@7000e000";
  10. serial0 = &uarta;
  11. serial1 = &uartc;
  12. };
  13. memory {
  14. reg = <0x00000000 0x20000000>;
  15. };
  16. host1x@50000000 {
  17. dc@54200000 {
  18. rgb {
  19. status = "okay";
  20. nvidia,panel = <&panel>;
  21. };
  22. };
  23. hdmi@54280000 {
  24. status = "okay";
  25. vdd-supply = <&hdmi_vdd_reg>;
  26. pll-supply = <&hdmi_pll_reg>;
  27. nvidia,ddc-i2c-bus = <&hdmi_ddc>;
  28. nvidia,hpd-gpio = <&gpio TEGRA_GPIO(N, 7)
  29. GPIO_ACTIVE_HIGH>;
  30. };
  31. };
  32. pinmux@70000014 {
  33. pinctrl-names = "default";
  34. pinctrl-0 = <&state_default>;
  35. state_default: pinmux {
  36. ata {
  37. nvidia,pins = "ata", "atc", "atd", "ate",
  38. "dap2", "gmb", "gmc", "gmd", "spia",
  39. "spib", "spic", "spid", "spie";
  40. nvidia,function = "gmi";
  41. };
  42. atb {
  43. nvidia,pins = "atb", "gma", "gme";
  44. nvidia,function = "sdio4";
  45. };
  46. cdev1 {
  47. nvidia,pins = "cdev1";
  48. nvidia,function = "plla_out";
  49. };
  50. cdev2 {
  51. nvidia,pins = "cdev2";
  52. nvidia,function = "pllp_out4";
  53. };
  54. crtp {
  55. nvidia,pins = "crtp";
  56. nvidia,function = "crt";
  57. };
  58. csus {
  59. nvidia,pins = "csus";
  60. nvidia,function = "pllc_out1";
  61. };
  62. dap1 {
  63. nvidia,pins = "dap1";
  64. nvidia,function = "dap1";
  65. };
  66. dap3 {
  67. nvidia,pins = "dap3";
  68. nvidia,function = "dap3";
  69. };
  70. dap4 {
  71. nvidia,pins = "dap4";
  72. nvidia,function = "dap4";
  73. };
  74. ddc {
  75. nvidia,pins = "ddc";
  76. nvidia,function = "i2c2";
  77. };
  78. dta {
  79. nvidia,pins = "dta", "dtb", "dtc", "dtd", "dte";
  80. nvidia,function = "rsvd1";
  81. };
  82. dtf {
  83. nvidia,pins = "dtf";
  84. nvidia,function = "i2c3";
  85. };
  86. gpu {
  87. nvidia,pins = "gpu", "sdb", "sdd";
  88. nvidia,function = "pwm";
  89. };
  90. gpu7 {
  91. nvidia,pins = "gpu7";
  92. nvidia,function = "rtck";
  93. };
  94. gpv {
  95. nvidia,pins = "gpv", "slxa", "slxk";
  96. nvidia,function = "pcie";
  97. };
  98. hdint {
  99. nvidia,pins = "hdint", "pta";
  100. nvidia,function = "hdmi";
  101. };
  102. i2cp {
  103. nvidia,pins = "i2cp";
  104. nvidia,function = "i2cp";
  105. };
  106. irrx {
  107. nvidia,pins = "irrx", "irtx";
  108. nvidia,function = "uarta";
  109. };
  110. kbca {
  111. nvidia,pins = "kbca", "kbcc", "kbce", "kbcf";
  112. nvidia,function = "kbc";
  113. };
  114. kbcb {
  115. nvidia,pins = "kbcb", "kbcd";
  116. nvidia,function = "sdio2";
  117. };
  118. lcsn {
  119. nvidia,pins = "lcsn", "ld0", "ld1", "ld2",
  120. "ld3", "ld4", "ld5", "ld6", "ld7",
  121. "ld8", "ld9", "ld10", "ld11", "ld12",
  122. "ld13", "ld14", "ld15", "ld16", "ld17",
  123. "ldc", "ldi", "lhp0", "lhp1", "lhp2",
  124. "lhs", "lm0", "lm1", "lpp", "lpw0",
  125. "lpw1", "lpw2", "lsc0", "lsc1", "lsck",
  126. "lsda", "lsdi", "lspi", "lvp0", "lvp1",
  127. "lvs";
  128. nvidia,function = "displaya";
  129. };
  130. owc {
  131. nvidia,pins = "owc";
  132. nvidia,function = "owr";
  133. };
  134. pmc {
  135. nvidia,pins = "pmc";
  136. nvidia,function = "pwr_on";
  137. };
  138. rm {
  139. nvidia,pins = "rm";
  140. nvidia,function = "i2c1";
  141. };
  142. sdc {
  143. nvidia,pins = "sdc";
  144. nvidia,function = "twc";
  145. };
  146. sdio1 {
  147. nvidia,pins = "sdio1";
  148. nvidia,function = "sdio1";
  149. };
  150. slxc {
  151. nvidia,pins = "slxc", "slxd";
  152. nvidia,function = "spi4";
  153. };
  154. spdi {
  155. nvidia,pins = "spdi", "spdo";
  156. nvidia,function = "rsvd2";
  157. };
  158. spif {
  159. nvidia,pins = "spif", "uac";
  160. nvidia,function = "rsvd4";
  161. };
  162. spig {
  163. nvidia,pins = "spig", "spih";
  164. nvidia,function = "spi2_alt";
  165. };
  166. uaa {
  167. nvidia,pins = "uaa", "uab", "uda";
  168. nvidia,function = "ulpi";
  169. };
  170. uad {
  171. nvidia,pins = "uad";
  172. nvidia,function = "spdif";
  173. };
  174. uca {
  175. nvidia,pins = "uca", "ucb";
  176. nvidia,function = "uartc";
  177. };
  178. conf_ata {
  179. nvidia,pins = "ata", "atb", "atc", "atd", "ate",
  180. "cdev1", "cdev2", "dap1", "dap2", "dtf",
  181. "gma", "gmb", "gmc", "gmd", "gme",
  182. "gpu", "gpu7", "gpv", "i2cp", "pta",
  183. "rm", "sdio1", "slxk", "spdo", "uac",
  184. "uda";
  185. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  186. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  187. };
  188. conf_ck32 {
  189. nvidia,pins = "ck32", "ddrc", "pmca", "pmcb",
  190. "pmcc", "pmcd", "pmce", "xm2c", "xm2d";
  191. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  192. };
  193. conf_crtp {
  194. nvidia,pins = "crtp", "dap3", "dap4", "dtb",
  195. "dtc", "dte", "slxa", "slxc", "slxd",
  196. "spdi";
  197. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  198. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  199. };
  200. conf_csus {
  201. nvidia,pins = "csus", "spia", "spib", "spid",
  202. "spif";
  203. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  204. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  205. };
  206. conf_ddc {
  207. nvidia,pins = "ddc", "irrx", "irtx", "kbca",
  208. "kbcb", "kbcc", "kbcd", "kbce", "kbcf",
  209. "spic", "spig", "uaa", "uab";
  210. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  211. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  212. };
  213. conf_dta {
  214. nvidia,pins = "dta", "dtd", "owc", "sdc", "sdd",
  215. "spie", "spih", "uad", "uca", "ucb";
  216. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  217. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  218. };
  219. conf_hdint {
  220. nvidia,pins = "hdint", "ld0", "ld1", "ld2",
  221. "ld3", "ld4", "ld5", "ld6", "ld7",
  222. "ld8", "ld9", "ld10", "ld11", "ld12",
  223. "ld13", "ld14", "ld15", "ld16", "ld17",
  224. "ldc", "ldi", "lhs", "lsc0", "lspi",
  225. "lvs", "pmc";
  226. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  227. };
  228. conf_lc {
  229. nvidia,pins = "lc", "ls";
  230. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  231. };
  232. conf_lcsn {
  233. nvidia,pins = "lcsn", "lhp0", "lhp1", "lhp2",
  234. "lm0", "lm1", "lpp", "lpw0", "lpw1",
  235. "lpw2", "lsc1", "lsck", "lsda", "lsdi",
  236. "lvp0", "lvp1", "sdb";
  237. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  238. };
  239. conf_ld17_0 {
  240. nvidia,pins = "ld17_0", "ld19_18", "ld21_20",
  241. "ld23_22";
  242. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  243. };
  244. };
  245. };
  246. i2s@70002800 {
  247. status = "okay";
  248. };
  249. serial@70006000 {
  250. status = "okay";
  251. };
  252. serial@70006200 {
  253. status = "okay";
  254. };
  255. pwm: pwm@7000a000 {
  256. status = "okay";
  257. };
  258. lvds_ddc: i2c@7000c000 {
  259. status = "okay";
  260. clock-frequency = <400000>;
  261. alc5632: alc5632@1e {
  262. compatible = "realtek,alc5632";
  263. reg = <0x1e>;
  264. gpio-controller;
  265. #gpio-cells = <2>;
  266. };
  267. };
  268. hdmi_ddc: i2c@7000c400 {
  269. status = "okay";
  270. clock-frequency = <100000>;
  271. };
  272. nvec@7000c500 {
  273. compatible = "nvidia,nvec";
  274. reg = <0x7000c500 0x100>;
  275. interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
  276. #address-cells = <1>;
  277. #size-cells = <0>;
  278. clock-frequency = <80000>;
  279. request-gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_HIGH>;
  280. slave-addr = <138>;
  281. clocks = <&tegra_car TEGRA20_CLK_I2C3>,
  282. <&tegra_car TEGRA20_CLK_PLL_P_OUT3>;
  283. clock-names = "div-clk", "fast-clk";
  284. resets = <&tegra_car 67>;
  285. reset-names = "i2c";
  286. };
  287. i2c@7000d000 {
  288. status = "okay";
  289. clock-frequency = <400000>;
  290. pmic: tps6586x@34 {
  291. compatible = "ti,tps6586x";
  292. reg = <0x34>;
  293. interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
  294. #gpio-cells = <2>;
  295. gpio-controller;
  296. sys-supply = <&p5valw_reg>;
  297. vin-sm0-supply = <&sys_reg>;
  298. vin-sm1-supply = <&sys_reg>;
  299. vin-sm2-supply = <&sys_reg>;
  300. vinldo01-supply = <&sm2_reg>;
  301. vinldo23-supply = <&sm2_reg>;
  302. vinldo4-supply = <&sm2_reg>;
  303. vinldo678-supply = <&sm2_reg>;
  304. vinldo9-supply = <&sm2_reg>;
  305. regulators {
  306. sys_reg: sys {
  307. regulator-name = "vdd_sys";
  308. regulator-always-on;
  309. };
  310. sm0 {
  311. regulator-name = "+1.2vs_sm0,vdd_core";
  312. regulator-min-microvolt = <1200000>;
  313. regulator-max-microvolt = <1200000>;
  314. regulator-always-on;
  315. };
  316. sm1 {
  317. regulator-name = "+1.0vs_sm1,vdd_cpu";
  318. regulator-min-microvolt = <1000000>;
  319. regulator-max-microvolt = <1000000>;
  320. regulator-always-on;
  321. };
  322. sm2_reg: sm2 {
  323. regulator-name = "+3.7vs_sm2,vin_ldo*";
  324. regulator-min-microvolt = <3700000>;
  325. regulator-max-microvolt = <3700000>;
  326. regulator-always-on;
  327. };
  328. /* LDO0 is not connected to anything */
  329. ldo1 {
  330. regulator-name = "+1.1vs_ldo1,avdd_pll*";
  331. regulator-min-microvolt = <1100000>;
  332. regulator-max-microvolt = <1100000>;
  333. regulator-always-on;
  334. };
  335. ldo2 {
  336. regulator-name = "+1.2vs_ldo2,vdd_rtc";
  337. regulator-min-microvolt = <1200000>;
  338. regulator-max-microvolt = <1200000>;
  339. };
  340. ldo3 {
  341. regulator-name = "+3.3vs_ldo3,avdd_usb*";
  342. regulator-min-microvolt = <3300000>;
  343. regulator-max-microvolt = <3300000>;
  344. regulator-always-on;
  345. };
  346. ldo4 {
  347. regulator-name = "+1.8vs_ldo4,avdd_osc,vddio_sys";
  348. regulator-min-microvolt = <1800000>;
  349. regulator-max-microvolt = <1800000>;
  350. regulator-always-on;
  351. };
  352. ldo5 {
  353. regulator-name = "+2.85vs_ldo5,vcore_mmc";
  354. regulator-min-microvolt = <2850000>;
  355. regulator-max-microvolt = <2850000>;
  356. regulator-always-on;
  357. };
  358. ldo6 {
  359. /*
  360. * Research indicates this should be
  361. * 1.8v; other boards that use this
  362. * rail for the same purpose need it
  363. * set to 1.8v. The schematic signal
  364. * name is incorrect; perhaps copied
  365. * from an incorrect NVIDIA reference.
  366. */
  367. regulator-name = "+2.85vs_ldo6,avdd_vdac";
  368. regulator-min-microvolt = <1800000>;
  369. regulator-max-microvolt = <1800000>;
  370. };
  371. hdmi_vdd_reg: ldo7 {
  372. regulator-name = "+3.3vs_ldo7,avdd_hdmi";
  373. regulator-min-microvolt = <3300000>;
  374. regulator-max-microvolt = <3300000>;
  375. };
  376. hdmi_pll_reg: ldo8 {
  377. regulator-name = "+1.8vs_ldo8,avdd_hdmi_pll";
  378. regulator-min-microvolt = <1800000>;
  379. regulator-max-microvolt = <1800000>;
  380. };
  381. ldo9 {
  382. regulator-name = "+2.85vs_ldo9,vdd_ddr_rx";
  383. regulator-min-microvolt = <2850000>;
  384. regulator-max-microvolt = <2850000>;
  385. regulator-always-on;
  386. };
  387. ldo_rtc {
  388. regulator-name = "+3.3vs_rtc";
  389. regulator-min-microvolt = <3300000>;
  390. regulator-max-microvolt = <3300000>;
  391. regulator-always-on;
  392. };
  393. };
  394. };
  395. adt7461@4c {
  396. compatible = "adi,adt7461";
  397. reg = <0x4c>;
  398. };
  399. };
  400. pmc@7000e400 {
  401. nvidia,invert-interrupt;
  402. nvidia,suspend-mode = <1>;
  403. nvidia,cpu-pwr-good-time = <2000>;
  404. nvidia,cpu-pwr-off-time = <0>;
  405. nvidia,core-pwr-good-time = <3845 3845>;
  406. nvidia,core-pwr-off-time = <0>;
  407. nvidia,sys-clock-req-active-high;
  408. };
  409. usb@c5000000 {
  410. status = "okay";
  411. };
  412. usb-phy@c5000000 {
  413. status = "okay";
  414. };
  415. usb@c5004000 {
  416. status = "okay";
  417. nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 0)
  418. GPIO_ACTIVE_LOW>;
  419. };
  420. usb-phy@c5004000 {
  421. status = "okay";
  422. nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 0)
  423. GPIO_ACTIVE_LOW>;
  424. };
  425. usb@c5008000 {
  426. status = "okay";
  427. };
  428. usb-phy@c5008000 {
  429. status = "okay";
  430. };
  431. sdhci@c8000000 {
  432. status = "okay";
  433. cd-gpios = <&gpio TEGRA_GPIO(V, 5) GPIO_ACTIVE_LOW>;
  434. wp-gpios = <&gpio TEGRA_GPIO(H, 1) GPIO_ACTIVE_HIGH>;
  435. power-gpios = <&gpio TEGRA_GPIO(V, 1) GPIO_ACTIVE_HIGH>;
  436. bus-width = <4>;
  437. };
  438. sdhci@c8000600 {
  439. status = "okay";
  440. bus-width = <8>;
  441. non-removable;
  442. };
  443. backlight: backlight {
  444. compatible = "pwm-backlight";
  445. enable-gpios = <&gpio TEGRA_GPIO(U, 4) GPIO_ACTIVE_HIGH>;
  446. pwms = <&pwm 0 5000000>;
  447. brightness-levels = <0 16 32 48 64 80 96 112 128 144 160 176 192 208 224 240 255>;
  448. default-brightness-level = <10>;
  449. backlight-boot-off;
  450. };
  451. clocks {
  452. compatible = "simple-bus";
  453. #address-cells = <1>;
  454. #size-cells = <0>;
  455. clk32k_in: clock@0 {
  456. compatible = "fixed-clock";
  457. reg=<0>;
  458. #clock-cells = <0>;
  459. clock-frequency = <32768>;
  460. };
  461. };
  462. gpio-keys {
  463. compatible = "gpio-keys";
  464. power {
  465. label = "Power";
  466. gpios = <&gpio TEGRA_GPIO(J, 7) GPIO_ACTIVE_LOW>;
  467. linux,code = <KEY_POWER>;
  468. gpio-key,wakeup;
  469. };
  470. };
  471. gpio-leds {
  472. compatible = "gpio-leds";
  473. wifi {
  474. label = "wifi-led";
  475. gpios = <&gpio TEGRA_GPIO(D, 0) GPIO_ACTIVE_HIGH>;
  476. linux,default-trigger = "rfkill0";
  477. };
  478. };
  479. panel: panel {
  480. compatible = "samsung,ltn101nt05", "simple-panel";
  481. ddc-i2c-bus = <&lvds_ddc>;
  482. power-supply = <&vdd_pnl_reg>;
  483. enable-gpios = <&gpio TEGRA_GPIO(M, 6) GPIO_ACTIVE_HIGH>;
  484. backlight = <&backlight>;
  485. };
  486. regulators {
  487. compatible = "simple-bus";
  488. #address-cells = <1>;
  489. #size-cells = <0>;
  490. p5valw_reg: regulator@0 {
  491. compatible = "regulator-fixed";
  492. reg = <0>;
  493. regulator-name = "+5valw";
  494. regulator-min-microvolt = <5000000>;
  495. regulator-max-microvolt = <5000000>;
  496. regulator-always-on;
  497. };
  498. vdd_pnl_reg: regulator@1 {
  499. compatible = "regulator-fixed";
  500. reg = <1>;
  501. regulator-name = "+3VS,vdd_pnl";
  502. regulator-min-microvolt = <3300000>;
  503. regulator-max-microvolt = <3300000>;
  504. gpio = <&gpio TEGRA_GPIO(A, 4) GPIO_ACTIVE_HIGH>;
  505. enable-active-high;
  506. };
  507. };
  508. sound {
  509. compatible = "nvidia,tegra-audio-alc5632-paz00",
  510. "nvidia,tegra-audio-alc5632";
  511. nvidia,model = "Compal PAZ00";
  512. nvidia,audio-routing =
  513. "Int Spk", "SPKOUT",
  514. "Int Spk", "SPKOUTN",
  515. "Headset Mic", "MICBIAS1",
  516. "MIC1", "Headset Mic",
  517. "Headset Stereophone", "HPR",
  518. "Headset Stereophone", "HPL",
  519. "DMICDAT", "Digital Mic";
  520. nvidia,audio-codec = <&alc5632>;
  521. nvidia,i2s-controller = <&tegra_i2s1>;
  522. nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(W, 2)
  523. GPIO_ACTIVE_HIGH>;
  524. clocks = <&tegra_car TEGRA20_CLK_PLL_A>,
  525. <&tegra_car TEGRA20_CLK_PLL_A_OUT0>,
  526. <&tegra_car TEGRA20_CLK_CDEV1>;
  527. clock-names = "pll_a", "pll_a_out0", "mclk";
  528. };
  529. };