tegra20-seaboard.dts 22 KB

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  1. /dts-v1/;
  2. #include <dt-bindings/input/input.h>
  3. #include "tegra20.dtsi"
  4. / {
  5. model = "NVIDIA Seaboard";
  6. compatible = "nvidia,seaboard", "nvidia,tegra20";
  7. aliases {
  8. rtc0 = "/i2c@7000d000/tps6586x@34";
  9. rtc1 = "/rtc@7000e000";
  10. serial0 = &uartd;
  11. };
  12. memory {
  13. reg = <0x00000000 0x40000000>;
  14. };
  15. host1x@50000000 {
  16. dc@54200000 {
  17. rgb {
  18. status = "okay";
  19. nvidia,panel = <&panel>;
  20. };
  21. };
  22. hdmi@54280000 {
  23. status = "okay";
  24. vdd-supply = <&hdmi_vdd_reg>;
  25. pll-supply = <&hdmi_pll_reg>;
  26. nvidia,ddc-i2c-bus = <&hdmi_ddc>;
  27. nvidia,hpd-gpio = <&gpio TEGRA_GPIO(N, 7)
  28. GPIO_ACTIVE_HIGH>;
  29. };
  30. };
  31. pinmux@70000014 {
  32. pinctrl-names = "default";
  33. pinctrl-0 = <&state_default>;
  34. state_default: pinmux {
  35. ata {
  36. nvidia,pins = "ata";
  37. nvidia,function = "ide";
  38. };
  39. atb {
  40. nvidia,pins = "atb", "gma", "gme";
  41. nvidia,function = "sdio4";
  42. };
  43. atc {
  44. nvidia,pins = "atc";
  45. nvidia,function = "nand";
  46. };
  47. atd {
  48. nvidia,pins = "atd", "ate", "gmb", "spia",
  49. "spib", "spic";
  50. nvidia,function = "gmi";
  51. };
  52. cdev1 {
  53. nvidia,pins = "cdev1";
  54. nvidia,function = "plla_out";
  55. };
  56. cdev2 {
  57. nvidia,pins = "cdev2";
  58. nvidia,function = "pllp_out4";
  59. };
  60. crtp {
  61. nvidia,pins = "crtp", "lm1";
  62. nvidia,function = "crt";
  63. };
  64. csus {
  65. nvidia,pins = "csus";
  66. nvidia,function = "vi_sensor_clk";
  67. };
  68. dap1 {
  69. nvidia,pins = "dap1";
  70. nvidia,function = "dap1";
  71. };
  72. dap2 {
  73. nvidia,pins = "dap2";
  74. nvidia,function = "dap2";
  75. };
  76. dap3 {
  77. nvidia,pins = "dap3";
  78. nvidia,function = "dap3";
  79. };
  80. dap4 {
  81. nvidia,pins = "dap4";
  82. nvidia,function = "dap4";
  83. };
  84. dta {
  85. nvidia,pins = "dta", "dtb", "dtc", "dtd", "dte";
  86. nvidia,function = "vi";
  87. };
  88. dtf {
  89. nvidia,pins = "dtf";
  90. nvidia,function = "i2c3";
  91. };
  92. gmc {
  93. nvidia,pins = "gmc";
  94. nvidia,function = "uartd";
  95. };
  96. gmd {
  97. nvidia,pins = "gmd";
  98. nvidia,function = "sflash";
  99. };
  100. gpu {
  101. nvidia,pins = "gpu";
  102. nvidia,function = "pwm";
  103. };
  104. gpu7 {
  105. nvidia,pins = "gpu7";
  106. nvidia,function = "rtck";
  107. };
  108. gpv {
  109. nvidia,pins = "gpv", "slxa", "slxk";
  110. nvidia,function = "pcie";
  111. };
  112. hdint {
  113. nvidia,pins = "hdint", "lpw0", "lpw2", "lsc1",
  114. "lsck", "lsda";
  115. nvidia,function = "hdmi";
  116. };
  117. i2cp {
  118. nvidia,pins = "i2cp";
  119. nvidia,function = "i2cp";
  120. };
  121. irrx {
  122. nvidia,pins = "irrx", "irtx";
  123. nvidia,function = "uartb";
  124. };
  125. kbca {
  126. nvidia,pins = "kbca", "kbcb", "kbcc", "kbcd",
  127. "kbce", "kbcf";
  128. nvidia,function = "kbc";
  129. };
  130. lcsn {
  131. nvidia,pins = "lcsn", "ldc", "lm0", "lpw1",
  132. "lsdi", "lvp0";
  133. nvidia,function = "rsvd4";
  134. };
  135. ld0 {
  136. nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4",
  137. "ld5", "ld6", "ld7", "ld8", "ld9",
  138. "ld10", "ld11", "ld12", "ld13", "ld14",
  139. "ld15", "ld16", "ld17", "ldi", "lhp0",
  140. "lhp1", "lhp2", "lhs", "lpp", "lsc0",
  141. "lspi", "lvp1", "lvs";
  142. nvidia,function = "displaya";
  143. };
  144. owc {
  145. nvidia,pins = "owc", "spdi", "spdo", "uac";
  146. nvidia,function = "rsvd2";
  147. };
  148. pmc {
  149. nvidia,pins = "pmc";
  150. nvidia,function = "pwr_on";
  151. };
  152. rm {
  153. nvidia,pins = "rm";
  154. nvidia,function = "i2c1";
  155. };
  156. sdb {
  157. nvidia,pins = "sdb", "sdc", "sdd";
  158. nvidia,function = "sdio3";
  159. };
  160. sdio1 {
  161. nvidia,pins = "sdio1";
  162. nvidia,function = "sdio1";
  163. };
  164. slxc {
  165. nvidia,pins = "slxc", "slxd";
  166. nvidia,function = "spdif";
  167. };
  168. spid {
  169. nvidia,pins = "spid", "spie", "spif";
  170. nvidia,function = "spi1";
  171. };
  172. spig {
  173. nvidia,pins = "spig", "spih";
  174. nvidia,function = "spi2_alt";
  175. };
  176. uaa {
  177. nvidia,pins = "uaa", "uab", "uda";
  178. nvidia,function = "ulpi";
  179. };
  180. uad {
  181. nvidia,pins = "uad";
  182. nvidia,function = "irda";
  183. };
  184. uca {
  185. nvidia,pins = "uca", "ucb";
  186. nvidia,function = "uartc";
  187. };
  188. conf_ata {
  189. nvidia,pins = "ata", "atb", "atc", "atd",
  190. "cdev1", "cdev2", "dap1", "dap2",
  191. "dap4", "ddc", "dtf", "gma", "gmc", "gmd",
  192. "gme", "gpu", "gpu7", "i2cp", "irrx",
  193. "irtx", "pta", "rm", "sdc", "sdd",
  194. "slxd", "slxk", "spdi", "spdo", "uac",
  195. "uad", "uca", "ucb", "uda";
  196. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  197. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  198. };
  199. conf_ate {
  200. nvidia,pins = "ate", "csus", "dap3",
  201. "gpv", "owc", "slxc", "spib", "spid",
  202. "spie";
  203. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  204. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  205. };
  206. conf_ck32 {
  207. nvidia,pins = "ck32", "ddrc", "pmca", "pmcb",
  208. "pmcc", "pmcd", "pmce", "xm2c", "xm2d";
  209. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  210. };
  211. conf_crtp {
  212. nvidia,pins = "crtp", "gmb", "slxa", "spia",
  213. "spig", "spih";
  214. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  215. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  216. };
  217. conf_dta {
  218. nvidia,pins = "dta", "dtb", "dtc", "dtd";
  219. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  220. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  221. };
  222. conf_dte {
  223. nvidia,pins = "dte", "spif";
  224. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  225. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  226. };
  227. conf_hdint {
  228. nvidia,pins = "hdint", "lcsn", "ldc", "lm1",
  229. "lpw1", "lsc1", "lsck", "lsda", "lsdi",
  230. "lvp0";
  231. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  232. };
  233. conf_kbca {
  234. nvidia,pins = "kbca", "kbcb", "kbcc", "kbcd",
  235. "kbce", "kbcf", "sdio1", "spic", "uaa",
  236. "uab";
  237. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  238. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  239. };
  240. conf_lc {
  241. nvidia,pins = "lc", "ls";
  242. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  243. };
  244. conf_ld0 {
  245. nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4",
  246. "ld5", "ld6", "ld7", "ld8", "ld9",
  247. "ld10", "ld11", "ld12", "ld13", "ld14",
  248. "ld15", "ld16", "ld17", "ldi", "lhp0",
  249. "lhp1", "lhp2", "lhs", "lm0", "lpp",
  250. "lpw0", "lpw2", "lsc0", "lspi", "lvp1",
  251. "lvs", "pmc", "sdb";
  252. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  253. };
  254. conf_ld17_0 {
  255. nvidia,pins = "ld17_0", "ld19_18", "ld21_20",
  256. "ld23_22";
  257. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  258. };
  259. drive_sdio1 {
  260. nvidia,pins = "drive_sdio1";
  261. nvidia,high-speed-mode = <TEGRA_PIN_DISABLE>;
  262. nvidia,schmitt = <TEGRA_PIN_DISABLE>;
  263. nvidia,low-power-mode = <TEGRA_PIN_LP_DRIVE_DIV_1>;
  264. nvidia,pull-down-strength = <31>;
  265. nvidia,pull-up-strength = <31>;
  266. nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_SLOWEST>;
  267. nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_SLOWEST>;
  268. };
  269. };
  270. state_i2cmux_ddc: pinmux_i2cmux_ddc {
  271. ddc {
  272. nvidia,pins = "ddc";
  273. nvidia,function = "i2c2";
  274. };
  275. pta {
  276. nvidia,pins = "pta";
  277. nvidia,function = "rsvd4";
  278. };
  279. };
  280. state_i2cmux_pta: pinmux_i2cmux_pta {
  281. ddc {
  282. nvidia,pins = "ddc";
  283. nvidia,function = "rsvd4";
  284. };
  285. pta {
  286. nvidia,pins = "pta";
  287. nvidia,function = "i2c2";
  288. };
  289. };
  290. state_i2cmux_idle: pinmux_i2cmux_idle {
  291. ddc {
  292. nvidia,pins = "ddc";
  293. nvidia,function = "rsvd4";
  294. };
  295. pta {
  296. nvidia,pins = "pta";
  297. nvidia,function = "rsvd4";
  298. };
  299. };
  300. };
  301. i2s@70002800 {
  302. status = "okay";
  303. };
  304. serial@70006300 {
  305. status = "okay";
  306. };
  307. pwm: pwm@7000a000 {
  308. status = "okay";
  309. };
  310. i2c@7000c000 {
  311. status = "okay";
  312. clock-frequency = <400000>;
  313. wm8903: wm8903@1a {
  314. compatible = "wlf,wm8903";
  315. reg = <0x1a>;
  316. interrupt-parent = <&gpio>;
  317. interrupts = <TEGRA_GPIO(X, 3) IRQ_TYPE_LEVEL_HIGH>;
  318. gpio-controller;
  319. #gpio-cells = <2>;
  320. micdet-cfg = <0>;
  321. micdet-delay = <100>;
  322. gpio-cfg = <0xffffffff 0xffffffff 0 0xffffffff 0xffffffff>;
  323. };
  324. /* ALS and proximity sensor */
  325. isl29018@44 {
  326. compatible = "isil,isl29018";
  327. reg = <0x44>;
  328. interrupt-parent = <&gpio>;
  329. interrupts = <TEGRA_GPIO(Z, 2) IRQ_TYPE_LEVEL_HIGH>;
  330. };
  331. gyrometer@68 {
  332. compatible = "invn,mpu3050";
  333. reg = <0x68>;
  334. interrupt-parent = <&gpio>;
  335. interrupts = <TEGRA_GPIO(Z, 4) IRQ_TYPE_LEVEL_HIGH>;
  336. };
  337. };
  338. i2c@7000c400 {
  339. status = "okay";
  340. clock-frequency = <100000>;
  341. };
  342. i2cmux {
  343. compatible = "i2c-mux-pinctrl";
  344. #address-cells = <1>;
  345. #size-cells = <0>;
  346. i2c-parent = <&{/i2c@7000c400}>;
  347. pinctrl-names = "ddc", "pta", "idle";
  348. pinctrl-0 = <&state_i2cmux_ddc>;
  349. pinctrl-1 = <&state_i2cmux_pta>;
  350. pinctrl-2 = <&state_i2cmux_idle>;
  351. hdmi_ddc: i2c@0 {
  352. reg = <0>;
  353. #address-cells = <1>;
  354. #size-cells = <0>;
  355. };
  356. lvds_ddc: i2c@1 {
  357. reg = <1>;
  358. #address-cells = <1>;
  359. #size-cells = <0>;
  360. smart-battery@b {
  361. compatible = "ti,bq20z75", "smart-battery-1.1";
  362. reg = <0xb>;
  363. ti,i2c-retry-count = <2>;
  364. ti,poll-retry-count = <10>;
  365. };
  366. };
  367. };
  368. i2c@7000c500 {
  369. status = "okay";
  370. clock-frequency = <400000>;
  371. };
  372. i2c@7000d000 {
  373. status = "okay";
  374. clock-frequency = <400000>;
  375. magnetometer@c {
  376. compatible = "ak,ak8975";
  377. reg = <0xc>;
  378. interrupt-parent = <&gpio>;
  379. interrupts = <TEGRA_GPIO(N, 5) IRQ_TYPE_LEVEL_HIGH>;
  380. };
  381. pmic: tps6586x@34 {
  382. compatible = "ti,tps6586x";
  383. reg = <0x34>;
  384. interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
  385. ti,system-power-controller;
  386. #gpio-cells = <2>;
  387. gpio-controller;
  388. sys-supply = <&vdd_5v0_reg>;
  389. vin-sm0-supply = <&sys_reg>;
  390. vin-sm1-supply = <&sys_reg>;
  391. vin-sm2-supply = <&sys_reg>;
  392. vinldo01-supply = <&sm2_reg>;
  393. vinldo23-supply = <&sm2_reg>;
  394. vinldo4-supply = <&sm2_reg>;
  395. vinldo678-supply = <&sm2_reg>;
  396. vinldo9-supply = <&sm2_reg>;
  397. regulators {
  398. sys_reg: sys {
  399. regulator-name = "vdd_sys";
  400. regulator-always-on;
  401. };
  402. sm0 {
  403. regulator-name = "vdd_sm0,vdd_core";
  404. regulator-min-microvolt = <1300000>;
  405. regulator-max-microvolt = <1300000>;
  406. regulator-always-on;
  407. };
  408. sm1 {
  409. regulator-name = "vdd_sm1,vdd_cpu";
  410. regulator-min-microvolt = <1125000>;
  411. regulator-max-microvolt = <1125000>;
  412. regulator-always-on;
  413. };
  414. sm2_reg: sm2 {
  415. regulator-name = "vdd_sm2,vin_ldo*";
  416. regulator-min-microvolt = <3700000>;
  417. regulator-max-microvolt = <3700000>;
  418. regulator-always-on;
  419. };
  420. /* LDO0 is not connected to anything */
  421. ldo1 {
  422. regulator-name = "vdd_ldo1,avdd_pll*";
  423. regulator-min-microvolt = <1100000>;
  424. regulator-max-microvolt = <1100000>;
  425. regulator-always-on;
  426. };
  427. ldo2 {
  428. regulator-name = "vdd_ldo2,vdd_rtc";
  429. regulator-min-microvolt = <1200000>;
  430. regulator-max-microvolt = <1200000>;
  431. };
  432. ldo3 {
  433. regulator-name = "vdd_ldo3,avdd_usb*";
  434. regulator-min-microvolt = <3300000>;
  435. regulator-max-microvolt = <3300000>;
  436. regulator-always-on;
  437. };
  438. ldo4 {
  439. regulator-name = "vdd_ldo4,avdd_osc,vddio_sys";
  440. regulator-min-microvolt = <1800000>;
  441. regulator-max-microvolt = <1800000>;
  442. regulator-always-on;
  443. };
  444. ldo5 {
  445. regulator-name = "vdd_ldo5,vcore_mmc";
  446. regulator-min-microvolt = <2850000>;
  447. regulator-max-microvolt = <2850000>;
  448. regulator-always-on;
  449. };
  450. ldo6 {
  451. regulator-name = "vdd_ldo6,avdd_vdac,vddio_vi,vddio_cam";
  452. regulator-min-microvolt = <1800000>;
  453. regulator-max-microvolt = <1800000>;
  454. };
  455. hdmi_vdd_reg: ldo7 {
  456. regulator-name = "vdd_ldo7,avdd_hdmi,vdd_fuse";
  457. regulator-min-microvolt = <3300000>;
  458. regulator-max-microvolt = <3300000>;
  459. };
  460. hdmi_pll_reg: ldo8 {
  461. regulator-name = "vdd_ldo8,avdd_hdmi_pll";
  462. regulator-min-microvolt = <1800000>;
  463. regulator-max-microvolt = <1800000>;
  464. };
  465. ldo9 {
  466. regulator-name = "vdd_ldo9,avdd_2v85,vdd_ddr_rx";
  467. regulator-min-microvolt = <2850000>;
  468. regulator-max-microvolt = <2850000>;
  469. regulator-always-on;
  470. };
  471. ldo_rtc {
  472. regulator-name = "vdd_rtc_out,vdd_cell";
  473. regulator-min-microvolt = <3300000>;
  474. regulator-max-microvolt = <3300000>;
  475. regulator-always-on;
  476. };
  477. };
  478. };
  479. temperature-sensor@4c {
  480. compatible = "onnn,nct1008";
  481. reg = <0x4c>;
  482. };
  483. };
  484. kbc@7000e200 {
  485. status = "okay";
  486. nvidia,debounce-delay-ms = <32>;
  487. nvidia,repeat-delay-ms = <160>;
  488. nvidia,ghost-filter;
  489. nvidia,kbc-row-pins = <0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15>;
  490. nvidia,kbc-col-pins = <16 17 18 19 20 21 22 23>;
  491. linux,keymap = <MATRIX_KEY(0x00, 0x02, KEY_W)
  492. MATRIX_KEY(0x00, 0x03, KEY_S)
  493. MATRIX_KEY(0x00, 0x04, KEY_A)
  494. MATRIX_KEY(0x00, 0x05, KEY_Z)
  495. MATRIX_KEY(0x00, 0x07, KEY_FN)
  496. MATRIX_KEY(0x01, 0x07, KEY_LEFTMETA)
  497. MATRIX_KEY(0x02, 0x06, KEY_RIGHTALT)
  498. MATRIX_KEY(0x02, 0x07, KEY_LEFTALT)
  499. MATRIX_KEY(0x03, 0x00, KEY_5)
  500. MATRIX_KEY(0x03, 0x01, KEY_4)
  501. MATRIX_KEY(0x03, 0x02, KEY_R)
  502. MATRIX_KEY(0x03, 0x03, KEY_E)
  503. MATRIX_KEY(0x03, 0x04, KEY_F)
  504. MATRIX_KEY(0x03, 0x05, KEY_D)
  505. MATRIX_KEY(0x03, 0x06, KEY_X)
  506. MATRIX_KEY(0x04, 0x00, KEY_7)
  507. MATRIX_KEY(0x04, 0x01, KEY_6)
  508. MATRIX_KEY(0x04, 0x02, KEY_T)
  509. MATRIX_KEY(0x04, 0x03, KEY_H)
  510. MATRIX_KEY(0x04, 0x04, KEY_G)
  511. MATRIX_KEY(0x04, 0x05, KEY_V)
  512. MATRIX_KEY(0x04, 0x06, KEY_C)
  513. MATRIX_KEY(0x04, 0x07, KEY_SPACE)
  514. MATRIX_KEY(0x05, 0x00, KEY_9)
  515. MATRIX_KEY(0x05, 0x01, KEY_8)
  516. MATRIX_KEY(0x05, 0x02, KEY_U)
  517. MATRIX_KEY(0x05, 0x03, KEY_Y)
  518. MATRIX_KEY(0x05, 0x04, KEY_J)
  519. MATRIX_KEY(0x05, 0x05, KEY_N)
  520. MATRIX_KEY(0x05, 0x06, KEY_B)
  521. MATRIX_KEY(0x05, 0x07, KEY_BACKSLASH)
  522. MATRIX_KEY(0x06, 0x00, KEY_MINUS)
  523. MATRIX_KEY(0x06, 0x01, KEY_0)
  524. MATRIX_KEY(0x06, 0x02, KEY_O)
  525. MATRIX_KEY(0x06, 0x03, KEY_I)
  526. MATRIX_KEY(0x06, 0x04, KEY_L)
  527. MATRIX_KEY(0x06, 0x05, KEY_K)
  528. MATRIX_KEY(0x06, 0x06, KEY_COMMA)
  529. MATRIX_KEY(0x06, 0x07, KEY_M)
  530. MATRIX_KEY(0x07, 0x01, KEY_EQUAL)
  531. MATRIX_KEY(0x07, 0x02, KEY_RIGHTBRACE)
  532. MATRIX_KEY(0x07, 0x03, KEY_ENTER)
  533. MATRIX_KEY(0x07, 0x07, KEY_MENU)
  534. MATRIX_KEY(0x08, 0x04, KEY_RIGHTSHIFT)
  535. MATRIX_KEY(0x08, 0x05, KEY_LEFTSHIFT)
  536. MATRIX_KEY(0x09, 0x05, KEY_RIGHTCTRL)
  537. MATRIX_KEY(0x09, 0x07, KEY_LEFTCTRL)
  538. MATRIX_KEY(0x0B, 0x00, KEY_LEFTBRACE)
  539. MATRIX_KEY(0x0B, 0x01, KEY_P)
  540. MATRIX_KEY(0x0B, 0x02, KEY_APOSTROPHE)
  541. MATRIX_KEY(0x0B, 0x03, KEY_SEMICOLON)
  542. MATRIX_KEY(0x0B, 0x04, KEY_SLASH)
  543. MATRIX_KEY(0x0B, 0x05, KEY_DOT)
  544. MATRIX_KEY(0x0C, 0x00, KEY_F10)
  545. MATRIX_KEY(0x0C, 0x01, KEY_F9)
  546. MATRIX_KEY(0x0C, 0x02, KEY_BACKSPACE)
  547. MATRIX_KEY(0x0C, 0x03, KEY_3)
  548. MATRIX_KEY(0x0C, 0x04, KEY_2)
  549. MATRIX_KEY(0x0C, 0x05, KEY_UP)
  550. MATRIX_KEY(0x0C, 0x06, KEY_PRINT)
  551. MATRIX_KEY(0x0C, 0x07, KEY_PAUSE)
  552. MATRIX_KEY(0x0D, 0x00, KEY_INSERT)
  553. MATRIX_KEY(0x0D, 0x01, KEY_DELETE)
  554. MATRIX_KEY(0x0D, 0x03, KEY_PAGEUP )
  555. MATRIX_KEY(0x0D, 0x04, KEY_PAGEDOWN)
  556. MATRIX_KEY(0x0D, 0x05, KEY_RIGHT)
  557. MATRIX_KEY(0x0D, 0x06, KEY_DOWN)
  558. MATRIX_KEY(0x0D, 0x07, KEY_LEFT)
  559. MATRIX_KEY(0x0E, 0x00, KEY_F11)
  560. MATRIX_KEY(0x0E, 0x01, KEY_F12)
  561. MATRIX_KEY(0x0E, 0x02, KEY_F8)
  562. MATRIX_KEY(0x0E, 0x03, KEY_Q)
  563. MATRIX_KEY(0x0E, 0x04, KEY_F4)
  564. MATRIX_KEY(0x0E, 0x05, KEY_F3)
  565. MATRIX_KEY(0x0E, 0x06, KEY_1)
  566. MATRIX_KEY(0x0E, 0x07, KEY_F7)
  567. MATRIX_KEY(0x0F, 0x00, KEY_ESC)
  568. MATRIX_KEY(0x0F, 0x01, KEY_GRAVE)
  569. MATRIX_KEY(0x0F, 0x02, KEY_F5)
  570. MATRIX_KEY(0x0F, 0x03, KEY_TAB)
  571. MATRIX_KEY(0x0F, 0x04, KEY_F1)
  572. MATRIX_KEY(0x0F, 0x05, KEY_F2)
  573. MATRIX_KEY(0x0F, 0x06, KEY_CAPSLOCK)
  574. MATRIX_KEY(0x0F, 0x07, KEY_F6)
  575. /* Software Handled Function Keys */
  576. MATRIX_KEY(0x14, 0x00, KEY_KP7)
  577. MATRIX_KEY(0x15, 0x00, KEY_KP9)
  578. MATRIX_KEY(0x15, 0x01, KEY_KP8)
  579. MATRIX_KEY(0x15, 0x02, KEY_KP4)
  580. MATRIX_KEY(0x15, 0x04, KEY_KP1)
  581. MATRIX_KEY(0x16, 0x01, KEY_KPSLASH)
  582. MATRIX_KEY(0x16, 0x02, KEY_KP6)
  583. MATRIX_KEY(0x16, 0x03, KEY_KP5)
  584. MATRIX_KEY(0x16, 0x04, KEY_KP3)
  585. MATRIX_KEY(0x16, 0x05, KEY_KP2)
  586. MATRIX_KEY(0x16, 0x07, KEY_KP0)
  587. MATRIX_KEY(0x1B, 0x01, KEY_KPASTERISK)
  588. MATRIX_KEY(0x1B, 0x03, KEY_KPMINUS)
  589. MATRIX_KEY(0x1B, 0x04, KEY_KPPLUS)
  590. MATRIX_KEY(0x1B, 0x05, KEY_KPDOT)
  591. MATRIX_KEY(0x1C, 0x05, KEY_VOLUMEUP)
  592. MATRIX_KEY(0x1D, 0x03, KEY_HOME)
  593. MATRIX_KEY(0x1D, 0x04, KEY_END)
  594. MATRIX_KEY(0x1D, 0x05, KEY_BRIGHTNESSDOWN)
  595. MATRIX_KEY(0x1D, 0x06, KEY_VOLUMEDOWN)
  596. MATRIX_KEY(0x1D, 0x07, KEY_BRIGHTNESSUP)
  597. MATRIX_KEY(0x1E, 0x00, KEY_NUMLOCK)
  598. MATRIX_KEY(0x1E, 0x01, KEY_SCROLLLOCK)
  599. MATRIX_KEY(0x1E, 0x02, KEY_MUTE)
  600. MATRIX_KEY(0x1F, 0x04, KEY_HELP)>;
  601. };
  602. pmc@7000e400 {
  603. nvidia,invert-interrupt;
  604. nvidia,suspend-mode = <1>;
  605. nvidia,cpu-pwr-good-time = <5000>;
  606. nvidia,cpu-pwr-off-time = <5000>;
  607. nvidia,core-pwr-good-time = <3845 3845>;
  608. nvidia,core-pwr-off-time = <3875>;
  609. nvidia,sys-clock-req-active-high;
  610. };
  611. memory-controller@7000f400 {
  612. emc-table@190000 {
  613. reg = <190000>;
  614. compatible = "nvidia,tegra20-emc-table";
  615. clock-frequency = <190000>;
  616. nvidia,emc-registers = <0x0000000c 0x00000026
  617. 0x00000009 0x00000003 0x00000004 0x00000004
  618. 0x00000002 0x0000000c 0x00000003 0x00000003
  619. 0x00000002 0x00000001 0x00000004 0x00000005
  620. 0x00000004 0x00000009 0x0000000d 0x0000059f
  621. 0x00000000 0x00000003 0x00000003 0x00000003
  622. 0x00000003 0x00000001 0x0000000b 0x000000c8
  623. 0x00000003 0x00000007 0x00000004 0x0000000f
  624. 0x00000002 0x00000000 0x00000000 0x00000002
  625. 0x00000000 0x00000000 0x00000083 0xa06204ae
  626. 0x007dc010 0x00000000 0x00000000 0x00000000
  627. 0x00000000 0x00000000 0x00000000 0x00000000>;
  628. };
  629. emc-table@380000 {
  630. reg = <380000>;
  631. compatible = "nvidia,tegra20-emc-table";
  632. clock-frequency = <380000>;
  633. nvidia,emc-registers = <0x00000017 0x0000004b
  634. 0x00000012 0x00000006 0x00000004 0x00000005
  635. 0x00000003 0x0000000c 0x00000006 0x00000006
  636. 0x00000003 0x00000001 0x00000004 0x00000005
  637. 0x00000004 0x00000009 0x0000000d 0x00000b5f
  638. 0x00000000 0x00000003 0x00000003 0x00000006
  639. 0x00000006 0x00000001 0x00000011 0x000000c8
  640. 0x00000003 0x0000000e 0x00000007 0x0000000f
  641. 0x00000002 0x00000000 0x00000000 0x00000002
  642. 0x00000000 0x00000000 0x00000083 0xe044048b
  643. 0x007d8010 0x00000000 0x00000000 0x00000000
  644. 0x00000000 0x00000000 0x00000000 0x00000000>;
  645. };
  646. };
  647. usb@c5000000 {
  648. status = "okay";
  649. dr_mode = "otg";
  650. };
  651. usb-phy@c5000000 {
  652. status = "okay";
  653. vbus-supply = <&vbus_reg>;
  654. dr_mode = "otg";
  655. };
  656. usb@c5004000 {
  657. status = "okay";
  658. nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 1)
  659. GPIO_ACTIVE_LOW>;
  660. };
  661. usb-phy@c5004000 {
  662. status = "okay";
  663. nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 1)
  664. GPIO_ACTIVE_LOW>;
  665. };
  666. usb@c5008000 {
  667. status = "okay";
  668. };
  669. usb-phy@c5008000 {
  670. status = "okay";
  671. };
  672. sdhci@c8000000 {
  673. status = "okay";
  674. power-gpios = <&gpio TEGRA_GPIO(K, 6) GPIO_ACTIVE_HIGH>;
  675. bus-width = <4>;
  676. keep-power-in-suspend;
  677. };
  678. sdhci@c8000400 {
  679. status = "okay";
  680. cd-gpios = <&gpio TEGRA_GPIO(I, 5) GPIO_ACTIVE_LOW>;
  681. wp-gpios = <&gpio TEGRA_GPIO(H, 1) GPIO_ACTIVE_HIGH>;
  682. power-gpios = <&gpio TEGRA_GPIO(I, 6) GPIO_ACTIVE_HIGH>;
  683. bus-width = <4>;
  684. };
  685. sdhci@c8000600 {
  686. status = "okay";
  687. bus-width = <8>;
  688. non-removable;
  689. };
  690. backlight: backlight {
  691. compatible = "pwm-backlight";
  692. enable-gpios = <&gpio TEGRA_GPIO(D, 4) GPIO_ACTIVE_HIGH>;
  693. power-supply = <&vdd_bl_reg>;
  694. pwms = <&pwm 2 5000000>;
  695. brightness-levels = <0 4 8 16 32 64 128 255>;
  696. default-brightness-level = <6>;
  697. };
  698. clocks {
  699. compatible = "simple-bus";
  700. #address-cells = <1>;
  701. #size-cells = <0>;
  702. clk32k_in: clock@0 {
  703. compatible = "fixed-clock";
  704. reg=<0>;
  705. #clock-cells = <0>;
  706. clock-frequency = <32768>;
  707. };
  708. };
  709. gpio-keys {
  710. compatible = "gpio-keys";
  711. power {
  712. label = "Power";
  713. gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_LOW>;
  714. linux,code = <KEY_POWER>;
  715. gpio-key,wakeup;
  716. };
  717. lid {
  718. label = "Lid";
  719. gpios = <&gpio TEGRA_GPIO(C, 7) GPIO_ACTIVE_HIGH>;
  720. linux,input-type = <5>; /* EV_SW */
  721. linux,code = <0>; /* SW_LID */
  722. debounce-interval = <1>;
  723. gpio-key,wakeup;
  724. };
  725. };
  726. panel: panel {
  727. compatible = "chunghwa,claa101wa01a", "simple-panel";
  728. power-supply = <&vdd_pnl_reg>;
  729. enable-gpios = <&gpio TEGRA_GPIO(B, 2) GPIO_ACTIVE_HIGH>;
  730. backlight = <&backlight>;
  731. ddc-i2c-bus = <&lvds_ddc>;
  732. };
  733. regulators {
  734. compatible = "simple-bus";
  735. #address-cells = <1>;
  736. #size-cells = <0>;
  737. vdd_5v0_reg: regulator@0 {
  738. compatible = "regulator-fixed";
  739. reg = <0>;
  740. regulator-name = "vdd_5v0";
  741. regulator-min-microvolt = <5000000>;
  742. regulator-max-microvolt = <5000000>;
  743. regulator-always-on;
  744. };
  745. regulator@1 {
  746. compatible = "regulator-fixed";
  747. reg = <1>;
  748. regulator-name = "vdd_1v5";
  749. regulator-min-microvolt = <1500000>;
  750. regulator-max-microvolt = <1500000>;
  751. gpio = <&pmic 0 GPIO_ACTIVE_HIGH>;
  752. };
  753. regulator@2 {
  754. compatible = "regulator-fixed";
  755. reg = <2>;
  756. regulator-name = "vdd_1v2";
  757. regulator-min-microvolt = <1200000>;
  758. regulator-max-microvolt = <1200000>;
  759. gpio = <&pmic 1 GPIO_ACTIVE_HIGH>;
  760. enable-active-high;
  761. };
  762. vbus_reg: regulator@3 {
  763. compatible = "regulator-fixed";
  764. reg = <3>;
  765. regulator-name = "vdd_vbus_wup1";
  766. regulator-min-microvolt = <5000000>;
  767. regulator-max-microvolt = <5000000>;
  768. enable-active-high;
  769. gpio = <&gpio TEGRA_GPIO(D, 0) 0>;
  770. regulator-always-on;
  771. regulator-boot-on;
  772. };
  773. vdd_pnl_reg: regulator@4 {
  774. compatible = "regulator-fixed";
  775. reg = <4>;
  776. regulator-name = "vdd_pnl";
  777. regulator-min-microvolt = <2800000>;
  778. regulator-max-microvolt = <2800000>;
  779. gpio = <&gpio TEGRA_GPIO(C, 6) GPIO_ACTIVE_HIGH>;
  780. enable-active-high;
  781. };
  782. vdd_bl_reg: regulator@5 {
  783. compatible = "regulator-fixed";
  784. reg = <5>;
  785. regulator-name = "vdd_bl";
  786. regulator-min-microvolt = <2800000>;
  787. regulator-max-microvolt = <2800000>;
  788. gpio = <&gpio TEGRA_GPIO(W, 0) GPIO_ACTIVE_HIGH>;
  789. enable-active-high;
  790. };
  791. };
  792. sound {
  793. compatible = "nvidia,tegra-audio-wm8903-seaboard",
  794. "nvidia,tegra-audio-wm8903";
  795. nvidia,model = "NVIDIA Tegra Seaboard";
  796. nvidia,audio-routing =
  797. "Headphone Jack", "HPOUTR",
  798. "Headphone Jack", "HPOUTL",
  799. "Int Spk", "ROP",
  800. "Int Spk", "RON",
  801. "Int Spk", "LOP",
  802. "Int Spk", "LON",
  803. "Mic Jack", "MICBIAS",
  804. "IN1R", "Mic Jack";
  805. nvidia,i2s-controller = <&tegra_i2s1>;
  806. nvidia,audio-codec = <&wm8903>;
  807. nvidia,spkr-en-gpios = <&wm8903 2 GPIO_ACTIVE_HIGH>;
  808. nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(X, 1) GPIO_ACTIVE_HIGH>;
  809. clocks = <&tegra_car TEGRA20_CLK_PLL_A>,
  810. <&tegra_car TEGRA20_CLK_PLL_A_OUT0>,
  811. <&tegra_car TEGRA20_CLK_CDEV1>;
  812. clock-names = "pll_a", "pll_a_out0", "mclk";
  813. };
  814. };