tegra20-trimslice.dts 9.7 KB

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  1. /dts-v1/;
  2. #include <dt-bindings/input/input.h>
  3. #include "tegra20.dtsi"
  4. / {
  5. model = "Compulab TrimSlice board";
  6. compatible = "compulab,trimslice", "nvidia,tegra20";
  7. aliases {
  8. rtc0 = "/i2c@7000c500/rtc@56";
  9. rtc1 = "/rtc@7000e000";
  10. serial0 = &uarta;
  11. };
  12. memory {
  13. reg = <0x00000000 0x40000000>;
  14. };
  15. host1x@50000000 {
  16. hdmi@54280000 {
  17. status = "okay";
  18. vdd-supply = <&hdmi_vdd_reg>;
  19. pll-supply = <&hdmi_pll_reg>;
  20. nvidia,ddc-i2c-bus = <&hdmi_ddc>;
  21. nvidia,hpd-gpio = <&gpio TEGRA_GPIO(N, 7)
  22. GPIO_ACTIVE_HIGH>;
  23. };
  24. };
  25. pinmux@70000014 {
  26. pinctrl-names = "default";
  27. pinctrl-0 = <&state_default>;
  28. state_default: pinmux {
  29. ata {
  30. nvidia,pins = "ata";
  31. nvidia,function = "ide";
  32. };
  33. atb {
  34. nvidia,pins = "atb", "gma";
  35. nvidia,function = "sdio4";
  36. };
  37. atc {
  38. nvidia,pins = "atc", "gmb";
  39. nvidia,function = "nand";
  40. };
  41. atd {
  42. nvidia,pins = "atd", "ate", "gme", "pta";
  43. nvidia,function = "gmi";
  44. };
  45. cdev1 {
  46. nvidia,pins = "cdev1";
  47. nvidia,function = "plla_out";
  48. };
  49. cdev2 {
  50. nvidia,pins = "cdev2";
  51. nvidia,function = "pllp_out4";
  52. };
  53. crtp {
  54. nvidia,pins = "crtp";
  55. nvidia,function = "crt";
  56. };
  57. csus {
  58. nvidia,pins = "csus";
  59. nvidia,function = "vi_sensor_clk";
  60. };
  61. dap1 {
  62. nvidia,pins = "dap1";
  63. nvidia,function = "dap1";
  64. };
  65. dap2 {
  66. nvidia,pins = "dap2";
  67. nvidia,function = "dap2";
  68. };
  69. dap3 {
  70. nvidia,pins = "dap3";
  71. nvidia,function = "dap3";
  72. };
  73. dap4 {
  74. nvidia,pins = "dap4";
  75. nvidia,function = "dap4";
  76. };
  77. ddc {
  78. nvidia,pins = "ddc";
  79. nvidia,function = "i2c2";
  80. };
  81. dta {
  82. nvidia,pins = "dta", "dtb", "dtc", "dtd", "dte";
  83. nvidia,function = "vi";
  84. };
  85. dtf {
  86. nvidia,pins = "dtf";
  87. nvidia,function = "i2c3";
  88. };
  89. gmc {
  90. nvidia,pins = "gmc", "gmd";
  91. nvidia,function = "sflash";
  92. };
  93. gpu {
  94. nvidia,pins = "gpu";
  95. nvidia,function = "uarta";
  96. };
  97. gpu7 {
  98. nvidia,pins = "gpu7";
  99. nvidia,function = "rtck";
  100. };
  101. gpv {
  102. nvidia,pins = "gpv", "slxa", "slxk";
  103. nvidia,function = "pcie";
  104. };
  105. hdint {
  106. nvidia,pins = "hdint";
  107. nvidia,function = "hdmi";
  108. };
  109. i2cp {
  110. nvidia,pins = "i2cp";
  111. nvidia,function = "i2cp";
  112. };
  113. irrx {
  114. nvidia,pins = "irrx", "irtx";
  115. nvidia,function = "uartb";
  116. };
  117. kbca {
  118. nvidia,pins = "kbca", "kbcb", "kbcc", "kbcd",
  119. "kbce", "kbcf";
  120. nvidia,function = "kbc";
  121. };
  122. lcsn {
  123. nvidia,pins = "lcsn", "ld0", "ld1", "ld2",
  124. "ld3", "ld4", "ld5", "ld6", "ld7",
  125. "ld8", "ld9", "ld10", "ld11", "ld12",
  126. "ld13", "ld14", "ld15", "ld16", "ld17",
  127. "ldc", "ldi", "lhp0", "lhp1", "lhp2",
  128. "lhs", "lm0", "lm1", "lpp", "lpw0",
  129. "lpw1", "lpw2", "lsc0", "lsc1", "lsck",
  130. "lsda", "lsdi", "lspi", "lvp0", "lvp1",
  131. "lvs";
  132. nvidia,function = "displaya";
  133. };
  134. owc {
  135. nvidia,pins = "owc", "uac";
  136. nvidia,function = "rsvd2";
  137. };
  138. pmc {
  139. nvidia,pins = "pmc";
  140. nvidia,function = "pwr_on";
  141. };
  142. rm {
  143. nvidia,pins = "rm";
  144. nvidia,function = "i2c1";
  145. };
  146. sdb {
  147. nvidia,pins = "sdb", "sdc", "sdd";
  148. nvidia,function = "pwm";
  149. };
  150. sdio1 {
  151. nvidia,pins = "sdio1";
  152. nvidia,function = "sdio1";
  153. };
  154. slxc {
  155. nvidia,pins = "slxc", "slxd";
  156. nvidia,function = "sdio3";
  157. };
  158. spdi {
  159. nvidia,pins = "spdi", "spdo";
  160. nvidia,function = "spdif";
  161. };
  162. spia {
  163. nvidia,pins = "spia", "spib", "spic";
  164. nvidia,function = "spi2";
  165. };
  166. spid {
  167. nvidia,pins = "spid", "spie", "spif";
  168. nvidia,function = "spi1";
  169. };
  170. spig {
  171. nvidia,pins = "spig", "spih";
  172. nvidia,function = "spi2_alt";
  173. };
  174. uaa {
  175. nvidia,pins = "uaa", "uab", "uda";
  176. nvidia,function = "ulpi";
  177. };
  178. uad {
  179. nvidia,pins = "uad";
  180. nvidia,function = "irda";
  181. };
  182. uca {
  183. nvidia,pins = "uca", "ucb";
  184. nvidia,function = "uartc";
  185. };
  186. conf_ata {
  187. nvidia,pins = "ata", "atc", "atd", "ate",
  188. "crtp", "dap2", "dap3", "dap4", "dta",
  189. "dtb", "dtc", "dtd", "dte", "gmb",
  190. "gme", "i2cp", "pta", "slxc", "slxd",
  191. "spdi", "spdo", "uda";
  192. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  193. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  194. };
  195. conf_atb {
  196. nvidia,pins = "atb", "cdev1", "cdev2", "dap1",
  197. "gma", "gmc", "gmd", "gpu", "gpu7",
  198. "gpv", "sdio1", "slxa", "slxk", "uac";
  199. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  200. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  201. };
  202. conf_ck32 {
  203. nvidia,pins = "ck32", "ddrc", "pmca", "pmcb",
  204. "pmcc", "pmcd", "pmce", "xm2c", "xm2d";
  205. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  206. };
  207. conf_csus {
  208. nvidia,pins = "csus", "spia", "spib",
  209. "spid", "spif";
  210. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  211. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  212. };
  213. conf_ddc {
  214. nvidia,pins = "ddc", "dtf", "rm", "sdc", "sdd";
  215. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  216. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  217. };
  218. conf_hdint {
  219. nvidia,pins = "hdint", "lcsn", "ldc", "lm1",
  220. "lpw1", "lsc1", "lsck", "lsda", "lsdi",
  221. "lvp0", "pmc";
  222. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  223. };
  224. conf_irrx {
  225. nvidia,pins = "irrx", "irtx", "kbca", "kbcb",
  226. "kbcc", "kbcd", "kbce", "kbcf", "owc",
  227. "spic", "spie", "spig", "spih", "uaa",
  228. "uab", "uad", "uca", "ucb";
  229. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  230. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  231. };
  232. conf_lc {
  233. nvidia,pins = "lc", "ls";
  234. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  235. };
  236. conf_ld0 {
  237. nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4",
  238. "ld5", "ld6", "ld7", "ld8", "ld9",
  239. "ld10", "ld11", "ld12", "ld13", "ld14",
  240. "ld15", "ld16", "ld17", "ldi", "lhp0",
  241. "lhp1", "lhp2", "lhs", "lm0", "lpp",
  242. "lpw0", "lpw2", "lsc0", "lspi", "lvp1",
  243. "lvs", "sdb";
  244. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  245. };
  246. conf_ld17_0 {
  247. nvidia,pins = "ld17_0", "ld19_18", "ld21_20",
  248. "ld23_22";
  249. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  250. };
  251. conf_spif {
  252. nvidia,pins = "spif";
  253. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  254. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  255. };
  256. };
  257. };
  258. i2s@70002800 {
  259. status = "okay";
  260. };
  261. serial@70006000 {
  262. status = "okay";
  263. };
  264. dvi_ddc: i2c@7000c000 {
  265. status = "okay";
  266. clock-frequency = <100000>;
  267. };
  268. spi@7000c380 {
  269. status = "okay";
  270. spi-max-frequency = <48000000>;
  271. spi-flash@0 {
  272. compatible = "winbond,w25q80bl";
  273. reg = <0>;
  274. spi-max-frequency = <48000000>;
  275. };
  276. };
  277. hdmi_ddc: i2c@7000c400 {
  278. status = "okay";
  279. clock-frequency = <100000>;
  280. };
  281. i2c@7000c500 {
  282. status = "okay";
  283. clock-frequency = <400000>;
  284. codec: codec@1a {
  285. compatible = "ti,tlv320aic23";
  286. reg = <0x1a>;
  287. };
  288. rtc@56 {
  289. compatible = "emmicro,em3027";
  290. reg = <0x56>;
  291. };
  292. };
  293. pmc@7000e400 {
  294. nvidia,suspend-mode = <1>;
  295. nvidia,cpu-pwr-good-time = <5000>;
  296. nvidia,cpu-pwr-off-time = <5000>;
  297. nvidia,core-pwr-good-time = <3845 3845>;
  298. nvidia,core-pwr-off-time = <3875>;
  299. nvidia,sys-clock-req-active-high;
  300. };
  301. pcie-controller@80003000 {
  302. status = "okay";
  303. avdd-pex-supply = <&pci_vdd_reg>;
  304. vdd-pex-supply = <&pci_vdd_reg>;
  305. avdd-pex-pll-supply = <&pci_vdd_reg>;
  306. avdd-plle-supply = <&pci_vdd_reg>;
  307. vddio-pex-clk-supply = <&pci_clk_reg>;
  308. pci@1,0 {
  309. status = "okay";
  310. };
  311. };
  312. usb@c5000000 {
  313. status = "okay";
  314. };
  315. usb-phy@c5000000 {
  316. status = "okay";
  317. vbus-supply = <&vbus_reg>;
  318. };
  319. usb@c5004000 {
  320. status = "okay";
  321. nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 0)
  322. GPIO_ACTIVE_LOW>;
  323. };
  324. usb-phy@c5004000 {
  325. status = "okay";
  326. nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 0)
  327. GPIO_ACTIVE_LOW>;
  328. };
  329. usb@c5008000 {
  330. status = "okay";
  331. };
  332. usb-phy@c5008000 {
  333. status = "okay";
  334. };
  335. sdhci@c8000000 {
  336. status = "okay";
  337. bus-width = <4>;
  338. };
  339. sdhci@c8000600 {
  340. status = "okay";
  341. cd-gpios = <&gpio TEGRA_GPIO(P, 1) GPIO_ACTIVE_LOW>;
  342. wp-gpios = <&gpio TEGRA_GPIO(P, 2) GPIO_ACTIVE_HIGH>;
  343. bus-width = <4>;
  344. };
  345. clocks {
  346. compatible = "simple-bus";
  347. #address-cells = <1>;
  348. #size-cells = <0>;
  349. clk32k_in: clock@0 {
  350. compatible = "fixed-clock";
  351. reg=<0>;
  352. #clock-cells = <0>;
  353. clock-frequency = <32768>;
  354. };
  355. };
  356. gpio-keys {
  357. compatible = "gpio-keys";
  358. power {
  359. label = "Power";
  360. gpios = <&gpio TEGRA_GPIO(X, 6) GPIO_ACTIVE_LOW>;
  361. linux,code = <KEY_POWER>;
  362. gpio-key,wakeup;
  363. };
  364. };
  365. poweroff {
  366. compatible = "gpio-poweroff";
  367. gpios = <&gpio TEGRA_GPIO(X, 7) GPIO_ACTIVE_LOW>;
  368. };
  369. regulators {
  370. compatible = "simple-bus";
  371. #address-cells = <1>;
  372. #size-cells = <0>;
  373. hdmi_vdd_reg: regulator@0 {
  374. compatible = "regulator-fixed";
  375. reg = <0>;
  376. regulator-name = "avdd_hdmi";
  377. regulator-min-microvolt = <3300000>;
  378. regulator-max-microvolt = <3300000>;
  379. regulator-always-on;
  380. };
  381. hdmi_pll_reg: regulator@1 {
  382. compatible = "regulator-fixed";
  383. reg = <1>;
  384. regulator-name = "avdd_hdmi_pll";
  385. regulator-min-microvolt = <1800000>;
  386. regulator-max-microvolt = <1800000>;
  387. regulator-always-on;
  388. };
  389. vbus_reg: regulator@2 {
  390. compatible = "regulator-fixed";
  391. reg = <2>;
  392. regulator-name = "usb1_vbus";
  393. regulator-min-microvolt = <5000000>;
  394. regulator-max-microvolt = <5000000>;
  395. enable-active-high;
  396. gpio = <&gpio TEGRA_GPIO(V, 2) 0>;
  397. regulator-always-on;
  398. regulator-boot-on;
  399. };
  400. pci_clk_reg: regulator@3 {
  401. compatible = "regulator-fixed";
  402. reg = <3>;
  403. regulator-name = "pci_clk";
  404. regulator-min-microvolt = <3300000>;
  405. regulator-max-microvolt = <3300000>;
  406. regulator-always-on;
  407. };
  408. pci_vdd_reg: regulator@4 {
  409. compatible = "regulator-fixed";
  410. reg = <4>;
  411. regulator-name = "pci_vdd";
  412. regulator-min-microvolt = <1050000>;
  413. regulator-max-microvolt = <1050000>;
  414. regulator-always-on;
  415. };
  416. };
  417. sound {
  418. compatible = "nvidia,tegra-audio-trimslice";
  419. nvidia,i2s-controller = <&tegra_i2s1>;
  420. nvidia,audio-codec = <&codec>;
  421. clocks = <&tegra_car TEGRA20_CLK_PLL_A>,
  422. <&tegra_car TEGRA20_CLK_PLL_A_OUT0>,
  423. <&tegra_car TEGRA20_CLK_CDEV1>;
  424. clock-names = "pll_a", "pll_a_out0", "mclk";
  425. };
  426. };