tegra20-ventana.dts 15 KB

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  1. /dts-v1/;
  2. #include <dt-bindings/input/input.h>
  3. #include "tegra20.dtsi"
  4. / {
  5. model = "NVIDIA Tegra20 Ventana evaluation board";
  6. compatible = "nvidia,ventana", "nvidia,tegra20";
  7. aliases {
  8. rtc0 = "/i2c@7000d000/tps6586x@34";
  9. rtc1 = "/rtc@7000e000";
  10. serial0 = &uartd;
  11. };
  12. memory {
  13. reg = <0x00000000 0x40000000>;
  14. };
  15. host1x@50000000 {
  16. dc@54200000 {
  17. rgb {
  18. status = "okay";
  19. nvidia,panel = <&panel>;
  20. };
  21. };
  22. hdmi@54280000 {
  23. status = "okay";
  24. vdd-supply = <&hdmi_vdd_reg>;
  25. pll-supply = <&hdmi_pll_reg>;
  26. nvidia,ddc-i2c-bus = <&hdmi_ddc>;
  27. nvidia,hpd-gpio = <&gpio TEGRA_GPIO(N, 7)
  28. GPIO_ACTIVE_HIGH>;
  29. };
  30. };
  31. pinmux@70000014 {
  32. pinctrl-names = "default";
  33. pinctrl-0 = <&state_default>;
  34. state_default: pinmux {
  35. ata {
  36. nvidia,pins = "ata";
  37. nvidia,function = "ide";
  38. };
  39. atb {
  40. nvidia,pins = "atb", "gma", "gme";
  41. nvidia,function = "sdio4";
  42. };
  43. atc {
  44. nvidia,pins = "atc";
  45. nvidia,function = "nand";
  46. };
  47. atd {
  48. nvidia,pins = "atd", "ate", "gmb", "spia",
  49. "spib", "spic";
  50. nvidia,function = "gmi";
  51. };
  52. cdev1 {
  53. nvidia,pins = "cdev1";
  54. nvidia,function = "plla_out";
  55. };
  56. cdev2 {
  57. nvidia,pins = "cdev2";
  58. nvidia,function = "pllp_out4";
  59. };
  60. crtp {
  61. nvidia,pins = "crtp", "lm1";
  62. nvidia,function = "crt";
  63. };
  64. csus {
  65. nvidia,pins = "csus";
  66. nvidia,function = "vi_sensor_clk";
  67. };
  68. dap1 {
  69. nvidia,pins = "dap1";
  70. nvidia,function = "dap1";
  71. };
  72. dap2 {
  73. nvidia,pins = "dap2";
  74. nvidia,function = "dap2";
  75. };
  76. dap3 {
  77. nvidia,pins = "dap3";
  78. nvidia,function = "dap3";
  79. };
  80. dap4 {
  81. nvidia,pins = "dap4";
  82. nvidia,function = "dap4";
  83. };
  84. dta {
  85. nvidia,pins = "dta", "dtb", "dtc", "dtd", "dte";
  86. nvidia,function = "vi";
  87. };
  88. dtf {
  89. nvidia,pins = "dtf";
  90. nvidia,function = "i2c3";
  91. };
  92. gmc {
  93. nvidia,pins = "gmc";
  94. nvidia,function = "uartd";
  95. };
  96. gmd {
  97. nvidia,pins = "gmd";
  98. nvidia,function = "sflash";
  99. };
  100. gpu {
  101. nvidia,pins = "gpu";
  102. nvidia,function = "pwm";
  103. };
  104. gpu7 {
  105. nvidia,pins = "gpu7";
  106. nvidia,function = "rtck";
  107. };
  108. gpv {
  109. nvidia,pins = "gpv", "slxa", "slxk";
  110. nvidia,function = "pcie";
  111. };
  112. hdint {
  113. nvidia,pins = "hdint";
  114. nvidia,function = "hdmi";
  115. };
  116. i2cp {
  117. nvidia,pins = "i2cp";
  118. nvidia,function = "i2cp";
  119. };
  120. irrx {
  121. nvidia,pins = "irrx", "irtx";
  122. nvidia,function = "uartb";
  123. };
  124. kbca {
  125. nvidia,pins = "kbca", "kbcb", "kbcc", "kbcd",
  126. "kbce", "kbcf";
  127. nvidia,function = "kbc";
  128. };
  129. lcsn {
  130. nvidia,pins = "lcsn", "ldc", "lm0", "lpw1",
  131. "lsdi", "lvp0";
  132. nvidia,function = "rsvd4";
  133. };
  134. ld0 {
  135. nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4",
  136. "ld5", "ld6", "ld7", "ld8", "ld9",
  137. "ld10", "ld11", "ld12", "ld13", "ld14",
  138. "ld15", "ld16", "ld17", "ldi", "lhp0",
  139. "lhp1", "lhp2", "lhs", "lpp", "lpw0",
  140. "lpw2", "lsc0", "lsc1", "lsck", "lsda",
  141. "lspi", "lvp1", "lvs";
  142. nvidia,function = "displaya";
  143. };
  144. owc {
  145. nvidia,pins = "owc", "spdi", "spdo", "uac";
  146. nvidia,function = "rsvd2";
  147. };
  148. pmc {
  149. nvidia,pins = "pmc";
  150. nvidia,function = "pwr_on";
  151. };
  152. rm {
  153. nvidia,pins = "rm";
  154. nvidia,function = "i2c1";
  155. };
  156. sdb {
  157. nvidia,pins = "sdb", "sdc", "sdd", "slxc";
  158. nvidia,function = "sdio3";
  159. };
  160. sdio1 {
  161. nvidia,pins = "sdio1";
  162. nvidia,function = "sdio1";
  163. };
  164. slxd {
  165. nvidia,pins = "slxd";
  166. nvidia,function = "spdif";
  167. };
  168. spid {
  169. nvidia,pins = "spid", "spie", "spif";
  170. nvidia,function = "spi1";
  171. };
  172. spig {
  173. nvidia,pins = "spig", "spih";
  174. nvidia,function = "spi2_alt";
  175. };
  176. uaa {
  177. nvidia,pins = "uaa", "uab", "uda";
  178. nvidia,function = "ulpi";
  179. };
  180. uad {
  181. nvidia,pins = "uad";
  182. nvidia,function = "irda";
  183. };
  184. uca {
  185. nvidia,pins = "uca", "ucb";
  186. nvidia,function = "uartc";
  187. };
  188. conf_ata {
  189. nvidia,pins = "ata", "atb", "atc", "atd",
  190. "cdev1", "cdev2", "dap1", "dap2",
  191. "dap4", "ddc", "dtf", "gma", "gmc",
  192. "gme", "gpu", "gpu7", "i2cp", "irrx",
  193. "irtx", "pta", "rm", "sdc", "sdd",
  194. "slxc", "slxd", "slxk", "spdi", "spdo",
  195. "uac", "uad", "uca", "ucb", "uda";
  196. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  197. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  198. };
  199. conf_ate {
  200. nvidia,pins = "ate", "csus", "dap3", "gmd",
  201. "gpv", "owc", "spia", "spib", "spic",
  202. "spid", "spie", "spig";
  203. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  204. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  205. };
  206. conf_ck32 {
  207. nvidia,pins = "ck32", "ddrc", "pmca", "pmcb",
  208. "pmcc", "pmcd", "pmce", "xm2c", "xm2d";
  209. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  210. };
  211. conf_crtp {
  212. nvidia,pins = "crtp", "gmb", "slxa", "spih";
  213. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  214. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  215. };
  216. conf_dta {
  217. nvidia,pins = "dta", "dtb", "dtc", "dtd";
  218. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  219. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  220. };
  221. conf_dte {
  222. nvidia,pins = "dte", "spif";
  223. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  224. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  225. };
  226. conf_hdint {
  227. nvidia,pins = "hdint", "lcsn", "ldc", "lm1",
  228. "lpw1", "lsck", "lsda", "lsdi", "lvp0";
  229. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  230. };
  231. conf_kbca {
  232. nvidia,pins = "kbca", "kbcb", "kbcc", "kbcd",
  233. "kbce", "kbcf", "sdio1", "uaa", "uab";
  234. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  235. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  236. };
  237. conf_lc {
  238. nvidia,pins = "lc", "ls";
  239. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  240. };
  241. conf_ld0 {
  242. nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4",
  243. "ld5", "ld6", "ld7", "ld8", "ld9",
  244. "ld10", "ld11", "ld12", "ld13", "ld14",
  245. "ld15", "ld16", "ld17", "ldi", "lhp0",
  246. "lhp1", "lhp2", "lhs", "lm0", "lpp",
  247. "lpw0", "lpw2", "lsc0", "lsc1", "lspi",
  248. "lvp1", "lvs", "pmc", "sdb";
  249. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  250. };
  251. conf_ld17_0 {
  252. nvidia,pins = "ld17_0", "ld19_18", "ld21_20",
  253. "ld23_22";
  254. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  255. };
  256. drive_sdio1 {
  257. nvidia,pins = "drive_sdio1";
  258. nvidia,high-speed-mode = <TEGRA_PIN_DISABLE>;
  259. nvidia,schmitt = <TEGRA_PIN_ENABLE>;
  260. nvidia,low-power-mode = <TEGRA_PIN_LP_DRIVE_DIV_1>;
  261. nvidia,pull-down-strength = <31>;
  262. nvidia,pull-up-strength = <31>;
  263. nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_SLOWEST>;
  264. nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_SLOWEST>;
  265. };
  266. };
  267. state_i2cmux_ddc: pinmux_i2cmux_ddc {
  268. ddc {
  269. nvidia,pins = "ddc";
  270. nvidia,function = "i2c2";
  271. };
  272. pta {
  273. nvidia,pins = "pta";
  274. nvidia,function = "rsvd4";
  275. };
  276. };
  277. state_i2cmux_pta: pinmux_i2cmux_pta {
  278. ddc {
  279. nvidia,pins = "ddc";
  280. nvidia,function = "rsvd4";
  281. };
  282. pta {
  283. nvidia,pins = "pta";
  284. nvidia,function = "i2c2";
  285. };
  286. };
  287. state_i2cmux_idle: pinmux_i2cmux_idle {
  288. ddc {
  289. nvidia,pins = "ddc";
  290. nvidia,function = "rsvd4";
  291. };
  292. pta {
  293. nvidia,pins = "pta";
  294. nvidia,function = "rsvd4";
  295. };
  296. };
  297. };
  298. i2s@70002800 {
  299. status = "okay";
  300. };
  301. serial@70006300 {
  302. status = "okay";
  303. };
  304. pwm: pwm@7000a000 {
  305. status = "okay";
  306. };
  307. i2c@7000c000 {
  308. status = "okay";
  309. clock-frequency = <400000>;
  310. wm8903: wm8903@1a {
  311. compatible = "wlf,wm8903";
  312. reg = <0x1a>;
  313. interrupt-parent = <&gpio>;
  314. interrupts = <TEGRA_GPIO(X, 3) IRQ_TYPE_LEVEL_HIGH>;
  315. gpio-controller;
  316. #gpio-cells = <2>;
  317. micdet-cfg = <0>;
  318. micdet-delay = <100>;
  319. gpio-cfg = <0xffffffff 0xffffffff 0 0xffffffff 0xffffffff>;
  320. };
  321. /* ALS and proximity sensor */
  322. isl29018@44 {
  323. compatible = "isil,isl29018";
  324. reg = <0x44>;
  325. interrupt-parent = <&gpio>;
  326. interrupts = <TEGRA_GPIO(Z, 2) IRQ_TYPE_LEVEL_HIGH>;
  327. };
  328. };
  329. i2c@7000c400 {
  330. status = "okay";
  331. clock-frequency = <100000>;
  332. };
  333. i2cmux {
  334. compatible = "i2c-mux-pinctrl";
  335. #address-cells = <1>;
  336. #size-cells = <0>;
  337. i2c-parent = <&{/i2c@7000c400}>;
  338. pinctrl-names = "ddc", "pta", "idle";
  339. pinctrl-0 = <&state_i2cmux_ddc>;
  340. pinctrl-1 = <&state_i2cmux_pta>;
  341. pinctrl-2 = <&state_i2cmux_idle>;
  342. hdmi_ddc: i2c@0 {
  343. reg = <0>;
  344. #address-cells = <1>;
  345. #size-cells = <0>;
  346. };
  347. lvds_ddc: i2c@1 {
  348. reg = <1>;
  349. #address-cells = <1>;
  350. #size-cells = <0>;
  351. };
  352. };
  353. i2c@7000c500 {
  354. status = "okay";
  355. clock-frequency = <400000>;
  356. };
  357. i2c@7000d000 {
  358. status = "okay";
  359. clock-frequency = <400000>;
  360. pmic: tps6586x@34 {
  361. compatible = "ti,tps6586x";
  362. reg = <0x34>;
  363. interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
  364. ti,system-power-controller;
  365. #gpio-cells = <2>;
  366. gpio-controller;
  367. sys-supply = <&vdd_5v0_reg>;
  368. vin-sm0-supply = <&sys_reg>;
  369. vin-sm1-supply = <&sys_reg>;
  370. vin-sm2-supply = <&sys_reg>;
  371. vinldo01-supply = <&sm2_reg>;
  372. vinldo23-supply = <&sm2_reg>;
  373. vinldo4-supply = <&sm2_reg>;
  374. vinldo678-supply = <&sm2_reg>;
  375. vinldo9-supply = <&sm2_reg>;
  376. regulators {
  377. sys_reg: sys {
  378. regulator-name = "vdd_sys";
  379. regulator-always-on;
  380. };
  381. sm0 {
  382. regulator-name = "vdd_sm0,vdd_core";
  383. regulator-min-microvolt = <1200000>;
  384. regulator-max-microvolt = <1200000>;
  385. regulator-always-on;
  386. };
  387. sm1 {
  388. regulator-name = "vdd_sm1,vdd_cpu";
  389. regulator-min-microvolt = <1000000>;
  390. regulator-max-microvolt = <1000000>;
  391. regulator-always-on;
  392. };
  393. sm2_reg: sm2 {
  394. regulator-name = "vdd_sm2,vin_ldo*";
  395. regulator-min-microvolt = <3700000>;
  396. regulator-max-microvolt = <3700000>;
  397. regulator-always-on;
  398. };
  399. /* LDO0 is not connected to anything */
  400. ldo1 {
  401. regulator-name = "vdd_ldo1,avdd_pll*";
  402. regulator-min-microvolt = <1100000>;
  403. regulator-max-microvolt = <1100000>;
  404. regulator-always-on;
  405. };
  406. ldo2 {
  407. regulator-name = "vdd_ldo2,vdd_rtc";
  408. regulator-min-microvolt = <1200000>;
  409. regulator-max-microvolt = <1200000>;
  410. };
  411. ldo3 {
  412. regulator-name = "vdd_ldo3,avdd_usb*";
  413. regulator-min-microvolt = <3300000>;
  414. regulator-max-microvolt = <3300000>;
  415. regulator-always-on;
  416. };
  417. ldo4 {
  418. regulator-name = "vdd_ldo4,avdd_osc,vddio_sys";
  419. regulator-min-microvolt = <1800000>;
  420. regulator-max-microvolt = <1800000>;
  421. regulator-always-on;
  422. };
  423. ldo5 {
  424. regulator-name = "vdd_ldo5,vcore_mmc";
  425. regulator-min-microvolt = <2850000>;
  426. regulator-max-microvolt = <2850000>;
  427. regulator-always-on;
  428. };
  429. ldo6 {
  430. regulator-name = "vdd_ldo6,avdd_vdac";
  431. regulator-min-microvolt = <1800000>;
  432. regulator-max-microvolt = <1800000>;
  433. };
  434. hdmi_vdd_reg: ldo7 {
  435. regulator-name = "vdd_ldo7,avdd_hdmi,vdd_fuse";
  436. regulator-min-microvolt = <3300000>;
  437. regulator-max-microvolt = <3300000>;
  438. };
  439. hdmi_pll_reg: ldo8 {
  440. regulator-name = "vdd_ldo8,avdd_hdmi_pll";
  441. regulator-min-microvolt = <1800000>;
  442. regulator-max-microvolt = <1800000>;
  443. };
  444. ldo9 {
  445. regulator-name = "vdd_ldo9,avdd_2v85,vdd_ddr_rx";
  446. regulator-min-microvolt = <2850000>;
  447. regulator-max-microvolt = <2850000>;
  448. regulator-always-on;
  449. };
  450. ldo_rtc {
  451. regulator-name = "vdd_rtc_out,vdd_cell";
  452. regulator-min-microvolt = <3300000>;
  453. regulator-max-microvolt = <3300000>;
  454. regulator-always-on;
  455. };
  456. };
  457. };
  458. temperature-sensor@4c {
  459. compatible = "onnn,nct1008";
  460. reg = <0x4c>;
  461. };
  462. };
  463. pmc@7000e400 {
  464. nvidia,invert-interrupt;
  465. nvidia,suspend-mode = <1>;
  466. nvidia,cpu-pwr-good-time = <2000>;
  467. nvidia,cpu-pwr-off-time = <100>;
  468. nvidia,core-pwr-good-time = <3845 3845>;
  469. nvidia,core-pwr-off-time = <458>;
  470. nvidia,sys-clock-req-active-high;
  471. };
  472. usb@c5000000 {
  473. status = "okay";
  474. };
  475. usb-phy@c5000000 {
  476. status = "okay";
  477. };
  478. usb@c5004000 {
  479. status = "okay";
  480. nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 1)
  481. GPIO_ACTIVE_LOW>;
  482. };
  483. usb-phy@c5004000 {
  484. status = "okay";
  485. nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 1)
  486. GPIO_ACTIVE_LOW>;
  487. };
  488. usb@c5008000 {
  489. status = "okay";
  490. };
  491. usb-phy@c5008000 {
  492. status = "okay";
  493. };
  494. sdhci@c8000000 {
  495. status = "okay";
  496. power-gpios = <&gpio TEGRA_GPIO(K, 6) GPIO_ACTIVE_HIGH>;
  497. bus-width = <4>;
  498. keep-power-in-suspend;
  499. };
  500. sdhci@c8000400 {
  501. status = "okay";
  502. cd-gpios = <&gpio TEGRA_GPIO(I, 5) GPIO_ACTIVE_LOW>;
  503. wp-gpios = <&gpio TEGRA_GPIO(H, 1) GPIO_ACTIVE_HIGH>;
  504. power-gpios = <&gpio TEGRA_GPIO(I, 6) GPIO_ACTIVE_HIGH>;
  505. bus-width = <4>;
  506. };
  507. sdhci@c8000600 {
  508. status = "okay";
  509. bus-width = <8>;
  510. non-removable;
  511. };
  512. backlight: backlight {
  513. compatible = "pwm-backlight";
  514. enable-gpios = <&gpio TEGRA_GPIO(D, 4) GPIO_ACTIVE_HIGH>;
  515. power-supply = <&vdd_bl_reg>;
  516. pwms = <&pwm 2 5000000>;
  517. brightness-levels = <0 4 8 16 32 64 128 255>;
  518. default-brightness-level = <6>;
  519. };
  520. clocks {
  521. compatible = "simple-bus";
  522. #address-cells = <1>;
  523. #size-cells = <0>;
  524. clk32k_in: clock@0 {
  525. compatible = "fixed-clock";
  526. reg=<0>;
  527. #clock-cells = <0>;
  528. clock-frequency = <32768>;
  529. };
  530. };
  531. gpio-keys {
  532. compatible = "gpio-keys";
  533. power {
  534. label = "Power";
  535. gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_LOW>;
  536. linux,code = <KEY_POWER>;
  537. gpio-key,wakeup;
  538. };
  539. };
  540. panel: panel {
  541. compatible = "chunghwa,claa101wa01a", "simple-panel";
  542. power-supply = <&vdd_pnl_reg>;
  543. enable-gpios = <&gpio TEGRA_GPIO(B, 2) GPIO_ACTIVE_HIGH>;
  544. backlight = <&backlight>;
  545. ddc-i2c-bus = <&lvds_ddc>;
  546. };
  547. regulators {
  548. compatible = "simple-bus";
  549. #address-cells = <1>;
  550. #size-cells = <0>;
  551. vdd_5v0_reg: regulator@0 {
  552. compatible = "regulator-fixed";
  553. reg = <0>;
  554. regulator-name = "vdd_5v0";
  555. regulator-min-microvolt = <5000000>;
  556. regulator-max-microvolt = <5000000>;
  557. regulator-always-on;
  558. };
  559. regulator@1 {
  560. compatible = "regulator-fixed";
  561. reg = <1>;
  562. regulator-name = "vdd_1v5";
  563. regulator-min-microvolt = <1500000>;
  564. regulator-max-microvolt = <1500000>;
  565. gpio = <&pmic 0 GPIO_ACTIVE_HIGH>;
  566. };
  567. regulator@2 {
  568. compatible = "regulator-fixed";
  569. reg = <2>;
  570. regulator-name = "vdd_1v2";
  571. regulator-min-microvolt = <1200000>;
  572. regulator-max-microvolt = <1200000>;
  573. gpio = <&pmic 1 GPIO_ACTIVE_HIGH>;
  574. enable-active-high;
  575. };
  576. vdd_pnl_reg: regulator@3 {
  577. compatible = "regulator-fixed";
  578. reg = <3>;
  579. regulator-name = "vdd_pnl";
  580. regulator-min-microvolt = <2800000>;
  581. regulator-max-microvolt = <2800000>;
  582. gpio = <&gpio TEGRA_GPIO(C, 6) GPIO_ACTIVE_HIGH>;
  583. enable-active-high;
  584. };
  585. vdd_bl_reg: regulator@4 {
  586. compatible = "regulator-fixed";
  587. reg = <4>;
  588. regulator-name = "vdd_bl";
  589. regulator-min-microvolt = <2800000>;
  590. regulator-max-microvolt = <2800000>;
  591. gpio = <&gpio TEGRA_GPIO(W, 0) GPIO_ACTIVE_HIGH>;
  592. enable-active-high;
  593. };
  594. };
  595. sound {
  596. compatible = "nvidia,tegra-audio-wm8903-ventana",
  597. "nvidia,tegra-audio-wm8903";
  598. nvidia,model = "NVIDIA Tegra Ventana";
  599. nvidia,audio-routing =
  600. "Headphone Jack", "HPOUTR",
  601. "Headphone Jack", "HPOUTL",
  602. "Int Spk", "ROP",
  603. "Int Spk", "RON",
  604. "Int Spk", "LOP",
  605. "Int Spk", "LON",
  606. "Mic Jack", "MICBIAS",
  607. "IN1L", "Mic Jack";
  608. nvidia,i2s-controller = <&tegra_i2s1>;
  609. nvidia,audio-codec = <&wm8903>;
  610. nvidia,spkr-en-gpios = <&wm8903 2 GPIO_ACTIVE_HIGH>;
  611. nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(W, 2) GPIO_ACTIVE_HIGH>;
  612. nvidia,int-mic-en-gpios = <&gpio TEGRA_GPIO(X, 0)
  613. GPIO_ACTIVE_HIGH>;
  614. nvidia,ext-mic-en-gpios = <&gpio TEGRA_GPIO(X, 1)
  615. GPIO_ACTIVE_HIGH>;
  616. clocks = <&tegra_car TEGRA20_CLK_PLL_A>,
  617. <&tegra_car TEGRA20_CLK_PLL_A_OUT0>,
  618. <&tegra_car TEGRA20_CLK_CDEV1>;
  619. clock-names = "pll_a", "pll_a_out0", "mclk";
  620. };
  621. };