tegra30-cardhu.dtsi 15 KB

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  1. #include "tegra30.dtsi"
  2. /**
  3. * This file contains common DT entry for all fab version of Cardhu.
  4. * There is multiple fab version of Cardhu starting from A01 to A07.
  5. * Cardhu fab version A01 and A03 are not supported. Cardhu fab version
  6. * A02 will have different sets of GPIOs for fixed regulator compare to
  7. * Cardhu fab version A04. The Cardhu fab version A05, A06, A07 are
  8. * compatible with fab version A04. Based on Cardhu fab version, the
  9. * related dts file need to be chosen like for Cardhu fab version A02,
  10. * use tegra30-cardhu-a02.dts, Cardhu fab version A04 and later, use
  11. * tegra30-cardhu-a04.dts.
  12. * The identification of board is done in two ways, by looking the sticker
  13. * on PCB and by reading board id eeprom.
  14. * The stciker will have number like 600-81291-1000-002 C.3. In this 4th
  15. * number is the fab version like here it is 002 and hence fab version A02.
  16. * The (downstream internal) U-Boot of Cardhu display the board-id as
  17. * follows:
  18. * BoardID: 0C5B, SKU: 0A01, Fab: 02, Rev: 45.00
  19. * In this Fab version is 02 i.e. A02.
  20. * The BoardID I2C eeprom is interfaced through i2c5 (pwr_i2c address 0x56).
  21. * The location 0x8 of this eeprom contains the Fab version. It is 1 byte
  22. * wide.
  23. */
  24. / {
  25. model = "NVIDIA Tegra30 Cardhu evaluation board";
  26. compatible = "nvidia,cardhu", "nvidia,tegra30";
  27. aliases {
  28. rtc0 = "/i2c@7000d000/tps65911@2d";
  29. rtc1 = "/rtc@7000e000";
  30. serial0 = &uarta;
  31. serial1 = &uartc;
  32. };
  33. memory {
  34. reg = <0x80000000 0x40000000>;
  35. };
  36. pcie-controller@00003000 {
  37. status = "okay";
  38. /* AVDD_PEXA and VDD_PEXA inputs are grounded on Cardhu. */
  39. avdd-pexb-supply = <&ldo1_reg>;
  40. vdd-pexb-supply = <&ldo1_reg>;
  41. avdd-pex-pll-supply = <&ldo1_reg>;
  42. hvdd-pex-supply = <&pex_hvdd_3v3_reg>;
  43. vddio-pex-ctl-supply = <&sys_3v3_reg>;
  44. avdd-plle-supply = <&ldo2_reg>;
  45. pci@1,0 {
  46. nvidia,num-lanes = <4>;
  47. };
  48. pci@2,0 {
  49. nvidia,num-lanes = <1>;
  50. };
  51. pci@3,0 {
  52. status = "okay";
  53. nvidia,num-lanes = <1>;
  54. };
  55. };
  56. host1x@50000000 {
  57. dc@54200000 {
  58. rgb {
  59. status = "okay";
  60. nvidia,panel = <&panel>;
  61. };
  62. };
  63. };
  64. pinmux@70000868 {
  65. pinctrl-names = "default";
  66. pinctrl-0 = <&state_default>;
  67. state_default: pinmux {
  68. sdmmc1_clk_pz0 {
  69. nvidia,pins = "sdmmc1_clk_pz0";
  70. nvidia,function = "sdmmc1";
  71. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  72. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  73. };
  74. sdmmc1_cmd_pz1 {
  75. nvidia,pins = "sdmmc1_cmd_pz1",
  76. "sdmmc1_dat0_py7",
  77. "sdmmc1_dat1_py6",
  78. "sdmmc1_dat2_py5",
  79. "sdmmc1_dat3_py4";
  80. nvidia,function = "sdmmc1";
  81. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  82. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  83. };
  84. sdmmc3_clk_pa6 {
  85. nvidia,pins = "sdmmc3_clk_pa6";
  86. nvidia,function = "sdmmc3";
  87. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  88. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  89. };
  90. sdmmc3_cmd_pa7 {
  91. nvidia,pins = "sdmmc3_cmd_pa7",
  92. "sdmmc3_dat0_pb7",
  93. "sdmmc3_dat1_pb6",
  94. "sdmmc3_dat2_pb5",
  95. "sdmmc3_dat3_pb4";
  96. nvidia,function = "sdmmc3";
  97. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  98. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  99. };
  100. sdmmc4_clk_pcc4 {
  101. nvidia,pins = "sdmmc4_clk_pcc4",
  102. "sdmmc4_rst_n_pcc3";
  103. nvidia,function = "sdmmc4";
  104. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  105. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  106. };
  107. sdmmc4_dat0_paa0 {
  108. nvidia,pins = "sdmmc4_dat0_paa0",
  109. "sdmmc4_dat1_paa1",
  110. "sdmmc4_dat2_paa2",
  111. "sdmmc4_dat3_paa3",
  112. "sdmmc4_dat4_paa4",
  113. "sdmmc4_dat5_paa5",
  114. "sdmmc4_dat6_paa6",
  115. "sdmmc4_dat7_paa7";
  116. nvidia,function = "sdmmc4";
  117. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  118. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  119. };
  120. dap2_fs_pa2 {
  121. nvidia,pins = "dap2_fs_pa2",
  122. "dap2_sclk_pa3",
  123. "dap2_din_pa4",
  124. "dap2_dout_pa5";
  125. nvidia,function = "i2s1";
  126. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  127. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  128. };
  129. sdio3 {
  130. nvidia,pins = "drive_sdio3";
  131. nvidia,high-speed-mode = <TEGRA_PIN_DISABLE>;
  132. nvidia,schmitt = <TEGRA_PIN_DISABLE>;
  133. nvidia,pull-down-strength = <46>;
  134. nvidia,pull-up-strength = <42>;
  135. nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_FAST>;
  136. nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_FAST>;
  137. };
  138. uart3_txd_pw6 {
  139. nvidia,pins = "uart3_txd_pw6",
  140. "uart3_cts_n_pa1",
  141. "uart3_rts_n_pc0",
  142. "uart3_rxd_pw7";
  143. nvidia,function = "uartc";
  144. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  145. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  146. };
  147. };
  148. };
  149. serial@70006000 {
  150. status = "okay";
  151. };
  152. serial@70006200 {
  153. compatible = "nvidia,tegra30-hsuart";
  154. status = "okay";
  155. };
  156. pwm@7000a000 {
  157. status = "okay";
  158. };
  159. panelddc: i2c@7000c000 {
  160. status = "okay";
  161. clock-frequency = <100000>;
  162. };
  163. i2c@7000c400 {
  164. status = "okay";
  165. clock-frequency = <100000>;
  166. };
  167. i2c@7000c500 {
  168. status = "okay";
  169. clock-frequency = <100000>;
  170. /* ALS and Proximity sensor */
  171. isl29028@44 {
  172. compatible = "isil,isl29028";
  173. reg = <0x44>;
  174. interrupt-parent = <&gpio>;
  175. interrupts = <TEGRA_GPIO(L, 0) IRQ_TYPE_LEVEL_HIGH>;
  176. };
  177. i2cmux@70 {
  178. compatible = "nxp,pca9546";
  179. #address-cells = <1>;
  180. #size-cells = <0>;
  181. reg = <0x70>;
  182. };
  183. };
  184. i2c@7000c700 {
  185. status = "okay";
  186. clock-frequency = <100000>;
  187. };
  188. i2c@7000d000 {
  189. status = "okay";
  190. clock-frequency = <100000>;
  191. wm8903: wm8903@1a {
  192. compatible = "wlf,wm8903";
  193. reg = <0x1a>;
  194. interrupt-parent = <&gpio>;
  195. interrupts = <TEGRA_GPIO(W, 3) IRQ_TYPE_LEVEL_HIGH>;
  196. gpio-controller;
  197. #gpio-cells = <2>;
  198. micdet-cfg = <0>;
  199. micdet-delay = <100>;
  200. gpio-cfg = <0xffffffff 0xffffffff 0 0xffffffff 0xffffffff>;
  201. };
  202. pmic: tps65911@2d {
  203. compatible = "ti,tps65911";
  204. reg = <0x2d>;
  205. interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
  206. #interrupt-cells = <2>;
  207. interrupt-controller;
  208. ti,system-power-controller;
  209. #gpio-cells = <2>;
  210. gpio-controller;
  211. vcc1-supply = <&vdd_ac_bat_reg>;
  212. vcc2-supply = <&vdd_ac_bat_reg>;
  213. vcc3-supply = <&vio_reg>;
  214. vcc4-supply = <&vdd_5v0_reg>;
  215. vcc5-supply = <&vdd_ac_bat_reg>;
  216. vcc6-supply = <&vdd2_reg>;
  217. vcc7-supply = <&vdd_ac_bat_reg>;
  218. vccio-supply = <&vdd_ac_bat_reg>;
  219. regulators {
  220. vdd1_reg: vdd1 {
  221. regulator-name = "vddio_ddr_1v2";
  222. regulator-min-microvolt = <1200000>;
  223. regulator-max-microvolt = <1200000>;
  224. regulator-always-on;
  225. };
  226. vdd2_reg: vdd2 {
  227. regulator-name = "vdd_1v5_gen";
  228. regulator-min-microvolt = <1500000>;
  229. regulator-max-microvolt = <1500000>;
  230. regulator-always-on;
  231. };
  232. vddctrl_reg: vddctrl {
  233. regulator-name = "vdd_cpu,vdd_sys";
  234. regulator-min-microvolt = <1000000>;
  235. regulator-max-microvolt = <1000000>;
  236. regulator-always-on;
  237. };
  238. vio_reg: vio {
  239. regulator-name = "vdd_1v8_gen";
  240. regulator-min-microvolt = <1800000>;
  241. regulator-max-microvolt = <1800000>;
  242. regulator-always-on;
  243. };
  244. ldo1_reg: ldo1 {
  245. regulator-name = "vdd_pexa,vdd_pexb";
  246. regulator-min-microvolt = <1050000>;
  247. regulator-max-microvolt = <1050000>;
  248. };
  249. ldo2_reg: ldo2 {
  250. regulator-name = "vdd_sata,avdd_plle";
  251. regulator-min-microvolt = <1050000>;
  252. regulator-max-microvolt = <1050000>;
  253. };
  254. /* LDO3 is not connected to anything */
  255. ldo4_reg: ldo4 {
  256. regulator-name = "vdd_rtc";
  257. regulator-min-microvolt = <1200000>;
  258. regulator-max-microvolt = <1200000>;
  259. regulator-always-on;
  260. };
  261. ldo5_reg: ldo5 {
  262. regulator-name = "vddio_sdmmc,avdd_vdac";
  263. regulator-min-microvolt = <3300000>;
  264. regulator-max-microvolt = <3300000>;
  265. regulator-always-on;
  266. };
  267. ldo6_reg: ldo6 {
  268. regulator-name = "avdd_dsi_csi,pwrdet_mipi";
  269. regulator-min-microvolt = <1200000>;
  270. regulator-max-microvolt = <1200000>;
  271. };
  272. ldo7_reg: ldo7 {
  273. regulator-name = "vdd_pllm,x,u,a_p_c_s";
  274. regulator-min-microvolt = <1200000>;
  275. regulator-max-microvolt = <1200000>;
  276. regulator-always-on;
  277. };
  278. ldo8_reg: ldo8 {
  279. regulator-name = "vdd_ddr_hs";
  280. regulator-min-microvolt = <1000000>;
  281. regulator-max-microvolt = <1000000>;
  282. regulator-always-on;
  283. };
  284. };
  285. };
  286. temperature-sensor@4c {
  287. compatible = "onnn,nct1008";
  288. reg = <0x4c>;
  289. vcc-supply = <&sys_3v3_reg>;
  290. interrupt-parent = <&gpio>;
  291. interrupts = <TEGRA_GPIO(CC, 2) IRQ_TYPE_LEVEL_LOW>;
  292. };
  293. tps62361@60 {
  294. compatible = "ti,tps62361";
  295. reg = <0x60>;
  296. regulator-name = "tps62361-vout";
  297. regulator-min-microvolt = <500000>;
  298. regulator-max-microvolt = <1500000>;
  299. regulator-boot-on;
  300. regulator-always-on;
  301. ti,vsel0-state-high;
  302. ti,vsel1-state-high;
  303. };
  304. };
  305. spi@7000da00 {
  306. status = "okay";
  307. spi-max-frequency = <25000000>;
  308. spi-flash@1 {
  309. compatible = "winbond,w25q32";
  310. reg = <1>;
  311. spi-max-frequency = <20000000>;
  312. };
  313. };
  314. pmc@7000e400 {
  315. status = "okay";
  316. nvidia,invert-interrupt;
  317. nvidia,suspend-mode = <1>;
  318. nvidia,cpu-pwr-good-time = <2000>;
  319. nvidia,cpu-pwr-off-time = <200>;
  320. nvidia,core-pwr-good-time = <3845 3845>;
  321. nvidia,core-pwr-off-time = <0>;
  322. nvidia,core-power-req-active-high;
  323. nvidia,sys-clock-req-active-high;
  324. };
  325. ahub@70080000 {
  326. i2s@70080400 {
  327. status = "okay";
  328. };
  329. };
  330. sdhci@78000000 {
  331. status = "okay";
  332. cd-gpios = <&gpio TEGRA_GPIO(I, 5) GPIO_ACTIVE_LOW>;
  333. wp-gpios = <&gpio TEGRA_GPIO(T, 3) GPIO_ACTIVE_HIGH>;
  334. power-gpios = <&gpio TEGRA_GPIO(D, 7) GPIO_ACTIVE_HIGH>;
  335. bus-width = <4>;
  336. };
  337. sdhci@78000600 {
  338. status = "okay";
  339. bus-width = <8>;
  340. non-removable;
  341. };
  342. usb@7d008000 {
  343. status = "okay";
  344. };
  345. usb-phy@7d008000 {
  346. vbus-supply = <&usb3_vbus_reg>;
  347. status = "okay";
  348. };
  349. backlight: backlight {
  350. compatible = "pwm-backlight";
  351. enable-gpios = <&gpio TEGRA_GPIO(H, 2) GPIO_ACTIVE_HIGH>;
  352. power-supply = <&vdd_bl_reg>;
  353. pwms = <&pwm 0 5000000>;
  354. brightness-levels = <0 4 8 16 32 64 128 255>;
  355. default-brightness-level = <6>;
  356. };
  357. clocks {
  358. compatible = "simple-bus";
  359. #address-cells = <1>;
  360. #size-cells = <0>;
  361. clk32k_in: clock@0 {
  362. compatible = "fixed-clock";
  363. reg=<0>;
  364. #clock-cells = <0>;
  365. clock-frequency = <32768>;
  366. };
  367. };
  368. panel: panel {
  369. compatible = "chunghwa,claa101wb01", "simple-panel";
  370. ddc-i2c-bus = <&panelddc>;
  371. power-supply = <&vdd_pnl1_reg>;
  372. enable-gpios = <&gpio TEGRA_GPIO(L, 2) GPIO_ACTIVE_HIGH>;
  373. backlight = <&backlight>;
  374. };
  375. regulators {
  376. compatible = "simple-bus";
  377. #address-cells = <1>;
  378. #size-cells = <0>;
  379. vdd_ac_bat_reg: regulator@0 {
  380. compatible = "regulator-fixed";
  381. reg = <0>;
  382. regulator-name = "vdd_ac_bat";
  383. regulator-min-microvolt = <5000000>;
  384. regulator-max-microvolt = <5000000>;
  385. regulator-always-on;
  386. };
  387. cam_1v8_reg: regulator@1 {
  388. compatible = "regulator-fixed";
  389. reg = <1>;
  390. regulator-name = "cam_1v8";
  391. regulator-min-microvolt = <1800000>;
  392. regulator-max-microvolt = <1800000>;
  393. enable-active-high;
  394. gpio = <&gpio TEGRA_GPIO(BB, 4) GPIO_ACTIVE_HIGH>;
  395. vin-supply = <&vio_reg>;
  396. };
  397. cp_5v_reg: regulator@2 {
  398. compatible = "regulator-fixed";
  399. reg = <2>;
  400. regulator-name = "cp_5v";
  401. regulator-min-microvolt = <5000000>;
  402. regulator-max-microvolt = <5000000>;
  403. regulator-boot-on;
  404. regulator-always-on;
  405. enable-active-high;
  406. gpio = <&pmic 0 GPIO_ACTIVE_HIGH>;
  407. };
  408. emmc_3v3_reg: regulator@3 {
  409. compatible = "regulator-fixed";
  410. reg = <3>;
  411. regulator-name = "emmc_3v3";
  412. regulator-min-microvolt = <3300000>;
  413. regulator-max-microvolt = <3300000>;
  414. regulator-always-on;
  415. regulator-boot-on;
  416. enable-active-high;
  417. gpio = <&gpio TEGRA_GPIO(D, 1) GPIO_ACTIVE_HIGH>;
  418. vin-supply = <&sys_3v3_reg>;
  419. };
  420. modem_3v3_reg: regulator@4 {
  421. compatible = "regulator-fixed";
  422. reg = <4>;
  423. regulator-name = "modem_3v3";
  424. regulator-min-microvolt = <3300000>;
  425. regulator-max-microvolt = <3300000>;
  426. enable-active-high;
  427. gpio = <&gpio TEGRA_GPIO(D, 6) GPIO_ACTIVE_HIGH>;
  428. };
  429. pex_hvdd_3v3_reg: regulator@5 {
  430. compatible = "regulator-fixed";
  431. reg = <5>;
  432. regulator-name = "pex_hvdd_3v3";
  433. regulator-min-microvolt = <3300000>;
  434. regulator-max-microvolt = <3300000>;
  435. enable-active-high;
  436. gpio = <&gpio TEGRA_GPIO(L, 7) GPIO_ACTIVE_HIGH>;
  437. vin-supply = <&sys_3v3_reg>;
  438. };
  439. vdd_cam1_ldo_reg: regulator@6 {
  440. compatible = "regulator-fixed";
  441. reg = <6>;
  442. regulator-name = "vdd_cam1_ldo";
  443. regulator-min-microvolt = <2800000>;
  444. regulator-max-microvolt = <2800000>;
  445. enable-active-high;
  446. gpio = <&gpio TEGRA_GPIO(R, 6) GPIO_ACTIVE_HIGH>;
  447. vin-supply = <&sys_3v3_reg>;
  448. };
  449. vdd_cam2_ldo_reg: regulator@7 {
  450. compatible = "regulator-fixed";
  451. reg = <7>;
  452. regulator-name = "vdd_cam2_ldo";
  453. regulator-min-microvolt = <2800000>;
  454. regulator-max-microvolt = <2800000>;
  455. enable-active-high;
  456. gpio = <&gpio TEGRA_GPIO(R, 7) GPIO_ACTIVE_HIGH>;
  457. vin-supply = <&sys_3v3_reg>;
  458. };
  459. vdd_cam3_ldo_reg: regulator@8 {
  460. compatible = "regulator-fixed";
  461. reg = <8>;
  462. regulator-name = "vdd_cam3_ldo";
  463. regulator-min-microvolt = <3300000>;
  464. regulator-max-microvolt = <3300000>;
  465. enable-active-high;
  466. gpio = <&gpio TEGRA_GPIO(S, 0) GPIO_ACTIVE_HIGH>;
  467. vin-supply = <&sys_3v3_reg>;
  468. };
  469. vdd_com_reg: regulator@9 {
  470. compatible = "regulator-fixed";
  471. reg = <9>;
  472. regulator-name = "vdd_com";
  473. regulator-min-microvolt = <3300000>;
  474. regulator-max-microvolt = <3300000>;
  475. regulator-always-on;
  476. regulator-boot-on;
  477. enable-active-high;
  478. gpio = <&gpio TEGRA_GPIO(D, 0) GPIO_ACTIVE_HIGH>;
  479. vin-supply = <&sys_3v3_reg>;
  480. };
  481. vdd_fuse_3v3_reg: regulator@10 {
  482. compatible = "regulator-fixed";
  483. reg = <10>;
  484. regulator-name = "vdd_fuse_3v3";
  485. regulator-min-microvolt = <3300000>;
  486. regulator-max-microvolt = <3300000>;
  487. enable-active-high;
  488. gpio = <&gpio TEGRA_GPIO(L, 6) GPIO_ACTIVE_HIGH>;
  489. vin-supply = <&sys_3v3_reg>;
  490. };
  491. vdd_pnl1_reg: regulator@11 {
  492. compatible = "regulator-fixed";
  493. reg = <11>;
  494. regulator-name = "vdd_pnl1";
  495. regulator-min-microvolt = <3300000>;
  496. regulator-max-microvolt = <3300000>;
  497. regulator-always-on;
  498. regulator-boot-on;
  499. enable-active-high;
  500. gpio = <&gpio TEGRA_GPIO(L, 4) GPIO_ACTIVE_HIGH>;
  501. vin-supply = <&sys_3v3_reg>;
  502. };
  503. vdd_vid_reg: regulator@12 {
  504. compatible = "regulator-fixed";
  505. reg = <12>;
  506. regulator-name = "vddio_vid";
  507. regulator-min-microvolt = <5000000>;
  508. regulator-max-microvolt = <5000000>;
  509. enable-active-high;
  510. gpio = <&gpio TEGRA_GPIO(T, 0) GPIO_ACTIVE_HIGH>;
  511. gpio-open-drain;
  512. vin-supply = <&vdd_5v0_reg>;
  513. };
  514. };
  515. sound {
  516. compatible = "nvidia,tegra-audio-wm8903-cardhu",
  517. "nvidia,tegra-audio-wm8903";
  518. nvidia,model = "NVIDIA Tegra Cardhu";
  519. nvidia,audio-routing =
  520. "Headphone Jack", "HPOUTR",
  521. "Headphone Jack", "HPOUTL",
  522. "Int Spk", "ROP",
  523. "Int Spk", "RON",
  524. "Int Spk", "LOP",
  525. "Int Spk", "LON",
  526. "Mic Jack", "MICBIAS",
  527. "IN1L", "Mic Jack";
  528. nvidia,i2s-controller = <&tegra_i2s1>;
  529. nvidia,audio-codec = <&wm8903>;
  530. nvidia,spkr-en-gpios = <&wm8903 2 GPIO_ACTIVE_HIGH>;
  531. nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(W, 2)
  532. GPIO_ACTIVE_HIGH>;
  533. clocks = <&tegra_car TEGRA30_CLK_PLL_A>,
  534. <&tegra_car TEGRA30_CLK_PLL_A_OUT0>,
  535. <&tegra_car TEGRA30_CLK_EXTERN1>;
  536. clock-names = "pll_a", "pll_a_out0", "mclk";
  537. };
  538. };