vexpress-v2m-rs1.dtsi 10 KB

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  1. /*
  2. * ARM Ltd. Versatile Express
  3. *
  4. * Motherboard Express uATX
  5. * V2M-P1
  6. *
  7. * HBI-0190D
  8. *
  9. * RS1 memory map ("ARM Cortex-A Series memory map" in the board's
  10. * Technical Reference Manual)
  11. *
  12. * WARNING! The hardware described in this file is independent from the
  13. * original variant (vexpress-v2m.dtsi), but there is a strong
  14. * correspondence between the two configurations.
  15. *
  16. * TAKE CARE WHEN MAINTAINING THIS FILE TO PROPAGATE ANY RELEVANT
  17. * CHANGES TO vexpress-v2m.dtsi!
  18. */
  19. motherboard {
  20. model = "V2M-P1";
  21. arm,hbi = <0x190>;
  22. arm,vexpress,site = <0>;
  23. arm,v2m-memory-map = "rs1";
  24. compatible = "arm,vexpress,v2m-p1", "simple-bus";
  25. #address-cells = <2>; /* SMB chipselect number and offset */
  26. #size-cells = <1>;
  27. #interrupt-cells = <1>;
  28. ranges;
  29. flash@0,00000000 {
  30. compatible = "arm,vexpress-flash", "cfi-flash";
  31. reg = <0 0x00000000 0x04000000>,
  32. <4 0x00000000 0x04000000>;
  33. bank-width = <4>;
  34. };
  35. psram@1,00000000 {
  36. compatible = "arm,vexpress-psram", "mtd-ram";
  37. reg = <1 0x00000000 0x02000000>;
  38. bank-width = <4>;
  39. };
  40. v2m_video_ram: vram@2,00000000 {
  41. compatible = "arm,vexpress-vram";
  42. reg = <2 0x00000000 0x00800000>;
  43. };
  44. ethernet@2,02000000 {
  45. compatible = "smsc,lan9118", "smsc,lan9115";
  46. reg = <2 0x02000000 0x10000>;
  47. interrupts = <15>;
  48. phy-mode = "mii";
  49. reg-io-width = <4>;
  50. smsc,irq-active-high;
  51. smsc,irq-push-pull;
  52. vdd33a-supply = <&v2m_fixed_3v3>;
  53. vddvario-supply = <&v2m_fixed_3v3>;
  54. };
  55. usb@2,03000000 {
  56. compatible = "nxp,usb-isp1761";
  57. reg = <2 0x03000000 0x20000>;
  58. interrupts = <16>;
  59. port1-otg;
  60. };
  61. iofpga@3,00000000 {
  62. compatible = "arm,amba-bus", "simple-bus";
  63. #address-cells = <1>;
  64. #size-cells = <1>;
  65. ranges = <0 3 0 0x200000>;
  66. v2m_sysreg: sysreg@010000 {
  67. compatible = "arm,vexpress-sysreg";
  68. reg = <0x010000 0x1000>;
  69. v2m_led_gpios: sys_led@08 {
  70. compatible = "arm,vexpress-sysreg,sys_led";
  71. gpio-controller;
  72. #gpio-cells = <2>;
  73. };
  74. v2m_mmc_gpios: sys_mci@48 {
  75. compatible = "arm,vexpress-sysreg,sys_mci";
  76. gpio-controller;
  77. #gpio-cells = <2>;
  78. };
  79. v2m_flash_gpios: sys_flash@4c {
  80. compatible = "arm,vexpress-sysreg,sys_flash";
  81. gpio-controller;
  82. #gpio-cells = <2>;
  83. };
  84. };
  85. v2m_sysctl: sysctl@020000 {
  86. compatible = "arm,sp810", "arm,primecell";
  87. reg = <0x020000 0x1000>;
  88. clocks = <&v2m_refclk32khz>, <&v2m_refclk1mhz>, <&smbclk>;
  89. clock-names = "refclk", "timclk", "apb_pclk";
  90. #clock-cells = <1>;
  91. clock-output-names = "timerclken0", "timerclken1", "timerclken2", "timerclken3";
  92. };
  93. /* PCI-E I2C bus */
  94. v2m_i2c_pcie: i2c@030000 {
  95. compatible = "arm,versatile-i2c";
  96. reg = <0x030000 0x1000>;
  97. #address-cells = <1>;
  98. #size-cells = <0>;
  99. pcie-switch@60 {
  100. compatible = "idt,89hpes32h8";
  101. reg = <0x60>;
  102. };
  103. };
  104. aaci@040000 {
  105. compatible = "arm,pl041", "arm,primecell";
  106. reg = <0x040000 0x1000>;
  107. interrupts = <11>;
  108. clocks = <&smbclk>;
  109. clock-names = "apb_pclk";
  110. };
  111. mmci@050000 {
  112. compatible = "arm,pl180", "arm,primecell";
  113. reg = <0x050000 0x1000>;
  114. interrupts = <9 10>;
  115. cd-gpios = <&v2m_mmc_gpios 0 0>;
  116. wp-gpios = <&v2m_mmc_gpios 1 0>;
  117. max-frequency = <12000000>;
  118. vmmc-supply = <&v2m_fixed_3v3>;
  119. clocks = <&v2m_clk24mhz>, <&smbclk>;
  120. clock-names = "mclk", "apb_pclk";
  121. };
  122. kmi@060000 {
  123. compatible = "arm,pl050", "arm,primecell";
  124. reg = <0x060000 0x1000>;
  125. interrupts = <12>;
  126. clocks = <&v2m_clk24mhz>, <&smbclk>;
  127. clock-names = "KMIREFCLK", "apb_pclk";
  128. };
  129. kmi@070000 {
  130. compatible = "arm,pl050", "arm,primecell";
  131. reg = <0x070000 0x1000>;
  132. interrupts = <13>;
  133. clocks = <&v2m_clk24mhz>, <&smbclk>;
  134. clock-names = "KMIREFCLK", "apb_pclk";
  135. };
  136. v2m_serial0: uart@090000 {
  137. compatible = "arm,pl011", "arm,primecell";
  138. reg = <0x090000 0x1000>;
  139. interrupts = <5>;
  140. clocks = <&v2m_oscclk2>, <&smbclk>;
  141. clock-names = "uartclk", "apb_pclk";
  142. };
  143. v2m_serial1: uart@0a0000 {
  144. compatible = "arm,pl011", "arm,primecell";
  145. reg = <0x0a0000 0x1000>;
  146. interrupts = <6>;
  147. clocks = <&v2m_oscclk2>, <&smbclk>;
  148. clock-names = "uartclk", "apb_pclk";
  149. };
  150. v2m_serial2: uart@0b0000 {
  151. compatible = "arm,pl011", "arm,primecell";
  152. reg = <0x0b0000 0x1000>;
  153. interrupts = <7>;
  154. clocks = <&v2m_oscclk2>, <&smbclk>;
  155. clock-names = "uartclk", "apb_pclk";
  156. };
  157. v2m_serial3: uart@0c0000 {
  158. compatible = "arm,pl011", "arm,primecell";
  159. reg = <0x0c0000 0x1000>;
  160. interrupts = <8>;
  161. clocks = <&v2m_oscclk2>, <&smbclk>;
  162. clock-names = "uartclk", "apb_pclk";
  163. };
  164. wdt@0f0000 {
  165. compatible = "arm,sp805", "arm,primecell";
  166. reg = <0x0f0000 0x1000>;
  167. interrupts = <0>;
  168. clocks = <&v2m_refclk32khz>, <&smbclk>;
  169. clock-names = "wdogclk", "apb_pclk";
  170. };
  171. v2m_timer01: timer@110000 {
  172. compatible = "arm,sp804", "arm,primecell";
  173. reg = <0x110000 0x1000>;
  174. interrupts = <2>;
  175. clocks = <&v2m_sysctl 0>, <&v2m_sysctl 1>, <&smbclk>;
  176. clock-names = "timclken1", "timclken2", "apb_pclk";
  177. };
  178. v2m_timer23: timer@120000 {
  179. compatible = "arm,sp804", "arm,primecell";
  180. reg = <0x120000 0x1000>;
  181. interrupts = <3>;
  182. clocks = <&v2m_sysctl 2>, <&v2m_sysctl 3>, <&smbclk>;
  183. clock-names = "timclken1", "timclken2", "apb_pclk";
  184. };
  185. /* DVI I2C bus */
  186. v2m_i2c_dvi: i2c@160000 {
  187. compatible = "arm,versatile-i2c";
  188. reg = <0x160000 0x1000>;
  189. #address-cells = <1>;
  190. #size-cells = <0>;
  191. dvi-transmitter@39 {
  192. compatible = "sil,sii9022-tpi", "sil,sii9022";
  193. reg = <0x39>;
  194. };
  195. dvi-transmitter@60 {
  196. compatible = "sil,sii9022-cpi", "sil,sii9022";
  197. reg = <0x60>;
  198. };
  199. };
  200. rtc@170000 {
  201. compatible = "arm,pl031", "arm,primecell";
  202. reg = <0x170000 0x1000>;
  203. interrupts = <4>;
  204. clocks = <&smbclk>;
  205. clock-names = "apb_pclk";
  206. };
  207. compact-flash@1a0000 {
  208. compatible = "arm,vexpress-cf", "ata-generic";
  209. reg = <0x1a0000 0x100
  210. 0x1a0100 0xf00>;
  211. reg-shift = <2>;
  212. };
  213. clcd@1f0000 {
  214. compatible = "arm,pl111", "arm,primecell";
  215. reg = <0x1f0000 0x1000>;
  216. interrupt-names = "combined";
  217. interrupts = <14>;
  218. clocks = <&v2m_oscclk1>, <&smbclk>;
  219. clock-names = "clcdclk", "apb_pclk";
  220. memory-region = <&v2m_video_ram>;
  221. max-memory-bandwidth = <50350000>; /* 16bpp @ 25.175MHz */
  222. port {
  223. v2m_clcd_pads: endpoint {
  224. remote-endpoint = <&v2m_clcd_panel>;
  225. arm,pl11x,tft-r0g0b0-pads = <0 8 16>;
  226. };
  227. };
  228. panel {
  229. compatible = "panel-dpi";
  230. port {
  231. v2m_clcd_panel: endpoint {
  232. remote-endpoint = <&v2m_clcd_pads>;
  233. };
  234. };
  235. panel-timing {
  236. clock-frequency = <25175000>;
  237. hactive = <640>;
  238. hback-porch = <40>;
  239. hfront-porch = <24>;
  240. hsync-len = <96>;
  241. vactive = <480>;
  242. vback-porch = <32>;
  243. vfront-porch = <11>;
  244. vsync-len = <2>;
  245. };
  246. };
  247. };
  248. };
  249. v2m_fixed_3v3: fixedregulator@0 {
  250. compatible = "regulator-fixed";
  251. regulator-name = "3V3";
  252. regulator-min-microvolt = <3300000>;
  253. regulator-max-microvolt = <3300000>;
  254. regulator-always-on;
  255. };
  256. v2m_clk24mhz: clk24mhz {
  257. compatible = "fixed-clock";
  258. #clock-cells = <0>;
  259. clock-frequency = <24000000>;
  260. clock-output-names = "v2m:clk24mhz";
  261. };
  262. v2m_refclk1mhz: refclk1mhz {
  263. compatible = "fixed-clock";
  264. #clock-cells = <0>;
  265. clock-frequency = <1000000>;
  266. clock-output-names = "v2m:refclk1mhz";
  267. };
  268. v2m_refclk32khz: refclk32khz {
  269. compatible = "fixed-clock";
  270. #clock-cells = <0>;
  271. clock-frequency = <32768>;
  272. clock-output-names = "v2m:refclk32khz";
  273. };
  274. leds {
  275. compatible = "gpio-leds";
  276. user@1 {
  277. label = "v2m:green:user1";
  278. gpios = <&v2m_led_gpios 0 0>;
  279. linux,default-trigger = "heartbeat";
  280. };
  281. user@2 {
  282. label = "v2m:green:user2";
  283. gpios = <&v2m_led_gpios 1 0>;
  284. linux,default-trigger = "mmc0";
  285. };
  286. user@3 {
  287. label = "v2m:green:user3";
  288. gpios = <&v2m_led_gpios 2 0>;
  289. linux,default-trigger = "cpu0";
  290. };
  291. user@4 {
  292. label = "v2m:green:user4";
  293. gpios = <&v2m_led_gpios 3 0>;
  294. linux,default-trigger = "cpu1";
  295. };
  296. user@5 {
  297. label = "v2m:green:user5";
  298. gpios = <&v2m_led_gpios 4 0>;
  299. linux,default-trigger = "cpu2";
  300. };
  301. user@6 {
  302. label = "v2m:green:user6";
  303. gpios = <&v2m_led_gpios 5 0>;
  304. linux,default-trigger = "cpu3";
  305. };
  306. user@7 {
  307. label = "v2m:green:user7";
  308. gpios = <&v2m_led_gpios 6 0>;
  309. linux,default-trigger = "cpu4";
  310. };
  311. user@8 {
  312. label = "v2m:green:user8";
  313. gpios = <&v2m_led_gpios 7 0>;
  314. linux,default-trigger = "cpu5";
  315. };
  316. };
  317. mcc {
  318. compatible = "arm,vexpress,config-bus";
  319. arm,vexpress,config-bridge = <&v2m_sysreg>;
  320. osc@0 {
  321. /* MCC static memory clock */
  322. compatible = "arm,vexpress-osc";
  323. arm,vexpress-sysreg,func = <1 0>;
  324. freq-range = <25000000 60000000>;
  325. #clock-cells = <0>;
  326. clock-output-names = "v2m:oscclk0";
  327. };
  328. v2m_oscclk1: osc@1 {
  329. /* CLCD clock */
  330. compatible = "arm,vexpress-osc";
  331. arm,vexpress-sysreg,func = <1 1>;
  332. freq-range = <23750000 65000000>;
  333. #clock-cells = <0>;
  334. clock-output-names = "v2m:oscclk1";
  335. };
  336. v2m_oscclk2: osc@2 {
  337. /* IO FPGA peripheral clock */
  338. compatible = "arm,vexpress-osc";
  339. arm,vexpress-sysreg,func = <1 2>;
  340. freq-range = <24000000 24000000>;
  341. #clock-cells = <0>;
  342. clock-output-names = "v2m:oscclk2";
  343. };
  344. volt@0 {
  345. /* Logic level voltage */
  346. compatible = "arm,vexpress-volt";
  347. arm,vexpress-sysreg,func = <2 0>;
  348. regulator-name = "VIO";
  349. regulator-always-on;
  350. label = "VIO";
  351. };
  352. temp@0 {
  353. /* MCC internal operating temperature */
  354. compatible = "arm,vexpress-temp";
  355. arm,vexpress-sysreg,func = <4 0>;
  356. label = "MCC";
  357. };
  358. reset@0 {
  359. compatible = "arm,vexpress-reset";
  360. arm,vexpress-sysreg,func = <5 0>;
  361. };
  362. muxfpga@0 {
  363. compatible = "arm,vexpress-muxfpga";
  364. arm,vexpress-sysreg,func = <7 0>;
  365. };
  366. shutdown@0 {
  367. compatible = "arm,vexpress-shutdown";
  368. arm,vexpress-sysreg,func = <8 0>;
  369. };
  370. reboot@0 {
  371. compatible = "arm,vexpress-reboot";
  372. arm,vexpress-sysreg,func = <9 0>;
  373. };
  374. dvimode@0 {
  375. compatible = "arm,vexpress-dvimode";
  376. arm,vexpress-sysreg,func = <11 0>;
  377. };
  378. };
  379. };