vexpress-v2m.dtsi 10 KB

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  1. /*
  2. * ARM Ltd. Versatile Express
  3. *
  4. * Motherboard Express uATX
  5. * V2M-P1
  6. *
  7. * HBI-0190D
  8. *
  9. * Original memory map ("Legacy memory map" in the board's
  10. * Technical Reference Manual)
  11. *
  12. * WARNING! The hardware described in this file is independent from the
  13. * RS1 variant (vexpress-v2m-rs1.dtsi), but there is a strong
  14. * correspondence between the two configurations.
  15. *
  16. * TAKE CARE WHEN MAINTAINING THIS FILE TO PROPAGATE ANY RELEVANT
  17. * CHANGES TO vexpress-v2m-rs1.dtsi!
  18. */
  19. motherboard {
  20. model = "V2M-P1";
  21. arm,hbi = <0x190>;
  22. arm,vexpress,site = <0>;
  23. compatible = "arm,vexpress,v2m-p1", "simple-bus";
  24. #address-cells = <2>; /* SMB chipselect number and offset */
  25. #size-cells = <1>;
  26. #interrupt-cells = <1>;
  27. ranges;
  28. flash@0,00000000 {
  29. compatible = "arm,vexpress-flash", "cfi-flash";
  30. reg = <0 0x00000000 0x04000000>,
  31. <1 0x00000000 0x04000000>;
  32. bank-width = <4>;
  33. };
  34. psram@2,00000000 {
  35. compatible = "arm,vexpress-psram", "mtd-ram";
  36. reg = <2 0x00000000 0x02000000>;
  37. bank-width = <4>;
  38. };
  39. v2m_video_ram: vram@3,00000000 {
  40. compatible = "arm,vexpress-vram";
  41. reg = <3 0x00000000 0x00800000>;
  42. };
  43. ethernet@3,02000000 {
  44. compatible = "smsc,lan9118", "smsc,lan9115";
  45. reg = <3 0x02000000 0x10000>;
  46. interrupts = <15>;
  47. phy-mode = "mii";
  48. reg-io-width = <4>;
  49. smsc,irq-active-high;
  50. smsc,irq-push-pull;
  51. vdd33a-supply = <&v2m_fixed_3v3>;
  52. vddvario-supply = <&v2m_fixed_3v3>;
  53. };
  54. usb@3,03000000 {
  55. compatible = "nxp,usb-isp1761";
  56. reg = <3 0x03000000 0x20000>;
  57. interrupts = <16>;
  58. port1-otg;
  59. };
  60. iofpga@7,00000000 {
  61. compatible = "arm,amba-bus", "simple-bus";
  62. #address-cells = <1>;
  63. #size-cells = <1>;
  64. ranges = <0 7 0 0x20000>;
  65. v2m_sysreg: sysreg@00000 {
  66. compatible = "arm,vexpress-sysreg";
  67. reg = <0x00000 0x1000>;
  68. v2m_led_gpios: sys_led@08 {
  69. compatible = "arm,vexpress-sysreg,sys_led";
  70. gpio-controller;
  71. #gpio-cells = <2>;
  72. };
  73. v2m_mmc_gpios: sys_mci@48 {
  74. compatible = "arm,vexpress-sysreg,sys_mci";
  75. gpio-controller;
  76. #gpio-cells = <2>;
  77. };
  78. v2m_flash_gpios: sys_flash@4c {
  79. compatible = "arm,vexpress-sysreg,sys_flash";
  80. gpio-controller;
  81. #gpio-cells = <2>;
  82. };
  83. };
  84. v2m_sysctl: sysctl@01000 {
  85. compatible = "arm,sp810", "arm,primecell";
  86. reg = <0x01000 0x1000>;
  87. clocks = <&v2m_refclk32khz>, <&v2m_refclk1mhz>, <&smbclk>;
  88. clock-names = "refclk", "timclk", "apb_pclk";
  89. #clock-cells = <1>;
  90. clock-output-names = "timerclken0", "timerclken1", "timerclken2", "timerclken3";
  91. };
  92. /* PCI-E I2C bus */
  93. v2m_i2c_pcie: i2c@02000 {
  94. compatible = "arm,versatile-i2c";
  95. reg = <0x02000 0x1000>;
  96. #address-cells = <1>;
  97. #size-cells = <0>;
  98. pcie-switch@60 {
  99. compatible = "idt,89hpes32h8";
  100. reg = <0x60>;
  101. };
  102. };
  103. aaci@04000 {
  104. compatible = "arm,pl041", "arm,primecell";
  105. reg = <0x04000 0x1000>;
  106. interrupts = <11>;
  107. clocks = <&smbclk>;
  108. clock-names = "apb_pclk";
  109. };
  110. mmci@05000 {
  111. compatible = "arm,pl180", "arm,primecell";
  112. reg = <0x05000 0x1000>;
  113. interrupts = <9 10>;
  114. cd-gpios = <&v2m_mmc_gpios 0 0>;
  115. wp-gpios = <&v2m_mmc_gpios 1 0>;
  116. max-frequency = <12000000>;
  117. vmmc-supply = <&v2m_fixed_3v3>;
  118. clocks = <&v2m_clk24mhz>, <&smbclk>;
  119. clock-names = "mclk", "apb_pclk";
  120. };
  121. kmi@06000 {
  122. compatible = "arm,pl050", "arm,primecell";
  123. reg = <0x06000 0x1000>;
  124. interrupts = <12>;
  125. clocks = <&v2m_clk24mhz>, <&smbclk>;
  126. clock-names = "KMIREFCLK", "apb_pclk";
  127. };
  128. kmi@07000 {
  129. compatible = "arm,pl050", "arm,primecell";
  130. reg = <0x07000 0x1000>;
  131. interrupts = <13>;
  132. clocks = <&v2m_clk24mhz>, <&smbclk>;
  133. clock-names = "KMIREFCLK", "apb_pclk";
  134. };
  135. v2m_serial0: uart@09000 {
  136. compatible = "arm,pl011", "arm,primecell";
  137. reg = <0x09000 0x1000>;
  138. interrupts = <5>;
  139. clocks = <&v2m_oscclk2>, <&smbclk>;
  140. clock-names = "uartclk", "apb_pclk";
  141. };
  142. v2m_serial1: uart@0a000 {
  143. compatible = "arm,pl011", "arm,primecell";
  144. reg = <0x0a000 0x1000>;
  145. interrupts = <6>;
  146. clocks = <&v2m_oscclk2>, <&smbclk>;
  147. clock-names = "uartclk", "apb_pclk";
  148. };
  149. v2m_serial2: uart@0b000 {
  150. compatible = "arm,pl011", "arm,primecell";
  151. reg = <0x0b000 0x1000>;
  152. interrupts = <7>;
  153. clocks = <&v2m_oscclk2>, <&smbclk>;
  154. clock-names = "uartclk", "apb_pclk";
  155. };
  156. v2m_serial3: uart@0c000 {
  157. compatible = "arm,pl011", "arm,primecell";
  158. reg = <0x0c000 0x1000>;
  159. interrupts = <8>;
  160. clocks = <&v2m_oscclk2>, <&smbclk>;
  161. clock-names = "uartclk", "apb_pclk";
  162. };
  163. wdt@0f000 {
  164. compatible = "arm,sp805", "arm,primecell";
  165. reg = <0x0f000 0x1000>;
  166. interrupts = <0>;
  167. clocks = <&v2m_refclk32khz>, <&smbclk>;
  168. clock-names = "wdogclk", "apb_pclk";
  169. };
  170. v2m_timer01: timer@11000 {
  171. compatible = "arm,sp804", "arm,primecell";
  172. reg = <0x11000 0x1000>;
  173. interrupts = <2>;
  174. clocks = <&v2m_sysctl 0>, <&v2m_sysctl 1>, <&smbclk>;
  175. clock-names = "timclken1", "timclken2", "apb_pclk";
  176. };
  177. v2m_timer23: timer@12000 {
  178. compatible = "arm,sp804", "arm,primecell";
  179. reg = <0x12000 0x1000>;
  180. interrupts = <3>;
  181. clocks = <&v2m_sysctl 2>, <&v2m_sysctl 3>, <&smbclk>;
  182. clock-names = "timclken1", "timclken2", "apb_pclk";
  183. };
  184. /* DVI I2C bus */
  185. v2m_i2c_dvi: i2c@16000 {
  186. compatible = "arm,versatile-i2c";
  187. reg = <0x16000 0x1000>;
  188. #address-cells = <1>;
  189. #size-cells = <0>;
  190. dvi-transmitter@39 {
  191. compatible = "sil,sii9022-tpi", "sil,sii9022";
  192. reg = <0x39>;
  193. };
  194. dvi-transmitter@60 {
  195. compatible = "sil,sii9022-cpi", "sil,sii9022";
  196. reg = <0x60>;
  197. };
  198. };
  199. rtc@17000 {
  200. compatible = "arm,pl031", "arm,primecell";
  201. reg = <0x17000 0x1000>;
  202. interrupts = <4>;
  203. clocks = <&smbclk>;
  204. clock-names = "apb_pclk";
  205. };
  206. compact-flash@1a000 {
  207. compatible = "arm,vexpress-cf", "ata-generic";
  208. reg = <0x1a000 0x100
  209. 0x1a100 0xf00>;
  210. reg-shift = <2>;
  211. };
  212. clcd@1f000 {
  213. compatible = "arm,pl111", "arm,primecell";
  214. reg = <0x1f000 0x1000>;
  215. interrupt-names = "combined";
  216. interrupts = <14>;
  217. clocks = <&v2m_oscclk1>, <&smbclk>;
  218. clock-names = "clcdclk", "apb_pclk";
  219. memory-region = <&v2m_video_ram>;
  220. max-memory-bandwidth = <50350000>; /* 16bpp @ 25.175MHz */
  221. port {
  222. v2m_clcd_pads: endpoint {
  223. remote-endpoint = <&v2m_clcd_panel>;
  224. arm,pl11x,tft-r0g0b0-pads = <0 8 16>;
  225. };
  226. };
  227. panel {
  228. compatible = "panel-dpi";
  229. port {
  230. v2m_clcd_panel: endpoint {
  231. remote-endpoint = <&v2m_clcd_pads>;
  232. };
  233. };
  234. panel-timing {
  235. clock-frequency = <25175000>;
  236. hactive = <640>;
  237. hback-porch = <40>;
  238. hfront-porch = <24>;
  239. hsync-len = <96>;
  240. vactive = <480>;
  241. vback-porch = <32>;
  242. vfront-porch = <11>;
  243. vsync-len = <2>;
  244. };
  245. };
  246. };
  247. };
  248. v2m_fixed_3v3: fixedregulator@0 {
  249. compatible = "regulator-fixed";
  250. regulator-name = "3V3";
  251. regulator-min-microvolt = <3300000>;
  252. regulator-max-microvolt = <3300000>;
  253. regulator-always-on;
  254. };
  255. v2m_clk24mhz: clk24mhz {
  256. compatible = "fixed-clock";
  257. #clock-cells = <0>;
  258. clock-frequency = <24000000>;
  259. clock-output-names = "v2m:clk24mhz";
  260. };
  261. v2m_refclk1mhz: refclk1mhz {
  262. compatible = "fixed-clock";
  263. #clock-cells = <0>;
  264. clock-frequency = <1000000>;
  265. clock-output-names = "v2m:refclk1mhz";
  266. };
  267. v2m_refclk32khz: refclk32khz {
  268. compatible = "fixed-clock";
  269. #clock-cells = <0>;
  270. clock-frequency = <32768>;
  271. clock-output-names = "v2m:refclk32khz";
  272. };
  273. leds {
  274. compatible = "gpio-leds";
  275. user@1 {
  276. label = "v2m:green:user1";
  277. gpios = <&v2m_led_gpios 0 0>;
  278. linux,default-trigger = "heartbeat";
  279. };
  280. user@2 {
  281. label = "v2m:green:user2";
  282. gpios = <&v2m_led_gpios 1 0>;
  283. linux,default-trigger = "mmc0";
  284. };
  285. user@3 {
  286. label = "v2m:green:user3";
  287. gpios = <&v2m_led_gpios 2 0>;
  288. linux,default-trigger = "cpu0";
  289. };
  290. user@4 {
  291. label = "v2m:green:user4";
  292. gpios = <&v2m_led_gpios 3 0>;
  293. linux,default-trigger = "cpu1";
  294. };
  295. user@5 {
  296. label = "v2m:green:user5";
  297. gpios = <&v2m_led_gpios 4 0>;
  298. linux,default-trigger = "cpu2";
  299. };
  300. user@6 {
  301. label = "v2m:green:user6";
  302. gpios = <&v2m_led_gpios 5 0>;
  303. linux,default-trigger = "cpu3";
  304. };
  305. user@7 {
  306. label = "v2m:green:user7";
  307. gpios = <&v2m_led_gpios 6 0>;
  308. linux,default-trigger = "cpu4";
  309. };
  310. user@8 {
  311. label = "v2m:green:user8";
  312. gpios = <&v2m_led_gpios 7 0>;
  313. linux,default-trigger = "cpu5";
  314. };
  315. };
  316. mcc {
  317. compatible = "arm,vexpress,config-bus";
  318. arm,vexpress,config-bridge = <&v2m_sysreg>;
  319. osc@0 {
  320. /* MCC static memory clock */
  321. compatible = "arm,vexpress-osc";
  322. arm,vexpress-sysreg,func = <1 0>;
  323. freq-range = <25000000 60000000>;
  324. #clock-cells = <0>;
  325. clock-output-names = "v2m:oscclk0";
  326. };
  327. v2m_oscclk1: osc@1 {
  328. /* CLCD clock */
  329. compatible = "arm,vexpress-osc";
  330. arm,vexpress-sysreg,func = <1 1>;
  331. freq-range = <23750000 65000000>;
  332. #clock-cells = <0>;
  333. clock-output-names = "v2m:oscclk1";
  334. };
  335. v2m_oscclk2: osc@2 {
  336. /* IO FPGA peripheral clock */
  337. compatible = "arm,vexpress-osc";
  338. arm,vexpress-sysreg,func = <1 2>;
  339. freq-range = <24000000 24000000>;
  340. #clock-cells = <0>;
  341. clock-output-names = "v2m:oscclk2";
  342. };
  343. volt@0 {
  344. /* Logic level voltage */
  345. compatible = "arm,vexpress-volt";
  346. arm,vexpress-sysreg,func = <2 0>;
  347. regulator-name = "VIO";
  348. regulator-always-on;
  349. label = "VIO";
  350. };
  351. temp@0 {
  352. /* MCC internal operating temperature */
  353. compatible = "arm,vexpress-temp";
  354. arm,vexpress-sysreg,func = <4 0>;
  355. label = "MCC";
  356. };
  357. reset@0 {
  358. compatible = "arm,vexpress-reset";
  359. arm,vexpress-sysreg,func = <5 0>;
  360. };
  361. muxfpga@0 {
  362. compatible = "arm,vexpress-muxfpga";
  363. arm,vexpress-sysreg,func = <7 0>;
  364. };
  365. shutdown@0 {
  366. compatible = "arm,vexpress-shutdown";
  367. arm,vexpress-sysreg,func = <8 0>;
  368. };
  369. reboot@0 {
  370. compatible = "arm,vexpress-reboot";
  371. arm,vexpress-sysreg,func = <9 0>;
  372. };
  373. dvimode@0 {
  374. compatible = "arm,vexpress-dvimode";
  375. arm,vexpress-sysreg,func = <11 0>;
  376. };
  377. };
  378. };